Index: include/llvm/Target/TargetRegisterInfo.h =================================================================== --- include/llvm/Target/TargetRegisterInfo.h +++ include/llvm/Target/TargetRegisterInfo.h @@ -469,6 +469,10 @@ return nullptr; } + /// Return all the call-preserved register masks defined for this target. + virtual ArrayRef getRegMasks() const = 0; + virtual ArrayRef getRegMaskNames() const = 0; + /// getReservedRegs - Returns a bitset indexed by physical register number /// indicating if a register is a special register that has particular uses /// and should be considered unavailable at all times, e.g. SP, RA. This is Index: utils/TableGen/RegisterInfoEmitter.cpp =================================================================== --- utils/TableGen/RegisterInfoEmitter.cpp +++ utils/TableGen/RegisterInfoEmitter.cpp @@ -1094,6 +1094,8 @@ << "const TargetRegisterClass *RC) const override;\n" << " const int *getRegUnitPressureSets(" << "unsigned RegUnit) const override;\n" + << " ArrayRef getRegMaskNames() const override;\n" + << " ArrayRef getRegMasks() const override;\n" << "};\n\n"; const auto &RegisterClasses = RegBank.getRegClasses(); @@ -1445,6 +1447,26 @@ } OS << "\n\n"; + OS << "ArrayRef " << ClassName + << "::getRegMasks() const {\n"; + OS << " static const uint32_t *Masks[] = {\n"; + for (Record *CSRSet : CSRSets) + OS << " " << CSRSet->getName() << "_RegMask, \n"; + OS << " nullptr\n };\n"; + OS << " return ArrayRef(Masks, (size_t)" << CSRSets.size() + << ");\n"; + OS << "}\n\n"; + + OS << "ArrayRef " << ClassName + << "::getRegMaskNames() const {\n"; + OS << " static const char *Names[] = {\n"; + for (Record *CSRSet : CSRSets) + OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; + OS << " nullptr\n };\n"; + OS << " return ArrayRef(Names, (size_t)" << CSRSets.size() + << ");\n"; + OS << "}\n\n"; + OS << "} // End llvm namespace\n"; OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; }