Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -221,6 +221,15 @@
   bool expandUlw(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandRotation(MCInst &Inst, SMLoc IDLoc,
+                      SmallVectorImpl<MCInst> &Instructions);
+  bool expandRotationImm(MCInst &Inst, SMLoc IDLoc,
+                         SmallVectorImpl<MCInst> &Instructions);
+  bool expandDRotation(MCInst &Inst, SMLoc IDLoc,
+                       SmallVectorImpl<MCInst> &Instructions);
+  bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
+                          SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
@@ -1962,6 +1971,14 @@
   case Mips::Ulhu:
   case Mips::Ulw:
   case Mips::NORImm:
+  case Mips::ROL:
+  case Mips::ROLImm:
+  case Mips::ROR:
+  case Mips::RORImm:
+  case Mips::DROL:
+  case Mips::DROLImm:
+  case Mips::DROR:
+  case Mips::DRORImm:
     return true;
   case Mips::ADDi:
   case Mips::ADDiu:
@@ -2086,6 +2103,18 @@
   case Mips::SLTiu:
   case Mips::XORi:
     return expandAliasImmediate(Inst, IDLoc, Instructions);
+  case Mips::ROL:
+  case Mips::ROR:
+    return expandRotation(Inst, IDLoc, Instructions);
+  case Mips::ROLImm:
+  case Mips::RORImm:
+    return expandRotationImm(Inst, IDLoc, Instructions);
+  case Mips::DROL:
+  case Mips::DROR:
+    return expandDRotation(Inst, IDLoc, Instructions);
+  case Mips::DROLImm:
+  case Mips::DRORImm:
+    return expandDRotationImm(Inst, IDLoc, Instructions);
   }
 }
 
@@ -3229,6 +3258,454 @@
   return true;
 }
 
+bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc,
+                                   SmallVectorImpl<MCInst> &Instructions) {
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  unsigned TReg = Inst.getOperand(2).getReg();
+
+  unsigned FirstShift = Mips::NOP;
+  unsigned SecondShift = Mips::NOP;
+
+  MCInst TmpInst;
+    
+  if (hasMips32r2() || hasMips32r6() || hasMips64r2() || hasMips64r6()) {
+    if (DReg == SReg) {
+      ATReg = getATReg(Inst.getLoc());
+      if (!ATReg)
+        return true;
+    }
+
+    if (Inst.getOpcode() == Mips::ROL) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::SUBu);
+      if (ATReg)
+        TmpInst.addOperand(MCOperand::createReg(ATReg));
+      else
+        TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      TmpInst.addOperand(MCOperand::createReg(TReg));
+      Instructions.push_back(TmpInst);
+
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::ROTRV);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      if (ATReg)
+        TmpInst.addOperand(MCOperand::createReg(ATReg));
+      else
+        TmpInst.addOperand(MCOperand::createReg(DReg));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+
+    if (Inst.getOpcode() == Mips::ROR) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::ROTRV);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      TmpInst.addOperand(MCOperand::createReg(TReg));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+    return true;
+  }
+
+  if (hasMips32() || hasMips64()) {
+    switch (Inst.getOpcode()) {
+    default:
+      llvm_unreachable("unexpected instruction opcode");
+    case Mips::ROL:
+      FirstShift = Mips::SRLV;
+      SecondShift = Mips::SLLV;
+      break;
+    case Mips::ROR:
+      FirstShift = Mips::SLLV;
+      SecondShift = Mips::SRLV;
+    break;
+    }
+
+    ATReg = getATReg(Inst.getLoc());
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(Mips::SUBu);
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+    TmpInst.addOperand(MCOperand::createReg(TReg));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(FirstShift);
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(SecondShift);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createReg(TReg));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(Mips::OR);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    Instructions.push_back(TmpInst);
+
+    return false;
+  }
+  return true;
+}
+
+bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
+                                      SmallVectorImpl<MCInst> &Instructions) {
+
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  int64_t ImmValue = Inst.getOperand(2).getImm();
+
+  unsigned FirstShift = Mips::NOP;
+  unsigned SecondShift = Mips::NOP;
+
+  MCInst TmpInst;
+
+  if (hasMips32r2() || hasMips32r6() || hasMips64r2() || hasMips64r6()) {
+
+    if (Inst.getOpcode() == Mips::ROLImm) {
+      uint64_t MaxShift = 32;
+
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::ROTR);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      if (ImmValue == 0)
+        TmpInst.addOperand(MCOperand::createImm(ImmValue));
+      else
+        TmpInst.addOperand(MCOperand::createImm(MaxShift - ImmValue));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+
+    if (Inst.getOpcode() == Mips::RORImm) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::ROTR);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      TmpInst.addOperand(MCOperand::createImm(ImmValue));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+    return true;
+  }
+
+  if (hasMips32() || hasMips64()) {
+
+    if (ImmValue == 0) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::SRL);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      TmpInst.addOperand(MCOperand::createImm(0));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+
+    switch (Inst.getOpcode()) {
+    default:
+      llvm_unreachable("unexpected instruction opcode");
+    case Mips::ROLImm:
+      FirstShift = Mips::SLL;
+      SecondShift = Mips::SRL;
+      break;
+    case Mips::RORImm:
+      FirstShift = Mips::SRL;
+      SecondShift = Mips::SLL;
+      break;
+    }
+
+    ATReg = getATReg(Inst.getLoc());
+    if (!ATReg)
+      return true;
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(FirstShift);
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createImm(ImmValue));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(SecondShift);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createImm(32 - ImmValue));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(Mips::OR);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    Instructions.push_back(TmpInst);
+
+    return false;
+  }
+  return true;
+}
+
+bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc,
+                                    SmallVectorImpl<MCInst> &Instructions) {
+
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  unsigned TReg = Inst.getOperand(2).getReg();
+
+  unsigned FirstShift = Mips::NOP;
+  unsigned SecondShift = Mips::NOP;
+
+  MCInst TmpInst;
+
+  if (hasMips64r2() || hasMips64r6()) {
+
+    if (DReg == SReg) {
+      ATReg = getATReg(Inst.getLoc());
+      if (!ATReg)
+        return true;
+    }
+
+    if (Inst.getOpcode() == Mips::DROL) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::DSUBu);
+      if (ATReg)
+        TmpInst.addOperand(MCOperand::createReg(ATReg));
+      else
+        TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      TmpInst.addOperand(MCOperand::createReg(TReg));
+      Instructions.push_back(TmpInst);
+
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::DROTRV);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      if (ATReg)
+        TmpInst.addOperand(MCOperand::createReg(ATReg));
+      else
+        TmpInst.addOperand(MCOperand::createReg(DReg));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+
+    if (Inst.getOpcode() == Mips::DROR) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::DROTRV);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      TmpInst.addOperand(MCOperand::createReg(TReg));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+    return true;
+  }
+
+  if (hasMips64()) {
+    switch (Inst.getOpcode()) {
+    default:
+      llvm_unreachable("unexpected instruction opcode");
+    case Mips::DROL:
+    case Mips::DROLImm:
+      FirstShift = Mips::DSRLV;
+      SecondShift = Mips::DSLLV;
+      break;
+    case Mips::DROR:
+    case Mips::DRORImm:
+      FirstShift = Mips::DSLLV;
+      SecondShift = Mips::DSRLV;
+      break;
+    }
+
+    ATReg = getATReg(Inst.getLoc());
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(Mips::DSUBu);
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+    TmpInst.addOperand(MCOperand::createReg(TReg));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(FirstShift);
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(SecondShift);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createReg(TReg));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(Mips::OR);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    Instructions.push_back(TmpInst);
+    
+    return false;
+  }
+  return true;
+}
+
+bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
+                                       SmallVectorImpl<MCInst> &Instructions) {
+
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  int64_t ImmValue = Inst.getOperand(2).getImm() % 64;
+
+  unsigned FirstShift = Mips::NOP;
+  unsigned SecondShift = Mips::NOP;
+
+  MCInst TmpInst;
+
+  if (hasMips64r2() || hasMips64r6()) {
+
+    unsigned FinalOpcode = Mips::NOP;
+    if (ImmValue == 0)
+      FinalOpcode = Mips::DROTR;
+    else if (ImmValue % 32 == 0)
+      FinalOpcode = Mips::DROTR32;
+    else if ((ImmValue >= 1) && (ImmValue <= 32)) {
+      if (Inst.getOpcode() == Mips::DROLImm)
+        FinalOpcode = Mips::DROTR32;
+      else
+        FinalOpcode = Mips::DROTR;
+    } else if (ImmValue >= 33) {
+      if (Inst.getOpcode() == Mips::DROLImm)
+        FinalOpcode = Mips::DROTR;
+      else
+        FinalOpcode = Mips::DROTR32;
+    }
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(FinalOpcode);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    if (Inst.getOpcode() == Mips::DROLImm)
+      TmpInst.addOperand(MCOperand::createImm((32 - ImmValue % 32) % 32));
+    else
+      TmpInst.addOperand(MCOperand::createImm(ImmValue % 32));
+    Instructions.push_back(TmpInst);
+    return false;
+  }
+
+  if (hasMips64()) {
+
+    if (ImmValue == 0) {
+      TmpInst.clear();
+      TmpInst.setLoc(Inst.getLoc());
+      TmpInst.setOpcode(Mips::DSRL);
+      TmpInst.addOperand(MCOperand::createReg(DReg));
+      TmpInst.addOperand(MCOperand::createReg(SReg));
+      TmpInst.addOperand(MCOperand::createImm(0));
+      Instructions.push_back(TmpInst);
+      return false;
+    }
+
+    switch (Inst.getOpcode()) {
+    default:
+      llvm_unreachable("unexpected instruction opcode");
+    case Mips::DROLImm:
+      if ((ImmValue >= 1) && (ImmValue <= 31)) {
+        FirstShift = Mips::DSLL;
+        SecondShift = Mips::DSRL32;
+      }
+      if (ImmValue == 32) {
+        FirstShift = Mips::DSLL32;
+        SecondShift = Mips::DSRL32;
+      }
+      if ((ImmValue >= 33) && (ImmValue <= 63)) {
+        FirstShift = Mips::DSLL32;
+        SecondShift = Mips::DSRL;
+      }
+      break;
+    case Mips::DRORImm:
+      if ((ImmValue >= 1) && (ImmValue <= 31)) {
+        FirstShift = Mips::DSRL;
+        SecondShift = Mips::DSLL32;
+      }
+      if (ImmValue == 32) {
+        FirstShift = Mips::DSRL32;
+        SecondShift = Mips::DSLL32;
+      }
+      if ((ImmValue >= 33) && (ImmValue <= 63)) {
+        FirstShift = Mips::DSRL32;
+        SecondShift = Mips::DSLL;
+      }
+      break;
+    }
+
+    ATReg = getATReg(Inst.getLoc());
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(FirstShift);
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createImm(ImmValue % 32));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(SecondShift);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(SReg));
+    TmpInst.addOperand(MCOperand::createImm((32 - ImmValue % 32) % 32));
+    Instructions.push_back(TmpInst);
+
+    TmpInst.clear();
+    TmpInst.setLoc(Inst.getLoc());
+    TmpInst.setOpcode(Mips::OR);
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(DReg));
+    TmpInst.addOperand(MCOperand::createReg(ATReg));
+    Instructions.push_back(TmpInst);
+
+    return false;
+  }
+  return true;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   if (hasShortDelaySlot)
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1636,6 +1636,50 @@
 def PREF :  MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
             INSN_MIPS3_32_NOT_32R6_64R6;
 
+def ROL : MipsAsmPseudoInst<(outs),
+                            (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+                            "rol\t$rs, $rt, $rd">;
+def ROLImm : MipsAsmPseudoInst<(outs),
+                               (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+                               "rol\t$rs, $rt, $imm">;
+def : MipsInstAlias<"rol $rd, $rs",
+                    (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"rol $rd, $imm",
+                    (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
+
+def ROR : MipsAsmPseudoInst<(outs),
+                            (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+                            "ror\t$rs, $rt, $rd">;
+def RORImm : MipsAsmPseudoInst<(outs),
+                               (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+                               "ror\t$rs, $rt, $imm">;
+def : MipsInstAlias<"ror $rd, $rs",
+                    (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"ror $rd, $imm",
+                    (RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
+
+def DROL : MipsAsmPseudoInst<(outs),
+                             (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+                             "drol\t$rs, $rt, $rd">, ISA_MIPS64;
+def DROLImm : MipsAsmPseudoInst<(outs),
+                                (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+                                "drol\t$rs, $rt, $imm">, ISA_MIPS64;
+def : MipsInstAlias<"drol $rd, $rs",
+                    (DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
+def : MipsInstAlias<"drol $rd, $imm",
+                    (DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
+
+def DROR : MipsAsmPseudoInst<(outs),
+                             (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+                             "dror\t$rs, $rt, $rd">, ISA_MIPS64;
+def DRORImm : MipsAsmPseudoInst<(outs),
+                                (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+                                "dror\t$rs, $rt, $imm">, ISA_MIPS64;
+def : MipsInstAlias<"dror $rd, $rs",
+                    (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
+def : MipsInstAlias<"dror $rd, $imm",
+                    (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
Index: test/MC/Mips/rotations32-bad.s
===================================================================
--- test/MC/Mips/rotations32-bad.s
+++ test/MC/Mips/rotations32-bad.s
@@ -0,0 +1,31 @@
+# RUN: not llvm-mc  %s -arch=mips -mcpu=mips32 -show-encoding 2> %t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc  %s -arch=mips -mcpu=mips32r2 -show-encoding 2> %t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc  %s -arch=mips -mcpu=mips32r3 -show-encoding 2> %t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc  %s -arch=mips -mcpu=mips32r5 -show-encoding 2> %t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc  %s -arch=mips -mcpu=mips32r6 -show-encoding 2> %t1
+# RUN: FileCheck %s < %t1
+
+  .text
+foo:
+
+  drol $4,$5
+# CHECK:        [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+  drol $4,$5,$6
+# CHECK:        [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+  drol $4,0
+# CHECK:        [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+  drol $4,$5,0
+# CHECK:        [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+
+  dror $4,$5
+# CHECK:        [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  dror $4,$5,$6
+# CHECK:        [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  dror $4,0
+# CHECK:        [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
+  dror $4,$5,0
+# CHECK:        [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
Index: test/MC/Mips/rotations32.s
===================================================================
--- test/MC/Mips/rotations32.s
+++ test/MC/Mips/rotations32.s
@@ -0,0 +1,87 @@
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips32 -show-encoding | FileCheck %s -check-prefix=CHECK-32
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips32r2 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips32r3 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips32r5 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips32r6 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+
+  .text
+foo:
+  rol $4,$5
+# CHECK-32:     negu    $1, $5              # encoding: [0x00,0x05,0x08,0x23]
+# CHECK-32:     srlv    $1, $4, $1          # encoding: [0x00,0x24,0x08,0x06]
+# CHECK-32:     sllv    $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x04]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    negu    $1, $5              # encoding: [0x00,0x05,0x08,0x23]
+# CHECK-32R:    rotrv   $4, $4, $1          # encoding: [0x00,0x24,0x20,0x46]
+  rol $4,$5,$6
+# CHECK-32:     negu    $1, $6              # encoding: [0x00,0x06,0x08,0x23]
+# CHECK-32:     srlv    $1, $5, $1          # encoding: [0x00,0x25,0x08,0x06]
+# CHECK-32:     sllv    $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x04]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    negu    $4, $6              # encoding: [0x00,0x06,0x20,0x23]
+# CHECK-32R:    rotrv   $4, $5, $4          # encoding: [0x00,0x85,0x20,0x46]
+  rol $4,0
+# CHECK-32:     srl     $4, $4, 0           # encoding: [0x00,0x04,0x20,0x02]
+# CHECK-32R:    rotr    $4, $4, 0           # encoding: [0x00,0x24,0x20,0x02]
+  rol $4,$5,0
+# CHECK-32:     srl     $4, $5, 0           # encoding: [0x00,0x05,0x20,0x02]
+# CHECK-32R:    rotr    $4, $5, 0           # encoding: [0x00,0x25,0x20,0x02]
+  rol $4,1
+# CHECK-32:     sll     $1, $4, 1           # encoding: [0x00,0x04,0x08,0x40]
+# CHECK-32:     srl     $4, $4, 31          # encoding: [0x00,0x04,0x27,0xc2]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $4, 31          # encoding: [0x00,0x24,0x27,0xc2]
+  rol $4,$5,1
+# CHECK-32:     sll     $1, $5, 1           # encoding: [0x00,0x05,0x08,0x40]
+# CHECK-32:     srl     $4, $5, 31          # encoding: [0x00,0x05,0x27,0xc2]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $5, 31          # encoding: [0x00,0x25,0x27,0xc2]
+  rol $4,2
+# CHECK-32:     sll     $1, $4, 2           # encoding: [0x00,0x04,0x08,0x80]
+# CHECK-32:     srl     $4, $4, 30          # encoding: [0x00,0x04,0x27,0x82]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $4, 30          # encoding: [0x00,0x24,0x27,0x82]
+  rol $4,$5,2
+# CHECK-32:     sll     $1, $5, 2           # encoding: [0x00,0x05,0x08,0x80]
+# CHECK-32:     srl     $4, $5, 30          # encoding: [0x00,0x05,0x27,0x82]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $5, 30          # encoding: [0x00,0x25,0x27,0x82]
+
+  ror $4,$5
+# CHECK-32:     negu    $1, $5              # encoding: [0x00,0x05,0x08,0x23]
+# CHECK-32:     sllv    $1, $4, $1          # encoding: [0x00,0x24,0x08,0x04]
+# CHECK-32:     srlv    $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x06]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotrv   $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x46]
+  ror $4,$5,$6
+# CHECK-32:     negu    $1, $6              # encoding: [0x00,0x06,0x08,0x23]
+# CHECK-32:     sllv    $1, $5, $1          # encoding: [0x00,0x25,0x08,0x04]
+# CHECK-32:     srlv    $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x06]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotrv   $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x46]
+  ror $4,0
+# CHECK-32:     srl     $4, $4, 0           # encoding: [0x00,0x04,0x20,0x02]
+# CHECK-32R:    rotr    $4, $4, 0           # encoding: [0x00,0x24,0x20,0x02]
+  ror $4,$5,0
+# CHECK-32:     srl     $4, $5, 0           # encoding: [0x00,0x05,0x20,0x02]
+# CHECK-32R:    rotr    $4, $5, 0           # encoding: [0x00,0x25,0x20,0x02]
+  ror $4,1
+# CHECK-32:     srl     $1, $4, 1           # encoding: [0x00,0x04,0x08,0x42]
+# CHECK-32:     sll     $4, $4, 31          # encoding: [0x00,0x04,0x27,0xc0]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $4, 1           # encoding: [0x00,0x24,0x20,0x42]
+  ror $4,$5,1
+# CHECK-32:     srl     $1, $5, 1           # encoding: [0x00,0x05,0x08,0x42]
+# CHECK-32:     sll     $4, $5, 31          # encoding: [0x00,0x05,0x27,0xc0]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $5, 1           # encoding: [0x00,0x25,0x20,0x42]
+  ror $4,2
+# CHECK-32:     srl     $1, $4, 2           # encoding: [0x00,0x04,0x08,0x82]
+# CHECK-32:     sll     $4, $4, 30          # encoding: [0x00,0x04,0x27,0x80]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $4, 2           # encoding: [0x00,0x24,0x20,0x82]
+  ror $4,$5,2
+# CHECK-32:     srl     $1, $5, 2           # encoding: [0x00,0x05,0x08,0x82]
+# CHECK-32:     sll     $4, $5, 30          # encoding: [0x00,0x05,0x27,0x80]
+# CHECK-32:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-32R:    rotr    $4, $5, 2           # encoding: [0x00,0x25,0x20,0x82]
Index: test/MC/Mips/rotations64.s
===================================================================
--- test/MC/Mips/rotations64.s
+++ test/MC/Mips/rotations64.s
@@ -0,0 +1,238 @@
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips64 -show-encoding | FileCheck %s -check-prefix=CHECK-64
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips64r2 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips64r3 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips64r5 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc  %s -arch=mips -mcpu=mips64r6 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+
+  .text
+foo:
+  rol $4,$5
+# CHECK-64:     subu    $1, $zero, $5       # encoding: [0x00,0x05,0x08,0x23]
+# CHECK-64:     srlv    $1, $4, $1          # encoding: [0x00,0x24,0x08,0x06]
+# CHECK-64:     sllv    $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x04]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    subu    $1, $zero, $5       # encoding: [0x00,0x05,0x08,0x23]
+# CHECK-64R:    rotrv   $4, $4, $1          # encoding: [0x00,0x24,0x20,0x46]
+  rol $4,$5,$6
+# CHECK-64:     subu    $1, $zero, $6       # encoding: [0x00,0x06,0x08,0x23]
+# CHECK-64:     srlv    $1, $5, $1          # encoding: [0x00,0x25,0x08,0x06]
+# CHECK-64:     sllv    $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x04]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    negu    $4, $6              # encoding: [0x00,0x06,0x20,0x23]
+# CHECK-64R:    rotrv   $4, $5, $4          # encoding: [0x00,0x85,0x20,0x46]
+  rol $4,0
+# CHECK-64:     srl     $4, $4, 0           # encoding: [0x00,0x04,0x20,0x02]
+# CHECK-64R:    rotr    $4, $4, 0           # encoding: [0x00,0x24,0x20,0x02]
+  rol $4,$5,0
+# CHECK-64:     srl     $4, $5, 0           # encoding: [0x00,0x05,0x20,0x02]
+# CHECK-64R:    rotr    $4, $5, 0           # encoding: [0x00,0x25,0x20,0x02]
+  rol $4,1
+# CHECK-64:     sll     $1, $4, 1           # encoding: [0x00,0x04,0x08,0x40]
+# CHECK-64:     srl     $4, $4, 31          # encoding: [0x00,0x04,0x27,0xc2]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $4, 31          # encoding: [0x00,0x24,0x27,0xc2]
+  rol $4,$5,1
+# CHECK-64:     sll     $1, $5, 1           # encoding: [0x00,0x05,0x08,0x40]
+# CHECK-64:     srl     $4, $5, 31          # encoding: [0x00,0x05,0x27,0xc2]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $5, 31          # encoding: [0x00,0x25,0x27,0xc2]
+  rol $4,2
+# CHECK-64:     sll     $1, $4, 2           # encoding: [0x00,0x04,0x08,0x80]
+# CHECK-64:     srl     $4, $4, 30          # encoding: [0x00,0x04,0x27,0x82]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $4, 30          # encoding: [0x00,0x24,0x27,0x82]
+  rol $4,$5,2
+# CHECK-64:     sll     $1, $5, 2           # encoding: [0x00,0x05,0x08,0x80]
+# CHECK-64:     srl     $4, $5, 30          # encoding: [0x00,0x05,0x27,0x82]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $5, 30          # encoding: [0x00,0x25,0x27,0x82]
+
+  ror $4,$5
+# CHECK-64:     subu    $1, $zero, $5       # encoding: [0x00,0x05,0x08,0x23]
+# CHECK-64:     sllv    $1, $4, $1          # encoding: [0x00,0x24,0x08,0x04]
+# CHECK-64:     srlv    $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x06]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotrv   $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x46]
+  ror $4,$5,$6
+# CHECK-64:     subu    $1, $zero, $6       # encoding: [0x00,0x06,0x08,0x23]
+# CHECK-64:     sllv    $1, $5, $1          # encoding: [0x00,0x25,0x08,0x04]
+# CHECK-64:     srlv    $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x06]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotrv   $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x46]
+  ror $4,0
+# CHECK-64:     srl     $4, $4, 0           # encoding: [0x00,0x04,0x20,0x02]
+# CHECK-64R:    rotr    $4, $4, 0           # encoding: [0x00,0x24,0x20,0x02]
+  ror $4,$5,0
+# CHECK-64:     srl     $4, $5, 0           # encoding: [0x00,0x05,0x20,0x02]
+# CHECK-64R:    rotr    $4, $5, 0           # encoding: [0x00,0x25,0x20,0x02]
+  ror $4,1
+# CHECK-64:     srl     $1, $4, 1           # encoding: [0x00,0x04,0x08,0x42]
+# CHECK-64:     sll     $4, $4, 31          # encoding: [0x00,0x04,0x27,0xc0]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $4, 1           # encoding: [0x00,0x24,0x20,0x42]
+  ror $4,$5,1
+# CHECK-64:     srl     $1, $5, 1           # encoding: [0x00,0x05,0x08,0x42]
+# CHECK-64:     sll     $4, $5, 31          # encoding: [0x00,0x05,0x27,0xc0]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $5, 1           # encoding: [0x00,0x25,0x20,0x42]
+  ror $4,2
+# CHECK-64:     srl     $1, $4, 2           # encoding: [0x00,0x04,0x08,0x82]
+# CHECK-64:     sll     $4, $4, 30          # encoding: [0x00,0x04,0x27,0x80]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $4, 2           # encoding: [0x00,0x24,0x20,0x82]
+  ror $4,$5,2
+# CHECK-64:     srl     $1, $5, 2           # encoding: [0x00,0x05,0x08,0x82]
+# CHECK-64:     sll     $4, $5, 30          # encoding: [0x00,0x05,0x27,0x80]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    rotr    $4, $5, 2           # encoding: [0x00,0x25,0x20,0x82]
+
+  drol $4,$5
+# CHECK-64:     dsubu   $1, $zero, $5       # encoding: [0x00,0x05,0x08,0x2f]
+# CHECK-64:     dsrlv   $1, $4, $1          # encoding: [0x00,0x24,0x08,0x16]
+# CHECK-64:     dsllv   $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x14]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    dsubu   $1, $zero, $5       # encoding: [0x00,0x05,0x08,0x2f]
+# CHECK-64R:    drotrv  $4, $4, $1          # encoding: [0x00,0x24,0x20,0x56]
+  drol $4,$5,$6
+# CHECK-64:     dsubu   $1, $zero, $6       # encoding: [0x00,0x06,0x08,0x2f]
+# CHECK-64:     dsrlv   $1, $5, $1          # encoding: [0x00,0x25,0x08,0x16]
+# CHECK-64:     dsllv   $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x14]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    dsubu   $4, $zero, $6       # encoding: [0x00,0x06,0x20,0x2f]
+# CHECK-64R:    drotrv  $4, $5, $4          # encoding: [0x00,0x85,0x20,0x56]
+
+  drol $4,1
+# CHECK-64:     dsll    $1, $4, 1           # encoding: [0x00,0x04,0x08,0x78]
+# CHECK-64:     dsrl32  $4, $4, 31          # encoding: [0x00,0x04,0x27,0xfe]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $4, 31          # encoding: [0x00,0x24,0x27,0xfe]
+  drol $4,$5,0
+# CHECK-64:     dsrl    $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3a]
+# CHECK-64R:    drotr   $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3a]
+  drol $4,$5,1
+# CHECK-64:     dsll    $1, $5, 1           # encoding: [0x00,0x05,0x08,0x78]
+# CHECK-64:     dsrl32  $4, $5, 31          # encoding: [0x00,0x05,0x27,0xfe]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfe]
+  drol $4,$5,31
+# CHECK-64:     dsll    $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xf8]
+# CHECK-64:     dsrl32  $4, $5, 1           # encoding: [0x00,0x05,0x20,0x7e]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7e]
+  drol $4,$5,32
+# CHECK-64:     dsll32  $1, $5, 0           # encoding: [0x00,0x05,0x08,0x3c]
+# CHECK-64:     dsrl32  $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3e]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3e]
+  drol $4,$5,33
+# CHECK-64:     dsll32  $1, $5, 1           # encoding: [0x00,0x05,0x08,0x7c]
+# CHECK-64:     dsrl    $4, $5, 31          # encoding: [0x00,0x05,0x27,0xfa]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfa]
+  drol $4,$5,63
+# CHECK-64:     dsll32  $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xfc]
+# CHECK-64:     dsrl    $4, $5, 1           # encoding: [0x00,0x05,0x20,0x7a]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7a]
+  drol $4,$5,64
+# CHECK-64:     dsrl    $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3a]
+# CHECK-64R:    drotr   $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3a]
+  drol $4,$5,65
+# CHECK-64:     dsll    $1, $5, 1           # encoding: [0x00,0x05,0x08,0x78]
+# CHECK-64:     dsrl32  $4, $5, 31          # encoding: [0x00,0x05,0x27,0xfe]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfe]
+  drol $4,$5,95
+# CHECK-64:     dsll    $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xf8]
+# CHECK-64:     dsrl32  $4, $5, 1           # encoding: [0x00,0x05,0x20,0x7e]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7e]
+  drol $4,$5,96
+# CHECK-64:     dsll32  $1, $5, 0           # encoding: [0x00,0x05,0x08,0x3c]
+# CHECK-64:     dsrl32  $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3e]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3e]
+  drol $4,$5,97
+# CHECK-64:     dsll32  $1, $5, 1           # encoding: [0x00,0x05,0x08,0x7c]
+# CHECK-64:     dsrl    $4, $5, 31          # encoding: [0x00,0x05,0x27,0xfa]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfa]
+  drol $4,$5,127
+# CHECK-64:     dsll32  $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xfc]
+# CHECK-64:     dsrl    $4, $5, 1           # encoding: [0x00,0x05,0x20,0x7a]
+# CHECK-64:     or  $4, $4, $1              # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7a]
+
+  dror $4,$5
+# CHECK-64:     dsubu   $1, $zero, $5       # encoding: [0x00,0x05,0x08,0x2f]
+# CHECK-64:     dsllv   $1, $4, $1          # encoding: [0x00,0x24,0x08,0x14]
+# CHECK-64:     dsrlv   $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x16]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotrv  $4, $4, $5          # encoding: [0x00,0xa4,0x20,0x56]
+  dror $4,$5,$6
+# CHECK-64:     dsubu   $1, $zero, $6       # encoding: [0x00,0x06,0x08,0x2f]
+# CHECK-64:     dsllv   $1, $5, $1          # encoding: [0x00,0x25,0x08,0x14]
+# CHECK-64:     dsrlv   $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x16]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotrv  $4, $5, $6          # encoding: [0x00,0xc5,0x20,0x56]
+  dror $4,1
+# CHECK-64:     dsrl    $1, $4, 1           # encoding: [0x00,0x04,0x08,0x7a]
+# CHECK-64:     dsll32  $4, $4, 31          # encoding: [0x00,0x04,0x27,0xfc]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $4, 1           # encoding: [0x00,0x24,0x20,0x7a]
+  dror $4,$5,0
+# CHECK-64:     dsrl    $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3a]
+# CHECK-64R:    drotr   $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3a]
+  dror $4,$5,1
+# CHECK-64:     dsrl    $1, $5, 1           # encoding: [0x00,0x05,0x08,0x7a]
+# CHECK-64:     dsll32  $4, $5, 31          # encoding: [0x00,0x05,0x27,0xfc]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7a]
+  dror $4,$5,31
+# CHECK-64:     dsrl    $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xfa]
+# CHECK-64:     dsll32  $4, $5, 1           # encoding: [0x00,0x05,0x20,0x7c]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfa]
+  dror $4,$5,32
+# CHECK-64:     dsrl32  $1, $5, 0           # encoding: [0x00,0x05,0x08,0x3e]
+# CHECK-64:     dsll32  $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3c]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3e]
+  dror $4,$5,33
+# CHECK-64:     dsrl32  $1, $5, 1           # encoding: [0x00,0x05,0x08,0x7e]
+# CHECK-64:     dsll    $4, $5, 31          # encoding: [0x00,0x05,0x27,0xf8]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7e]
+  dror $4,$5,63
+# CHECK-64:     dsrl32  $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xfe]
+# CHECK-64:     dsll    $4, $5, 1           # encoding: [0x00,0x05,0x20,0x78]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfe]
+  dror $4,$5,64
+# CHECK-64:     dsrl    $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3a]
+# CHECK-64R:    drotr   $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3a]
+  dror $4,$5,65
+# CHECK-64:     dsrl    $1, $5, 1           # encoding: [0x00,0x05,0x08,0x7a]
+# CHECK-64:     dsll32  $4, $5, 31          # encoding: [0x00,0x05,0x27,0xfc]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7a]
+  dror $4,$5,95
+# CHECK-64:     dsrl    $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xfa]
+# CHECK-64:     dsll32  $4, $5, 1           # encoding: [0x00,0x05,0x20,0x7c]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr   $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfa]
+  dror $4,$5,96
+# CHECK-64:     dsrl32  $1, $5, 0           # encoding: [0x00,0x05,0x08,0x3e]
+# CHECK-64:     dsll32  $4, $5, 0           # encoding: [0x00,0x05,0x20,0x3c]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 0           # encoding: [0x00,0x25,0x20,0x3e]
+  dror $4,$5,97
+# CHECK-64:     dsrl32  $1, $5, 1           # encoding: [0x00,0x05,0x08,0x7e]
+# CHECK-64:     dsll    $4, $5, 31          # encoding: [0x00,0x05,0x27,0xf8]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 1           # encoding: [0x00,0x25,0x20,0x7e]
+  dror $4,$5,127
+# CHECK-64:     dsrl32  $1, $5, 31          # encoding: [0x00,0x05,0x0f,0xfe]
+# CHECK-64:     dsll    $4, $5, 1           # encoding: [0x00,0x05,0x20,0x78]
+# CHECK-64:     or      $4, $4, $1          # encoding: [0x00,0x81,0x20,0x25]
+# CHECK-64R:    drotr32 $4, $5, 31          # encoding: [0x00,0x25,0x27,0xfe]