diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
@@ -69,4 +69,7 @@
 
   // Set up DWARF directives
   MinInstAlignment = 4;
+
+  // Support $ as PC in inline asm
+  DollarIsPC = true;
 }
diff --git a/llvm/test/CodeGen/PowerPC/inline-asm-dollarpc.ll b/llvm/test/CodeGen/PowerPC/inline-asm-dollarpc.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/inline-asm-dollarpc.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr7 -verify-machineinstrs \
+; RUN:     -mtriple=powerpc-unknown-aix < %s  | FileCheck %s --check-prefix=IS32
+
+; RUN: llc -mcpu=pwr7 -verify-machineinstrs \
+; RUN:     -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix=IS64
+
+; RUN: llc -mcpu=pwr7 -verify-machineinstrs -no-integrated-as \
+; RUN:     -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix=NOIS
+
+define dso_local i32 @dollarpc() #0 {
+; IS32-LABEL: dollarpc:
+; IS32:       # %bb.0: # %entry
+; IS32-NEXT:    li 3, 0
+; IS32-NEXT:    stw 3, -4(1)
+; IS32-NEXT:    #APP
+; IS32-NEXT:    mfspr 5, 269
+; IS32-NEXT:    mfspr 3, 268
+; IS32-NEXT:    mfspr 4, 269
+; IS32-NEXT:    cmpw 5, 4
+; IS32-NEXT:  L..tmp0:
+; IS32-NEXT:    bne 0, L..tmp0-16
+; IS32-EMPTY:
+; IS32-NEXT:    #NO_APP
+; IS32-NEXT:    stw 3, -12(1)
+; IS32-NEXT:    stw 4, -8(1)
+; IS32-NEXT:    stw 5, -16(1)
+; IS32-NEXT:    blr
+;
+; IS64-LABEL: dollarpc:
+; IS64:       # %bb.0: # %entry
+; IS64-NEXT:    li 3, 0
+; IS64-NEXT:    stw 3, -4(1)
+; IS64-NEXT:    #APP
+; IS64-NEXT:    mfspr 4, 269
+; IS64-NEXT:    mfspr 3, 268
+; IS64-NEXT:    mfspr 5, 269
+; IS64-NEXT:    cmpw 4, 5
+; IS64-NEXT:  L..tmp0:
+; IS64-NEXT:    bne 0, L..tmp0-16
+; IS64-EMPTY:
+; IS64-NEXT:    #NO_APP
+; IS64-NEXT:    stw 3, -12(1)
+; IS64-NEXT:    rldimi 3, 5, 32, 0
+; IS64-NEXT:    stw 5, -8(1)
+; IS64-NEXT:    stw 4, -16(1)
+; IS64-NEXT:    blr
+;
+; NOIS-LABEL: dollarpc:
+; NOIS:       # %bb.0: # %entry
+; NOIS-NEXT:    li 3, 0
+; NOIS-NEXT:    stw 3, -4(1)
+; NOIS-NEXT:    #APP
+; NOIS-NEXT:    mftbu 4
+; NOIS-NEXT:  mftb 3
+; NOIS-NEXT:  mftbu 5
+; NOIS-NEXT:  cmpw 4,5
+; NOIS-NEXT:  bne $-0x10
+; NOIS-EMPTY:
+; NOIS-NEXT:    #NO_APP
+; NOIS-NEXT:    stw 3, -12(1)
+; NOIS-NEXT:    rldimi 3, 5, 32, 0
+; NOIS-NEXT:    stw 5, -8(1)
+; NOIS-NEXT:    stw 4, -16(1)
+; NOIS-NEXT:    blr
+entry:
+  %retval = alloca i32, align 4
+  %tbu = alloca i32, align 4
+  %tbl = alloca i32, align 4
+  %temp = alloca i32, align 4
+  store i32 0, i32* %retval, align 4
+  %0 = call { i32, i32, i32 } asm sideeffect "mftbu  $2\0Amftb   $0\0Amftbu  $1\0Acmpw   $2,$1\0Abne    $$-0x10\0A", "=r,=r,=r,~{cc}"()
+  %asmresult = extractvalue { i32, i32, i32 } %0, 0
+  %asmresult1 = extractvalue { i32, i32, i32 } %0, 1
+  %asmresult2 = extractvalue { i32, i32, i32 } %0, 2
+  store i32 %asmresult, i32* %tbl, align 4
+  store i32 %asmresult1, i32* %tbu, align 4
+  store i32 %asmresult2, i32* %temp, align 4
+  %1 = load i32, i32* %tbu, align 4
+  %conv = zext i32 %1 to i64
+  %shl = shl i64 %conv, 32
+  %2 = load i32, i32* %tbl, align 4
+  %conv3 = zext i32 %2 to i64
+  %or = or i64 %shl, %conv3
+  %conv4 = trunc i64 %or to i32
+  ret i32 %conv4
+}
+