diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2006,11 +2006,11 @@ // 15.3. Vector Single-Width Floating-Point Reduction Instructions defm vfredmax : RVVFloatingReductionBuiltin; defm vfredmin : RVVFloatingReductionBuiltin; -defm vfredsum : RVVFloatingReductionBuiltin; +defm vfredusum : RVVFloatingReductionBuiltin; defm vfredosum : RVVFloatingReductionBuiltin; // 15.4. Vector Widening Floating-Point Reduction Instructions -defm vfwredsum : RVVFloatingWidenReductionBuiltin; +defm vfwredusum : RVVFloatingWidenReductionBuiltin; defm vfwredosum : RVVFloatingWidenReductionBuiltin; } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c @@ -5,194 +5,212 @@ #include -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32mf2_f32m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32mf2_f32m1(vfloat32m1_t dst, - vfloat32mf2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1(vfloat32m1_t dst, + vfloat32mf2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m1_f32m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m1_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m1_f32m1(vfloat32m1_t dst, vfloat32m1_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m1_f32m1(vfloat32m1_t dst, vfloat32m1_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m2_f32m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m2_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m2_f32m1(vfloat32m1_t dst, vfloat32m2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m2_f32m1(vfloat32m1_t dst, vfloat32m2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m4_f32m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m4_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m4_f32m1(vfloat32m1_t dst, vfloat32m4_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m4_f32m1(vfloat32m1_t dst, vfloat32m4_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m8_f32m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m8_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m8_f32m1(vfloat32m1_t dst, vfloat32m8_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m1_t dst, vfloat32m8_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m1_f64m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m1_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m1_f64m1(vfloat64m1_t dst, vfloat64m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m1_f64m1(vfloat64m1_t dst, vfloat64m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m2_f64m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m2_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m2_f64m1(vfloat64m1_t dst, vfloat64m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m2_f64m1(vfloat64m1_t dst, vfloat64m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m4_f64m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m4_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m4_f64m1(vfloat64m1_t dst, vfloat64m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m4_f64m1(vfloat64m1_t dst, vfloat64m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m8_f64m1( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m8_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m8_f64m1(vfloat64m1_t dst, vfloat64m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m1_t dst, vfloat64m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32mf2_f32m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32m1_t dst, - vfloat32mf2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32m1_t dst, + vfloat32mf2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m1_f32m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m1_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t dst, - vfloat32m1_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t dst, + vfloat32m1_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m2_f32m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m2_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m1_t dst, - vfloat32m2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m1_t dst, + vfloat32m2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m4_f32m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m4_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m1_t dst, - vfloat32m4_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m1_t dst, + vfloat32m4_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m8_f32m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m8_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m1_t dst, - vfloat32m8_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m1_t dst, + vfloat32m8_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m1_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m1_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t dst, - vfloat64m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t dst, + vfloat64m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m2_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m2_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m1_t dst, - vfloat64m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m1_t dst, + vfloat64m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m4_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m4_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m1_t dst, - vfloat64m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m1_t dst, + vfloat64m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m8_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m8_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst, - vfloat64m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst, + vfloat64m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum(mask, dst, vector, scalar, vl); } // CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c @@ -5,114 +5,124 @@ #include -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1(vfloat64m1_t dst, - vfloat32mf2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat64m1_t dst, + vfloat32mf2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1(vfloat64m1_t dst, - vfloat32m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat64m1_t dst, + vfloat32m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1(vfloat64m1_t dst, - vfloat32m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat64m1_t dst, + vfloat32m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1(vfloat64m1_t dst, - vfloat32m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat64m1_t dst, + vfloat32m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1(vfloat64m1_t dst, - vfloat32m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat64m1_t dst, + vfloat32m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst, - vfloat32mf2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst, + vfloat32mf2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst, - vfloat32m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst, + vfloat32m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst, - vfloat32m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst, + vfloat32m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst, - vfloat32m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst, + vfloat32m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1_m( +// +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst, - vfloat32m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst, + vfloat32m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum(mask, dst, vector, scalar, vl); } // CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1( diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c @@ -6,194 +6,194 @@ #include -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32mf2_f32m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32mf2_f32m1(vfloat32m1_t dst, - vfloat32mf2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32mf2_f32m1(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1(vfloat32m1_t dst, + vfloat32mf2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32mf2_f32m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m1_f32m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m1_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m1_f32m1(vfloat32m1_t dst, vfloat32m1_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m1_f32m1(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m1_f32m1(vfloat32m1_t dst, vfloat32m1_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m1_f32m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m2_f32m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m2_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m2_f32m1(vfloat32m1_t dst, vfloat32m2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m2_f32m1(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m2_f32m1(vfloat32m1_t dst, vfloat32m2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m2_f32m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m4_f32m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m4_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m4_f32m1(vfloat32m1_t dst, vfloat32m4_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m4_f32m1(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m4_f32m1(vfloat32m1_t dst, vfloat32m4_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m4_f32m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m8_f32m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m8_f32m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m8_f32m1(vfloat32m1_t dst, vfloat32m8_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m8_f32m1(dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m1_t dst, vfloat32m8_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m8_f32m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m1_f64m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m1_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m1_f64m1(vfloat64m1_t dst, vfloat64m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m1_f64m1(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m1_f64m1(vfloat64m1_t dst, vfloat64m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m1_f64m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m2_f64m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m2_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m2_f64m1(vfloat64m1_t dst, vfloat64m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m2_f64m1(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m2_f64m1(vfloat64m1_t dst, vfloat64m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m2_f64m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m4_f64m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m4_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m4_f64m1(vfloat64m1_t dst, vfloat64m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m4_f64m1(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m4_f64m1(vfloat64m1_t dst, vfloat64m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m4_f64m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m8_f64m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m8_f64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m8_f64m1(vfloat64m1_t dst, vfloat64m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m8_f64m1(dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m1_t dst, vfloat64m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m8_f64m1(dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32mf2_f32m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32m1_t dst, - vfloat32mf2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32mf2_f32m1_m(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32m1_t dst, + vfloat32mf2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32mf2_f32m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m1_f32m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m1_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t dst, - vfloat32m1_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m1_f32m1_m(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t dst, + vfloat32m1_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m1_f32m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m2_f32m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m2_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m1_t dst, - vfloat32m2_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m2_f32m1_m(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m1_t dst, + vfloat32m2_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m2_f32m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m4_f32m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m4_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m1_t dst, - vfloat32m4_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m4_f32m1_m(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m1_t dst, + vfloat32m4_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m4_f32m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f32m8_f32m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f32m8_f32m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat32m1_t test_vfredsum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m1_t dst, - vfloat32m8_t vector, - vfloat32m1_t scalar, size_t vl) { - return vfredsum_vs_f32m8_f32m1_m(mask, dst, vector, scalar, vl); +vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m1_t dst, + vfloat32m8_t vector, + vfloat32m1_t scalar, size_t vl) { + return vfredusum_vs_f32m8_f32m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m1_f64m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m1_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t dst, - vfloat64m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m1_f64m1_m(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t dst, + vfloat64m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m1_f64m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m2_f64m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m2_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m1_t dst, - vfloat64m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m2_f64m1_m(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m1_t dst, + vfloat64m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m2_f64m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m4_f64m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m4_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m1_t dst, - vfloat64m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m4_f64m1_m(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m1_t dst, + vfloat64m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m4_f64m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f64m8_f64m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f64m8_f64m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat64m1_t test_vfredsum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst, - vfloat64m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfredsum_vs_f64m8_f64m1_m(mask, dst, vector, scalar, vl); +vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst, + vfloat64m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfredusum_vs_f64m8_f64m1_m(mask, dst, vector, scalar, vl); } // CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1( @@ -394,112 +394,112 @@ return vfredosum_vs_f64m8_f64m1_m(mask, dst, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16mf4_f16m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16mf4_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv4f16.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16mf4_f16m1 (vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16mf4_f16m1(dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1(vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16mf4_f16m1(dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16mf2_f16m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16mf2_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv4f16.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16mf2_f16m1 (vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16mf2_f16m1(dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1(vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16mf2_f16m1(dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m1_f16m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m1_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv4f16.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m1_f16m1 (vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m1_f16m1(dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m1_f16m1(vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m1_f16m1(dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m2_f16m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m2_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv4f16.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m2_f16m1 (vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m2_f16m1(dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m2_f16m1(vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m2_f16m1(dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m4_f16m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m4_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv4f16.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m4_f16m1 (vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m4_f16m1(dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m4_f16m1(vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m4_f16m1(dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m8_f16m1( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m8_f16m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.nxv4f16.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m8_f16m1 (vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m8_f16m1(dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m8_f16m1(vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m8_f16m1(dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16mf4_f16m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16mf4_f16m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16mf4_f16m1_m (vbool64_t mask, vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16mf4_f16m1_m(mask, dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16mf4_f16m1_m(mask, dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16mf2_f16m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16mf2_f16m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16mf2_f16m1_m (vbool32_t mask, vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16mf2_f16m1_m(mask, dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16mf2_f16m1_m(mask, dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m1_f16m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m1_f16m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m1_f16m1_m (vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m1_f16m1_m(mask, dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m1_f16m1_m(mask, dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m2_f16m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m2_f16m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m2_f16m1_m (vbool8_t mask, vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m2_f16m1_m(mask, dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m2_f16m1_m(mask, dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m4_f16m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m4_f16m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m4_f16m1_m (vbool4_t mask, vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m4_f16m1_m(mask, dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m4_f16m1_m(mask, dest, vector, scalar, vl); } -// CHECK-RV64-LABEL: @test_vfredsum_vs_f16m8_f16m1_m( +// CHECK-RV64-LABEL: @test_vfredusum_vs_f16m8_f16m1_m( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredsum_vs_f16m8_f16m1_m (vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { - return vfredsum_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl); +vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { + return vfredusum_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl); } // CHECK-RV64-LABEL: @test_vfredosum_vs_f16mf4_f16m1( @@ -507,7 +507,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1 (vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1(vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16mf4_f16m1(dest, vector, scalar, vl); } @@ -516,7 +516,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1 (vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1(vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16mf2_f16m1(dest, vector, scalar, vl); } @@ -525,7 +525,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m1_f16m1 (vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m1_f16m1(vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m1_f16m1(dest, vector, scalar, vl); } @@ -534,7 +534,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m2_f16m1 (vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m2_f16m1(vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m2_f16m1(dest, vector, scalar, vl); } @@ -543,7 +543,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m4_f16m1 (vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m4_f16m1(vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m4_f16m1(dest, vector, scalar, vl); } @@ -552,7 +552,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m8_f16m1 (vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m8_f16m1(vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m8_f16m1(dest, vector, scalar, vl); } @@ -561,7 +561,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_m (vbool64_t mask, vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16m1_t dest, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16mf4_f16m1_m(mask, dest, vector, scalar, vl); } @@ -570,7 +570,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_m (vbool32_t mask, vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16m1_t dest, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16mf2_f16m1_m(mask, dest, vector, scalar, vl); } @@ -579,7 +579,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_m (vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m1_f16m1_m(mask, dest, vector, scalar, vl); } @@ -588,7 +588,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_m (vbool8_t mask, vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m1_t dest, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m2_f16m1_m(mask, dest, vector, scalar, vl); } @@ -597,7 +597,7 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_m (vbool4_t mask, vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m1_t dest, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m4_f16m1_m(mask, dest, vector, scalar, vl); } @@ -606,6 +606,6 @@ // CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: ret [[TMP0]] // -vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m (vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { +vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) { return vfredosum_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c deleted file mode 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c +++ /dev/null @@ -1,225 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s - -#include - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1(vfloat64m1_t dst, - vfloat32mf2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32mf2_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1(vfloat64m1_t dst, - vfloat32m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m1_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1(vfloat64m1_t dst, - vfloat32m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m2_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1(vfloat64m1_t dst, - vfloat32m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m4_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv1f64.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1(vfloat64m1_t dst, - vfloat32m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m8_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst, - vfloat32mf2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32mf2_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst, - vfloat32m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m1_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst, - vfloat32m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m2_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst, - vfloat32m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m4_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.i64( [[DST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst, - vfloat32m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredsum_vs_f32m8_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16mf4_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv2f32.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16mf4_f32m1 (vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16mf4_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16mf2_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv2f32.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16mf2_f32m1 (vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16mf2_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m1_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv2f32.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m1_f32m1 (vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m1_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m2_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv2f32.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m2_f32m1 (vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m2_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m4_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv2f32.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m4_f32m1 (vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m4_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m8_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.nxv2f32.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m8_f32m1 (vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m8_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16mf4_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16mf4_f32m1_m (vbool64_t mask, vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16mf4_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16mf2_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16mf2_f32m1_m (vbool32_t mask, vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16mf2_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m1_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m1_f32m1_m (vbool16_t mask, vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m1_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m2_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m2_f32m1_m (vbool8_t mask, vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m2_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m4_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m4_f32m1_m (vbool4_t mask, vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m4_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredsum_vs_f16m8_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.i64( [[DEST:%.*]], [[VECTOR:%.*]], [[SCALAR:%.*]], [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vfloat32m1_t test_vfwredsum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredsum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl); -} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1185,11 +1185,11 @@ defm vwredsum : RISCVReduction; defm vfredosum : RISCVReduction; - defm vfredsum : RISCVReduction; + defm vfredusum : RISCVReduction; defm vfredmin : RISCVReduction; defm vfredmax : RISCVReduction; - defm vfwredsum : RISCVReduction; + defm vfwredusum : RISCVReduction; defm vfwredosum : RISCVReduction; def int_riscv_vmand: RISCVBinaryAAANoMask; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1333,11 +1333,14 @@ // Vector Single-Width Floating-Point Reduction Instructions let RVVConstraint = NoConstraint in { defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; -defm VFREDSUM : VRED_FV_V<"vfredsum", 0b000001>; +defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>; defm VFREDMAX : VRED_FV_V<"vfredmax", 0b000111>; defm VFREDMIN : VRED_FV_V<"vfredmin", 0b000101>; } // RVVConstraint = NoConstraint +def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm", + (VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; + // Vector Widening Floating-Point Reduction Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { // Set earlyclobber for following instructions for second and mask operands. @@ -1345,10 +1348,14 @@ // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>; -defm VFWREDSUM : VWRED_FV_V<"vfwredsum", 0b110001>; +defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint } // Predicates = [HasStdExtV, HasStdExtF] +def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm", + (VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; + + let Predicates = [HasStdExtV] in { // Vector Mask-Register Logical Instructions let RVVConstraint = NoConstraint in { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3981,14 +3981,14 @@ // 15.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// defm PseudoVFREDOSUM : VPseudoReductionV_VS; -defm PseudoVFREDSUM : VPseudoReductionV_VS; +defm PseudoVFREDUSUM : VPseudoReductionV_VS; defm PseudoVFREDMIN : VPseudoReductionV_VS; defm PseudoVFREDMAX : VPseudoReductionV_VS; //===----------------------------------------------------------------------===// // 15.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -defm PseudoVFWREDSUM : VPseudoReductionV_VS; +defm PseudoVFWREDUSUM : VPseudoReductionV_VS; defm PseudoVFWREDOSUM : VPseudoReductionV_VS; } // Predicates = [HasStdExtV, HasStdExtF] @@ -4646,14 +4646,14 @@ // 15.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// defm : VPatReductionV_VS<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=*/1>; -defm : VPatReductionV_VS<"int_riscv_vfredsum", "PseudoVFREDSUM", /*IsFloat=*/1>; +defm : VPatReductionV_VS<"int_riscv_vfredusum", "PseudoVFREDUSUM", /*IsFloat=*/1>; defm : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>; defm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>; //===----------------------------------------------------------------------===// // 15.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -defm : VPatReductionW_VS<"int_riscv_vfwredsum", "PseudoVFWREDSUM", /*IsFloat=*/1>; +defm : VPatReductionW_VS<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", /*IsFloat=*/1>; defm : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>; } // Predicates = [HasStdExtV, HasStdExtF] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -942,7 +942,7 @@ // 15.3. Vector Single-Width Floating-Point Reduction Instructions let Predicates = [HasStdExtV, HasStdExtF] in { defm : VPatReductionVL; -defm : VPatReductionVL; +defm : VPatReductionVL; defm : VPatReductionVL; defm : VPatReductionVL; } // Predicates = [HasStdExtV, HasStdExtF] diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll @@ -12,7 +12,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl) @@ -40,7 +40,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl) @@ -68,7 +68,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl) @@ -96,7 +96,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl) @@ -124,7 +124,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl) @@ -152,7 +152,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll @@ -45,7 +45,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v26, ft0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v25, v26 +; CHECK-NEXT: vfredusum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -82,7 +82,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v26, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v25, v26 +; CHECK-NEXT: vfredusum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -119,7 +119,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v26, ft0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v25, v26 +; CHECK-NEXT: vfredusum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -156,7 +156,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v26, v25 +; CHECK-NEXT: vfredusum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -194,7 +194,7 @@ ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV32-NEXT: vfmv.v.f v25, ft0 ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV32-NEXT: vfredsum.vs v25, v28, v25 +; RV32-NEXT: vfredusum.vs v25, v28, v25 ; RV32-NEXT: vfmv.f.s ft0, v25 ; RV32-NEXT: fadd.h fa0, fa0, ft0 ; RV32-NEXT: ret @@ -209,7 +209,7 @@ ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64-NEXT: vfmv.v.f v25, ft0 ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-NEXT: vfredsum.vs v25, v28, v25 +; RV64-NEXT: vfredusum.vs v25, v28, v25 ; RV64-NEXT: vfmv.f.s ft0, v25 ; RV64-NEXT: fadd.h fa0, fa0, ft0 ; RV64-NEXT: ret @@ -248,7 +248,7 @@ ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV32-NEXT: vfmv.v.f v25, ft0 ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV32-NEXT: vfredsum.vs v25, v8, v25 +; RV32-NEXT: vfredusum.vs v25, v8, v25 ; RV32-NEXT: vfmv.f.s ft0, v25 ; RV32-NEXT: fadd.h fa0, fa0, ft0 ; RV32-NEXT: ret @@ -263,7 +263,7 @@ ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64-NEXT: vfmv.v.f v25, ft0 ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV64-NEXT: vfredsum.vs v25, v8, v25 +; RV64-NEXT: vfredusum.vs v25, v8, v25 ; RV64-NEXT: vfmv.f.s ft0, v25 ; RV64-NEXT: fadd.h fa0, fa0, ft0 ; RV64-NEXT: ret @@ -305,7 +305,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -381,7 +381,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v26, ft0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v25, v26 +; CHECK-NEXT: vfredusum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -418,7 +418,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v26, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v25, v26 +; CHECK-NEXT: vfredusum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -455,7 +455,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v26, v25 +; CHECK-NEXT: vfredusum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -492,7 +492,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v28, v25 +; CHECK-NEXT: vfredusum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -530,7 +530,7 @@ ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vfmv.v.f v25, ft0 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV32-NEXT: vfredsum.vs v25, v8, v25 +; RV32-NEXT: vfredusum.vs v25, v8, v25 ; RV32-NEXT: vfmv.f.s ft0, v25 ; RV32-NEXT: fadd.s fa0, fa0, ft0 ; RV32-NEXT: ret @@ -545,7 +545,7 @@ ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64-NEXT: vfmv.v.f v25, ft0 ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV64-NEXT: vfredsum.vs v25, v8, v25 +; RV64-NEXT: vfredusum.vs v25, v8, v25 ; RV64-NEXT: vfmv.f.s ft0, v25 ; RV64-NEXT: fadd.s fa0, fa0, ft0 ; RV64-NEXT: ret @@ -587,7 +587,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -663,7 +663,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v26, ft0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v25, v26 +; CHECK-NEXT: vfredusum.vs v25, v25, v26 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -700,7 +700,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v26, v25 +; CHECK-NEXT: vfredusum.vs v25, v26, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -737,7 +737,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v28, v25 +; CHECK-NEXT: vfredusum.vs v25, v28, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -774,7 +774,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -814,7 +814,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll deleted file mode 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll +++ /dev/null @@ -1,692 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ -; RUN: < %s | FileCheck %s -declare @llvm.riscv.vfredsum.nxv4f16.nxv1f16( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv1f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv2f16( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv2f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv4f16( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv4f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv8f16( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv8f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv16f16( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv16f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv32f16( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv32f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv1f32( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv1f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv2f32( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv2f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv4f32( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv4f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv8f32( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv8f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv16f32( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv16f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv1f64( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv1f64( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv2f64( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv2f64( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv4f64( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv4f64( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv8f64( - , - , - , - i32); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv8f64( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1( - , - , - , - , - i32); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll deleted file mode 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll +++ /dev/null @@ -1,692 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ -; RUN: < %s | FileCheck %s -declare @llvm.riscv.vfredsum.nxv4f16.nxv1f16( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv1f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv2f16( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv2f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv4f16( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv4f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv8f16( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv8f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv16f16( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv16f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv4f16.nxv32f16( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv4f16.nxv32f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv1f32( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv1f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv2f32( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv2f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv4f32( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv4f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv8f32( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv8f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv2f32.nxv16f32( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv2f32.nxv16f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv1f64( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv1f64( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv2f64( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv2f64( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv4f64( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv4f64( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfredsum.nxv1f64.nxv8f64( - , - , - , - i64); - -define @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.nxv1f64.nxv8f64( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64( - , - , - , - , - i64); - -define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu -; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll deleted file mode 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll +++ /dev/null @@ -1,508 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ -; RUN: < %s | FileCheck %s -declare @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( - , - , - , - i32); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( - %0, - %1, - %2, - i32 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64( - , - , - , - , - i32); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64( - %0, - %1, - %2, - %3, - i32 %4) - - ret %a -} diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll deleted file mode 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll +++ /dev/null @@ -1,508 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ -; RUN: < %s | FileCheck %s -declare @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} - -declare @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( - , - , - , - i64); - -define @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9 -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( - %0, - %1, - %2, - i64 %3) - - ret %a -} - -declare @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32( - , - , - , - , - i64); - -define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu -; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t -; CHECK-NEXT: ret -entry: - %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32( - %0, - %1, - %2, - %3, - i64 %4) - - ret %a -} diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll @@ -14,7 +14,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -45,7 +45,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -75,7 +75,7 @@ ; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -105,7 +105,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -135,7 +135,7 @@ ; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -165,7 +165,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -195,7 +195,7 @@ ; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -225,7 +225,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret @@ -256,7 +256,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v25, v8, v25 ; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll @@ -12,7 +12,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.nxv1f16(half %s, %v, %m, i32 %evl) @@ -40,7 +40,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.nxv2f16(half %s, %v, %m, i32 %evl) @@ -68,7 +68,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.nxv4f16(half %s, %v, %m, i32 %evl) @@ -96,7 +96,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.nxv1f32(float %s, %v, %m, i32 %evl) @@ -124,7 +124,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.nxv2f32(float %s, %v, %m, i32 %evl) @@ -152,7 +152,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.nxv4f32(float %s, %v, %m, i32 %evl) @@ -180,7 +180,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.nxv1f64(double %s, %v, %m, i32 %evl) @@ -208,7 +208,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.nxv2f64(double %s, %v, %m, i32 %evl) @@ -236,7 +236,7 @@ ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: vfredsum.vs v25, v8, v25, v0.t +; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.nxv4f64(double %s, %v, %m, i32 %evl) diff --git a/llvm/test/MC/RISCV/rvv/aliases.s b/llvm/test/MC/RISCV/rvv/aliases.s --- a/llvm/test/MC/RISCV/rvv/aliases.s +++ b/llvm/test/MC/RISCV/rvv/aliases.s @@ -84,3 +84,9 @@ # ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02] # NO-ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02] vse1.v v8, (a0) +# ALIAS: vfredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0x04] +# NO-ALIAS: vfredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0x04] +vfredsum.vs v8, v4, v20, v0.t +# ALIAS: vfwredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0xc4] +# NO-ALIAS: vfwredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0xc4] +vfwredsum.vs v8, v4, v20, v0.t diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s --- a/llvm/test/MC/RISCV/rvv/freduction.s +++ b/llvm/test/MC/RISCV/rvv/freduction.s @@ -1,12 +1,12 @@ # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ -# RUN: --mattr=+f \ +# RUN: --mattr=+f --riscv-no-aliases \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ # RUN: --mattr=+f \ -# RUN: | llvm-objdump -d --mattr=+experimental-v --mattr=+f - \ -# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: | llvm-objdump -d --mattr=+experimental-v --mattr=+f \ +# RUN: -M no-aliases - | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ # RUN: --mattr=+f \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN @@ -23,14 +23,14 @@ # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 4a 0e -vfredsum.vs v8, v4, v20, v0.t -# CHECK-INST: vfredsum.vs v8, v4, v20, v0.t +vfredusum.vs v8, v4, v20, v0.t +# CHECK-INST: vfredusum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x04] # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 4a 04 -vfredsum.vs v8, v4, v20 -# CHECK-INST: vfredsum.vs v8, v4, v20 +vfredusum.vs v8, v4, v20 +# CHECK-INST: vfredusum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x06] # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 4a 06 @@ -71,14 +71,14 @@ # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 4a ce -vfwredsum.vs v8, v4, v20, v0.t -# CHECK-INST: vfwredsum.vs v8, v4, v20, v0.t +vfwredusum.vs v8, v4, v20, v0.t +# CHECK-INST: vfwredusum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc4] # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 4a c4 -vfwredsum.vs v8, v4, v20 -# CHECK-INST: vfwredsum.vs v8, v4, v20 +vfwredusum.vs v8, v4, v20 +# CHECK-INST: vfwredusum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc6] # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 4a c6