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Differential D105685

[RISCV][RVV] Precommit a test case for D105684
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Authored by arcbbb on Jul 9 2021, 2:12 AM.

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Reviewers
frasercrmck
Commits
rGbe8159bfa56f: [RISCV][RVV] Precommit a test case for D105684

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Event Timeline

arcbbb created this revision.Jul 9 2021, 2:12 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 24 others. · View Herald TranscriptJul 9 2021, 2:12 AM
arcbbb requested review of this revision.Jul 9 2021, 2:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 9 2021, 2:12 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
arcbbb added a child revision: D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.Jul 9 2021, 2:12 AM
Harbormaster completed remote builds in B113153: Diff 357444.Jul 9 2021, 2:46 AM
• post.kadirselcuk added a child revision: D34362: [LNT] Support for different DataSet usage in Polybench for "lnt runtest nt".Jul 10 2021, 5:55 PM
• post.kadirselcuk added a parent revision: D105762: [X86] Teach X86FloatingPoint's handleCall to only erase the FP stack if there is a regmask operand that clobbers the FP stack..Jul 10 2021, 8:06 PM
craig.topper removed a parent revision: D105762: [X86] Teach X86FloatingPoint's handleCall to only erase the FP stack if there is a regmask operand that clobbers the FP stack..Jul 10 2021, 9:47 PM
craig.topper removed a child revision: D34362: [LNT] Support for different DataSet usage in Polybench for "lnt runtest nt".Jul 13 2021, 10:14 AM
frasercrmck accepted this revision.Jul 14 2021, 2:26 AM

LGTM

This revision is now accepted and ready to land.Jul 14 2021, 2:26 AM
This revision was landed with ongoing or failed builds.Jul 17 2021, 9:44 AM
Closed by commit rGbe8159bfa56f: [RISCV][RVV] Precommit a test case for D105684 (authored by arcbbb). · Explain Why
This revision was automatically updated to reflect the committed changes.
arcbbb added a commit: rGbe8159bfa56f: [RISCV][RVV] Precommit a test case for D105684.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
23 lines

Diff 359567

llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -mtriple=riscv64 -mattr=+experimental-v -run-pass=simple-register-coalescing -o - | FileCheck %s
---
# Make sure that SrcReg & DstReg of PseudoVRGATHER are not coalesced
name: test_earlyclobber
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10
; CHECK-LABEL: name: test_earlyclobber
; CHECK: liveins: $x10
; CHECK: undef %2.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
; CHECK: %2.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
; CHECK: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 $x10, 1, 5
; CHECK: early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %2.sub_vrm2_0, 0, 1, 5, implicit $vl, implicit $vtype
; CHECK: PseudoVSUXSEG2EI32_V_M2_M2 %2, $x10, [[PseudoVLE32_V_M2_]], 1, 5, implicit $vl, implicit $vtype
undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
%0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5
%1:vrm2 = PseudoVLE32_V_M2 $x10, 1, 5
undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0:vrn2m2, 0, 1, 5, implicit $vl, implicit $vtype
%2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1:vrn2m2
PseudoVSUXSEG2EI32_V_M2_M2 %2:vrn2m2, $x10, %1:vrm2, 1, 5, implicit $vl, implicit $vtype
...