diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -3025,8 +3025,10 @@ MachineBasicBlock::iterator MI = MBB->begin(); if (!VNI->isPHIDef()) { MI = Indexes->getInstructionFromIndex(VNI->def); - // No need to check the instruction defining VNI for reads. - ++MI; + if (!VNI->def.isEarlyClobber()) { + // No need to check the instruction defining VNI for reads. + ++MI; + } } assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) && "Interference ends on VNI->def. Should have been handled earlier"); diff --git a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir --- a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir +++ b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir @@ -9,10 +9,11 @@ liveins: $x10 ; CHECK-LABEL: name: test_earlyclobber ; CHECK: liveins: $x10 - ; CHECK: undef %2.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5 - ; CHECK: %2.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5 + ; CHECK: undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5 + ; CHECK: %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5 ; CHECK: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 $x10, 1, 5 - ; CHECK: early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %2.sub_vrm2_0, 0, 1, 5, implicit $vl, implicit $vtype + ; CHECK: undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0, 0, 1, 5, implicit $vl, implicit $vtype + ; CHECK: %2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1 ; CHECK: PseudoVSUXSEG2EI32_V_M2_M2 %2, $x10, [[PseudoVLE32_V_M2_]], 1, 5, implicit $vl, implicit $vtype undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5 %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 $x10, 1, 5