Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -486,11 +486,11 @@
     RegKind_CCR = 128,    /// CCR
     RegKind_HWRegs = 256, /// HWRegs
     RegKind_COP3 = 512,   /// COP3
-
+    RegKind_COP0 = 1024,  /// COP0
     /// Potentially any (e.g. $1)
     RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
                       RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
-                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3
+                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
   };
 
 private:
@@ -652,6 +652,14 @@
     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
   }
 
+  /// Coerce the register to COP0 and return the real register for the
+  /// current target.
+  unsigned getCOP0Reg() const {
+    assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
+    unsigned ClassID = Mips::COP0RegClassID;
+    return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
+  }
+
   /// Coerce the register to COP2 and return the real register for the
   /// current target.
   unsigned getCOP2Reg() const {
@@ -793,6 +801,11 @@
     Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
   }
 
+  void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
+  }
+
   void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
@@ -1168,6 +1181,9 @@
   bool isACCAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
   }
+  bool isCOP0AsmReg() const {
+    return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
+  }
   bool isCOP2AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
   }
Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp
===================================================================
--- lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -178,6 +178,11 @@
                                                uint64_t Address,
                                                const void *Decoder);
 
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
+                                            unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder);
+
 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
                                             unsigned RegNo,
                                             uint64_t Address,
@@ -1564,6 +1569,18 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
+                                            unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+
+  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
                                             unsigned RegNo,
                                             uint64_t Address,
Index: lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
@@ -79,6 +79,9 @@
     if (GPR32RegClass->contains(CurrentSubReg) ||
         GPR64RegClass->contains(CurrentSubReg))
       ri_gprmask |= Value;
+    else if (COP0RegClass->contains(CurrentSubReg))
+      ri_cprmask[0] |= Value;
+    // MIPS COP1 is the FPU.
     else if (FGR32RegClass->contains(CurrentSubReg) ||
              FGR64RegClass->contains(CurrentSubReg) ||
              AFGR64RegClass->contains(CurrentSubReg) ||
Index: lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips64InstrInfo.td
+++ lib/Target/Mips/Mips64InstrInfo.td
@@ -427,10 +427,10 @@
 
 /// Move between CPU and coprocessor registers
 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
-def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
-def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
-def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
-def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
+def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>;
+def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
+def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
+def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
 }
 
 //===----------------------------------------------------------------------===//
@@ -613,10 +613,10 @@
                     ISA_MIPS3;
 
 // Two operand (implicit 0 selector) versions:
-def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
+def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
 
 let Predicates = [HasMips64, HasCnMips] in {
 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1050,8 +1050,12 @@
   let Constraints = "$rt = $dst";
 }
 
-class MFC3OP<string asmstr, RegisterOperand RO> :
-  InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
+class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+  InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
+         !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
+
+class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+  InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
          !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
 
 class TrapBase<Instruction RealInst>
@@ -1484,10 +1488,10 @@
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 
 /// Move Control Registers From/To CPU Registers
-def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
-def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
-def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
-def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
+def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
+def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
+def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
+def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
 
 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
                                       FrmOther, asmstr>;
@@ -1604,10 +1608,10 @@
 def : MipsInstAlias<"or $rs, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
-def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
+def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
 }
Index: lib/Target/Mips/MipsOptionRecord.h
===================================================================
--- lib/Target/Mips/MipsOptionRecord.h
+++ lib/Target/Mips/MipsOptionRecord.h
@@ -49,6 +49,7 @@
     FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
     AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
     MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
+    COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
     COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
     COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
   }
@@ -66,6 +67,7 @@
   const MCRegisterClass *FGR64RegClass;
   const MCRegisterClass *AFGR64RegClass;
   const MCRegisterClass *MSA128BRegClass;
+  const MCRegisterClass *COP0RegClass;
   const MCRegisterClass *COP2RegClass;
   const MCRegisterClass *COP3RegClass;
   uint32_t ri_gprmask;
Index: lib/Target/Mips/MipsRegisterInfo.td
===================================================================
--- lib/Target/Mips/MipsRegisterInfo.td
+++ lib/Target/Mips/MipsRegisterInfo.td
@@ -201,6 +201,10 @@
   foreach I = 0-7 in
   def FCC#I : MipsReg<#I, "fcc"#I>;
 
+  // COP0 registers.
+  foreach I = 0-31 in
+  def COP0#I : MipsReg<#I, ""#I>;
+
   // COP2 registers.
   foreach I = 0-31 in
   def COP2#I : MipsReg<#I, ""#I>;
@@ -431,6 +435,10 @@
 
 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
 
+// Coprocessor 0 registers.
+def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,
+           Unallocatable;
+
 // Coprocessor 2 registers.
 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
            Unallocatable;
@@ -559,6 +567,10 @@
   let Name = "HWRegsAsmReg";
 }
 
+def COP0AsmOperand : MipsAsmRegOperand {
+  let Name = "COP0AsmReg";
+}
+
 def COP2AsmOperand : MipsAsmRegOperand {
   let Name = "COP2AsmReg";
 }
@@ -609,6 +621,10 @@
   let ParserMatchClass = ACC64DSPAsmOperand;
 }
 
+def COP0Opnd : RegisterOperand<COP0> {
+  let ParserMatchClass = COP0AsmOperand;
+}
+
 def COP2Opnd : RegisterOperand<COP2> {
   let ParserMatchClass = COP2AsmOperand;
 }
Index: test/MC/Disassembler/Mips/mips32.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32.txt
+++ test/MC/Disassembler/Mips/mips32.txt
@@ -255,6 +255,9 @@
 # CHECK: maddu  $6,  $7
 0x70 0xc7 0x00 0x01
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x44 0x06 0x38 0x00
 
@@ -294,6 +297,9 @@
 # CHECK: msubu  $6,  $7
 0x70 0xc7 0x00 0x05
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x44 0x86 0x38 0x00
 
Index: test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
+++ test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
@@ -86,6 +86,7 @@
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
@@ -93,6 +94,7 @@
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
Index: test/MC/Disassembler/Mips/mips32/valid-mips32.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32/valid-mips32.txt
+++ test/MC/Disassembler/Mips/mips32/valid-mips32.txt
@@ -86,6 +86,7 @@
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
@@ -93,6 +94,7 @@
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
Index: test/MC/Disassembler/Mips/mips32_le.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32_le.txt
+++ test/MC/Disassembler/Mips/mips32_le.txt
@@ -254,6 +254,9 @@
 # CHECK: maddu  $6,  $7
 0x01 0x00 0xc7 0x70
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x00 0x38 0x06 0x44
 
@@ -299,6 +302,9 @@
 # CHECK: msubu  $6,  $7
 0x05 0x00 0xc7 0x70
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x00 0x38 0x86 0x44
 
Index: test/MC/Disassembler/Mips/mips32r2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2.txt
+++ test/MC/Disassembler/Mips/mips32r2.txt
@@ -269,6 +269,9 @@
 # CHECK: maddu  $6,  $7
 0x70 0xc7 0x00 0x01
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x44 0x06 0x38 0x00
 
@@ -290,6 +293,9 @@
 # CHECK: msubu  $6,  $7
 0x70 0xc7 0x00 0x05
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x44 0x86 0x38 0x00
 
Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
+++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
@@ -101,6 +101,7 @@
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $16, 4
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -111,6 +112,7 @@
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -101,6 +101,7 @@
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $16, 4
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -111,6 +112,7 @@
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips32r2_le.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r2_le.txt
+++ test/MC/Disassembler/Mips/mips32r2_le.txt
@@ -269,6 +269,9 @@
 # CHECK: maddu  $6,  $7
 0x01 0x00 0xc7 0x70
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x00 0x38 0x06 0x44
 
@@ -290,6 +293,9 @@
 # CHECK: msubu  $6,  $7
 0x05 0x00 0xc7 0x70
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x00 0x38 0x86 0x44
 
Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
+++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
@@ -98,6 +98,7 @@
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -108,6 +109,7 @@
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
+++ test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -98,6 +98,7 @@
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -108,6 +109,7 @@
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
+++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
@@ -98,6 +98,7 @@
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -108,6 +109,7 @@
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
+++ test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -98,6 +98,7 @@
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -108,6 +109,7 @@
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips32r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r6.txt
+++ test/MC/Disassembler/Mips/mips32r6.txt
@@ -88,8 +88,10 @@
 # 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256
 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
+0x40 0x08 0x80 0x08 # CHECK: mfc0 $8, $16, 4
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
 0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
Index: test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -83,6 +83,7 @@
 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 3
 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
 0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
@@ -93,6 +94,7 @@
 0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4
 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2
 0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2
 0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4
Index: test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -83,6 +83,8 @@
 0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3
 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
Index: test/MC/Disassembler/Mips/mips64.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64.txt
+++ test/MC/Disassembler/Mips/mips64.txt
@@ -14,9 +14,15 @@
 # CHECK: ddivu $zero, $9, $24
 0x01 0x38 0x00 0x1f
 
+# CHECK: dmfc0 $24, $10, 0
+0x40 0x38 0x50 0x00
+
 # CHECK: dmfc1 $2, $f14
 0x44 0x22 0x70 0x00
 
+# CHECK: dmtc0 $4, $10, 0
+0x40 0xa4 0x50 0x00
+
 # CHECK: dmtc1 $23, $f5
 0x44 0xb7 0x28 0x00
 
@@ -47,6 +53,12 @@
 # CHECK: dsubu $gp, $27, $24
 0x03 0x78 0xe0 0x2f
 
+# CHECK: mfc0 $8, $15, 1
+0x40 0x08 0x80 0x04
+
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: lw $27, -15155($1)
 0x8c 0x3b 0xc4 0xcd
 
Index: test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -82,7 +82,9 @@
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
@@ -142,6 +144,7 @@
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
@@ -149,6 +152,7 @@
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
Index: test/MC/Disassembler/Mips/mips64/valid-mips64.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -82,7 +82,9 @@
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
@@ -144,6 +146,7 @@
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
@@ -151,6 +154,7 @@
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -88,7 +88,9 @@
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
@@ -161,6 +163,7 @@
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -170,6 +173,7 @@
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -88,7 +88,9 @@
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
@@ -163,6 +165,7 @@
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -172,6 +175,7 @@
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -85,7 +85,9 @@
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
@@ -158,6 +160,7 @@
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -167,6 +170,7 @@
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -85,7 +85,9 @@
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
@@ -160,6 +162,7 @@
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -169,6 +172,7 @@
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -85,7 +85,9 @@
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
@@ -158,6 +160,7 @@
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
@@ -167,6 +170,7 @@
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -85,7 +85,9 @@
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
@@ -160,6 +162,7 @@
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
@@ -169,6 +172,7 @@
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
Index: test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -92,8 +92,10 @@
 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4
 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4
 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 3
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4
 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
@@ -119,12 +121,14 @@
 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
 0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
Index: test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -92,8 +92,10 @@
 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
 0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4
 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
 0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4
 0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4
@@ -121,6 +123,7 @@
 0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
 0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4
 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
 0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4
@@ -129,6 +132,7 @@
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4
 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
Index: test/MC/Mips/mips-cop0-reginfo.s
===================================================================
--- /dev/null
+++ test/MC/Mips/mips-cop0-reginfo.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -filetype=obj %s -o - | \
+# RUN:   llvm-readobj -sections -section-data - | \
+# RUN:     FileCheck %s -check-prefix=CHECK
+	mfc0	$16, $15, 1
+	mfc0	$16, $16, 1
+
+
+# Checking for the coprocessor 0's register usage was recorded
+# and emitted.
+# CHECK:  Section {
+# CHECK:     Index: 5
+# CHECK:     Name: .reginfo (27)
+# CHECK:     Type: SHT_MIPS_REGINFO (0x70000006)
+# CHECK:     Flags [ (0x2)
+# CHECK:       SHF_ALLOC (0x2)
+# CHECK:     ]
+# CHECK:     Address: 0x0
+# CHECK:     Offset: 0x50
+# CHECK:     Size: 24
+# CHECK:     Link: 0
+# CHECK:     Info: 0
+# CHECK:     AddressAlignment: 4
+# CHECK:     EntrySize: 24
+# CHECK:     SectionData (
+# CHECK:       0000: 00010000 00018000 00000000 00000000  |................|
+# CHECK:       0010: 00000000 00000000                    |........|
+# CHECK:     )
+# CHECK:   }
Index: test/MC/Mips/mips32/valid.s
===================================================================
--- test/MC/Mips/mips32/valid.s
+++ test/MC/Mips/mips32/valid.s
@@ -89,7 +89,7 @@
         madd      $zero,$9
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhi      $s3
         mfhi      $sp
@@ -112,7 +112,7 @@
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
Index: test/MC/Mips/mips32r2/valid.s
===================================================================
--- test/MC/Mips/mips32r2/valid.s
+++ test/MC/Mips/mips32r2/valid.s
@@ -103,7 +103,7 @@
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
@@ -129,7 +129,7 @@
         msub.d    $f10,$f1,$f31,$f18
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1     # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
Index: test/MC/Mips/mips32r3/valid.s
===================================================================
--- test/MC/Mips/mips32r3/valid.s
+++ test/MC/Mips/mips32r3/valid.s
@@ -103,7 +103,7 @@
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
@@ -129,7 +129,7 @@
         msub.d    $f10,$f1,$f31,$f18
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
Index: test/MC/Mips/mips32r5/valid.s
===================================================================
--- test/MC/Mips/mips32r5/valid.s
+++ test/MC/Mips/mips32r5/valid.s
@@ -103,7 +103,7 @@
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
@@ -129,7 +129,7 @@
         msub.d    $f10,$f1,$f31,$f18
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
Index: test/MC/Mips/mips32r6/valid.s
===================================================================
--- test/MC/Mips/mips32r6/valid.s
+++ test/MC/Mips/mips32r6/valid.s
@@ -108,8 +108,10 @@
         lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
+        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1  # encoding: [0x40,0x89,0x78,0x01]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
Index: test/MC/Mips/mips64/valid.s
===================================================================
--- test/MC/Mips/mips64/valid.s
+++ test/MC/Mips/mips64/valid.s
@@ -82,7 +82,9 @@
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10, $16, 2          # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4, $10, 0           # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
@@ -154,7 +156,7 @@
         maddu     $24,$s2
         madd.d    $f18, $f22, $f26, $f20  # encoding: [0x4e,0xd4,0xd4,0xa1]
         madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhi      $s3
         mfhi      $sp
@@ -181,7 +183,7 @@
         msubu     $15,$a1
         msub.d    $f10, $f2, $f30, $f18   # encoding: [0x4c,0x52,0xf2,0xa9]
         msub.s    $f12, $f18, $f10, $f16  # encoding: [0x4e,0x50,0x53,0x28]
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1                # CHECK: mtc0 $9, $15, 1     # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
Index: test/MC/Mips/mips64r2/valid.s
===================================================================
--- test/MC/Mips/mips64r2/valid.s
+++ test/MC/Mips/mips64r2/valid.s
@@ -84,7 +84,9 @@
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10,$16,2            # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4,$10,0             # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
@@ -169,7 +171,7 @@
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
@@ -196,7 +198,7 @@
         msub      $s7,$k1
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1     # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
Index: test/MC/Mips/mips64r3/valid.s
===================================================================
--- test/MC/Mips/mips64r3/valid.s
+++ test/MC/Mips/mips64r3/valid.s
@@ -84,7 +84,9 @@
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10, $16, 2          # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4, $10, 0           # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
@@ -169,7 +171,7 @@
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
@@ -196,7 +198,7 @@
         msub      $s7,$k1
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
Index: test/MC/Mips/mips64r5/valid.s
===================================================================
--- test/MC/Mips/mips64r5/valid.s
+++ test/MC/Mips/mips64r5/valid.s
@@ -84,7 +84,9 @@
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10, $16, 2          # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4, $10, 0           # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
@@ -169,7 +171,7 @@
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
@@ -196,7 +198,7 @@
         msub      $s7,$k1
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
Index: test/MC/Mips/mips64r6/valid.s
===================================================================
--- test/MC/Mips/mips64r6/valid.s
+++ test/MC/Mips/mips64r6/valid.s
@@ -117,8 +117,10 @@
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5]
+        dmfc0   $10, $16, 2      # CHECK: dmfc0 $10, $16, 2  # encoding: [0x40,0x2a,0x80,0x02]
         dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
         dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
+        dmtc0   $4, $10, 0       # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00]
         dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdc]
         dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
         dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9c]
@@ -158,8 +160,10 @@
         min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
         mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
         mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
         msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]