Index: llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h =================================================================== --- llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -71,11 +71,17 @@ /// arguments. const Value *OrigValue = nullptr; - ArgInfo(ArrayRef Regs, Type *Ty, + /// Index original Function's argument. + unsigned OrigArgIndex; + + /// Sentinel value for implicit machine-level input arguments. + static const unsigned NoArgIndex = UINT_MAX; + + ArgInfo(ArrayRef Regs, Type *Ty, unsigned OrigIndex, ArrayRef Flags = ArrayRef(), bool IsFixed = true, const Value *OrigValue = nullptr) : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()), - OrigValue(OrigValue) { + OrigValue(OrigValue), OrigArgIndex(OrigIndex) { if (!Regs.empty() && Flags.empty()) this->Flags.push_back(ISD::ArgFlagsTy()); // FIXME: We should have just one way of saying "no register". @@ -84,10 +90,10 @@ "only void types should have no register"); } - ArgInfo(ArrayRef Regs, const Value &OrigValue, + ArgInfo(ArrayRef Regs, const Value &OrigValue, unsigned OrigIndex, ArrayRef Flags = ArrayRef(), bool IsFixed = true) - : ArgInfo(Regs, OrigValue.getType(), Flags, IsFixed, &OrigValue) {} + : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {} ArgInfo() : BaseArgInfo() {} }; Index: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp =================================================================== --- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -114,7 +114,7 @@ unsigned i = 0; unsigned NumFixedArgs = CB.getFunctionType()->getNumParams(); for (auto &Arg : CB.args()) { - ArgInfo OrigArg{ArgRegs[i], *Arg.get(), getAttributesForArgIdx(CB, i), + ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i), i < NumFixedArgs}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB); @@ -135,7 +135,7 @@ else Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false); - Info.OrigRet = ArgInfo{ResRegs, RetTy, ISD::ArgFlagsTy{}}; + Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, ISD::ArgFlagsTy{}}; if (!Info.OrigRet.Ty->isVoidTy()) setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CB); @@ -215,8 +215,8 @@ // No splitting to do, but we want to replace the original type (e.g. [1 x // double] -> double). SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), - OrigArg.Flags[0], OrigArg.IsFixed, - OrigArg.OrigValue); + OrigArg.OrigArgIndex, OrigArg.Flags[0], + OrigArg.IsFixed, OrigArg.OrigValue); return; } @@ -227,8 +227,8 @@ OrigArg.Ty, CallConv, false, DL); for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) { Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx); - SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0], - OrigArg.IsFixed); + SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex, + OrigArg.Flags[0], OrigArg.IsFixed); if (NeedsRegBlock) SplitArgs.back().Flags[0].setInConsecutiveRegs(); } @@ -837,7 +837,8 @@ // NOTE: Assume that a pointer won't get split into more than one VT. assert(ValueVTs.size() == 1); - ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext())); + ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()), + ArgInfo::NoArgIndex); setArgFlags(DemoteArg, AttributeList::ReturnIndex, DL, F); DemoteArg.Flags[0].setSRet(); SplitArgs.insert(SplitArgs.begin(), DemoteArg); @@ -855,7 +856,8 @@ DL.getTypeAllocSize(RetTy), DL.getPrefTypeAlign(RetTy), false); Register DemoteReg = MIRBuilder.buildFrameIndex(FramePtrTy, FI).getReg(0); - ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS)); + ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS), + ArgInfo::NoArgIndex); setArgFlags(DemoteArg, AttributeList::ReturnIndex, DL, CB); DemoteArg.Flags[0].setSRet(); Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -546,11 +546,12 @@ Type *OpType) { auto Libcall = getRTLibDesc(MI.getOpcode(), Size); + // FIXME: What does the original arg index mean here? SmallVector Args; for (unsigned i = 1; i < MI.getNumOperands(); i++) - Args.push_back({MI.getOperand(i).getReg(), OpType}); - return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, - Args); + Args.push_back({MI.getOperand(i).getReg(), OpType, 0}); + return createLibcall(MIRBuilder, Libcall, + {MI.getOperand(0).getReg(), OpType, 0}, Args); } LegalizerHelper::LegalizeResult @@ -570,7 +571,7 @@ OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); else OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); - Args.push_back({Reg, OpTy}); + Args.push_back({Reg, OpTy, 0}); } auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); @@ -605,7 +606,7 @@ CallLowering::CallLoweringInfo Info; Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); Info.Callee = MachineOperand::CreateES(Name); - Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); + Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx), 0); Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && isLibCallInTailPosition(MIRBuilder.getTII(), MI); @@ -664,8 +665,9 @@ conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, Type *FromType) { RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); - return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, - {{MI.getOperand(1).getReg(), FromType}}); + return createLibcall(MIRBuilder, Libcall, + {MI.getOperand(0).getReg(), ToType, 0}, + {{MI.getOperand(1).getReg(), FromType, 0}}); } LegalizerHelper::LegalizeResult Index: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -370,7 +370,7 @@ } Register CurVReg = VRegs[i]; - ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)}; + ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx), 0}; setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F); // i1 is a special case because SDAG i1 true is naturally zero extended @@ -533,7 +533,7 @@ if (DL.getTypeStoreSize(Arg.getType()).isZero()) continue; - ArgInfo OrigArg{VRegs[i], Arg}; + ArgInfo OrigArg{VRegs[i], Arg, i}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); if (Arg.hasAttribute(Attribute::SwiftAsync)) Index: llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -293,7 +293,7 @@ for (unsigned i = 0; i < SplitEVTs.size(); ++i) { EVT VT = SplitEVTs[i]; Register Reg = VRegs[i]; - ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx)); + ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx), 0); setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F); if (VT.isScalarInteger()) { @@ -637,7 +637,7 @@ } } - ArgInfo OrigArg(VRegs[Idx], Arg); + ArgInfo OrigArg(VRegs[Idx], Arg, Idx); const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex; setArgFlags(OrigArg, OrigArgIdx, DL, F); Index: llvm/lib/Target/ARM/ARMCallLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMCallLowering.cpp +++ llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -186,7 +186,7 @@ if (!isSupportedType(DL, TLI, Val->getType())) return false; - ArgInfo OrigRetInfo(VRegs, Val->getType()); + ArgInfo OrigRetInfo(VRegs, Val->getType(), 0); setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F); SmallVector SplitRetInfos; @@ -388,7 +388,7 @@ SmallVector SplitArgInfos; unsigned Idx = 0; for (auto &Arg : F.args()) { - ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType()); + ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType(), Idx); setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F); splitToValueTypes(OrigArgInfo, SplitArgInfos, DL, F.getCallingConv()); Index: llvm/lib/Target/ARM/ARMLegalizerInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -389,9 +389,9 @@ StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}; - auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy}, - {{MI.getOperand(1).getReg(), ArgTy}, - {MI.getOperand(2).getReg(), ArgTy}}); + auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy, 0}, + {{MI.getOperand(1).getReg(), ArgTy, 0}, + {MI.getOperand(2).getReg(), ArgTy, 0}}); if (Status != LegalizerHelper::Legalized) return false; break; @@ -424,10 +424,10 @@ SmallVector Results; for (auto Libcall : Libcalls) { auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); - auto Status = - createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, - {{MI.getOperand(2).getReg(), ArgTy}, - {MI.getOperand(3).getReg(), ArgTy}}); + auto Status = createLibcall(MIRBuilder, Libcall.LibcallID, + {LibcallResult, RetTy, 0}, + {{MI.getOperand(2).getReg(), ArgTy, 0}, + {MI.getOperand(3).getReg(), ArgTy, 0}}); if (Status != LegalizerHelper::Legalized) return false; Index: llvm/lib/Target/Mips/MipsCallLowering.cpp =================================================================== --- llvm/lib/Target/Mips/MipsCallLowering.cpp +++ llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -392,7 +392,7 @@ SmallVector RetInfos; SmallVector OrigArgIndices; - ArgInfo ArgRetInfo(VRegs, Val->getType()); + ArgInfo ArgRetInfo(VRegs, Val->getType(), 0); setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F); splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices); @@ -436,7 +436,7 @@ SmallVector OrigArgIndices; unsigned i = 0; for (auto &Arg : F.args()) { - ArgInfo AInfo(VRegs[i], Arg.getType()); + ArgInfo AInfo(VRegs[i], Arg.getType(), i); setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F); ArgInfos.push_back(AInfo); OrigArgIndices.push_back(i); @@ -682,7 +682,8 @@ ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitEVTs); for (unsigned i = 0; i < SplitEVTs.size(); ++i) { - ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; + ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx), + OriginalIndex}; Info.Flags = OrigArg.Flags; SplitArgs.push_back(Info); SplitArgsOrigIndices.push_back(OriginalIndex); Index: llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp =================================================================== --- llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp +++ llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp @@ -63,7 +63,7 @@ if (DL.getTypeStoreSize(Arg.getType()).isZero()) continue; - ArgInfo OrigArg{VRegs[I], Arg}; + ArgInfo OrigArg{VRegs[I], Arg, I}; setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F); splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv()); ++I; Index: llvm/lib/Target/X86/X86CallLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86CallLowering.cpp +++ llvm/lib/Target/X86/X86CallLowering.cpp @@ -142,7 +142,7 @@ MachineRegisterInfo &MRI = MF.getRegInfo(); const DataLayout &DL = MF.getDataLayout(); - ArgInfo OrigRetInfo(VRegs, Val->getType()); + ArgInfo OrigRetInfo(VRegs, Val->getType(), 0); setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F); SmallVector SplitRetInfos; @@ -261,7 +261,7 @@ Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) return false; - ArgInfo OrigArg(VRegs[Idx], Arg.getType()); + ArgInfo OrigArg(VRegs[Idx], Arg.getType(), Idx); setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F); splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv()); Idx++; Index: llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp =================================================================== --- llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp +++ llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp @@ -3576,7 +3576,7 @@ auto *RetTy = Type::getVoidTy(Ctx); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, - createLibcall(B, "abort", {{}, RetTy}, {}, CallingConv::C)); + createLibcall(B, "abort", {{}, RetTy, 0}, {}, CallingConv::C)); auto CheckStr = R"( CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp