diff --git a/llvm/test/tools/llvm-mca/JSON/X86/views-multiple-region.s b/llvm/test/tools/llvm-mca/JSON/X86/views-multiple-region.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-mca/JSON/X86/views-multiple-region.s @@ -0,0 +1,307 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# Verify that we create proper JSON for the MCA views TimelineView, ResourcePressureview, +# InstructionInfoView and SummaryView. + +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell --json --timeline-max-iterations=1 --timeline --all-stats --all-views < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell --json --timeline-max-iterations=1 --timeline --all-stats --all-views -o %t.json < %s +# RUN: cat %t.json \ +# RUN: | %python -c 'import json, sys; json.dump(json.loads(sys.stdin.read()), sys.stdout, sort_keys=True, indent=2)' \ +# RUN: | FileCheck %s + +# LLVM-MCA-BEGIN foo +add %eax, %eax +# LLVM-MCA-BEGIN bar +add %ebx, %ebx +add %ecx, %ecx +# LLVM-MCA-END bar +add %edx, %edx +# LLVM-MCA-END foo + +# CHECK: { +# CHECK-NEXT: "bar": { +# CHECK-NEXT: "DispatchStatistics": { +# CHECK-NEXT: "GROUP": 0, +# CHECK-NEXT: "LQ": 0, +# CHECK-NEXT: "RAT": 0, +# CHECK-NEXT: "RCU": 0, +# CHECK-NEXT: "SCHEDQ": 41, +# CHECK-NEXT: "SQ": 0, +# CHECK-NEXT: "USH": 0 +# CHECK-NEXT: }, +# CHECK-NEXT: "InstructionInfoView": { +# CHECK-NEXT: "InstructionList": [ +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 0, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 1, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: }, +# CHECK-NEXT: "Instructions and CPU resources": { +# CHECK-NEXT: "Instructions": [ +# CHECK-NEXT: "addl\t%ebx, %ebx", +# CHECK-NEXT: "addl\t%ecx, %ecx" +# CHECK-NEXT: ], +# CHECK-NEXT: "Resources": { +# CHECK-NEXT: "CPUName": "haswell", +# CHECK-NEXT: "Resources": [ +# CHECK-NEXT: "HWDivider", +# CHECK-NEXT: "HWFPDivider", +# CHECK-NEXT: "HWPort0", +# CHECK-NEXT: "HWPort1", +# CHECK-NEXT: "HWPort2", +# CHECK-NEXT: "HWPort3", +# CHECK-NEXT: "HWPort4", +# CHECK-NEXT: "HWPort5", +# CHECK-NEXT: "HWPort6", +# CHECK-NEXT: "HWPort7" +# CHECK-NEXT: ] +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "ResourcePressureView": { +# CHECK-NEXT: "ResourcePressureInfo": [ +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 0, +# CHECK-NEXT: "ResourceIndex": 3, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 0, +# CHECK-NEXT: "ResourceIndex": 8, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 1, +# CHECK-NEXT: "ResourceIndex": 2, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 1, +# CHECK-NEXT: "ResourceIndex": 7, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 2, +# CHECK-NEXT: "ResourceIndex": 2, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 2, +# CHECK-NEXT: "ResourceIndex": 3, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 2, +# CHECK-NEXT: "ResourceIndex": 7, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 2, +# CHECK-NEXT: "ResourceIndex": 8, +# CHECK-NEXT: "ResourceUsage": 0.5 +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: }, +# CHECK-NEXT: "SummaryView": { +# CHECK-NEXT: "BlockRThroughput": 0.5, +# CHECK-NEXT: "DispatchWidth": 4, +# CHECK-NEXT: "IPC": 1.941747572815534, +# CHECK-NEXT: "Instructions": 200, +# CHECK-NEXT: "Iterations": 100, +# CHECK-NEXT: "TotalCycles": 103, +# CHECK-NEXT: "TotaluOps": 200, +# CHECK-NEXT: "uOpsPerCycle": 1.941747572815534 +# CHECK-NEXT: }, +# CHECK-NEXT: "TimelineView": { +# CHECK-NEXT: "TimelineInfo": [ +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "foo": { +# CHECK-NEXT: "DispatchStatistics": { +# CHECK-NEXT: "GROUP": 0, +# CHECK-NEXT: "LQ": 0, +# CHECK-NEXT: "RAT": 0, +# CHECK-NEXT: "RCU": 0, +# CHECK-NEXT: "SCHEDQ": 0, +# CHECK-NEXT: "SQ": 0, +# CHECK-NEXT: "USH": 0 +# CHECK-NEXT: }, +# CHECK-NEXT: "InstructionInfoView": { +# CHECK-NEXT: "InstructionList": [ +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 0, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 1, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 2, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 3, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: }, +# CHECK-NEXT: "Instructions and CPU resources": { +# CHECK-NEXT: "Instructions": [ +# CHECK-NEXT: "addl\t%eax, %eax", +# CHECK-NEXT: "addl\t%ebx, %ebx", +# CHECK-NEXT: "addl\t%ecx, %ecx", +# CHECK-NEXT: "addl\t%edx, %edx" +# CHECK-NEXT: ], +# CHECK-NEXT: "Resources": { +# CHECK-NEXT: "CPUName": "haswell", +# CHECK-NEXT: "Resources": [ +# CHECK-NEXT: "HWDivider", +# CHECK-NEXT: "HWFPDivider", +# CHECK-NEXT: "HWPort0", +# CHECK-NEXT: "HWPort1", +# CHECK-NEXT: "HWPort2", +# CHECK-NEXT: "HWPort3", +# CHECK-NEXT: "HWPort4", +# CHECK-NEXT: "HWPort5", +# CHECK-NEXT: "HWPort6", +# CHECK-NEXT: "HWPort7" +# CHECK-NEXT: ] +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "ResourcePressureView": { +# CHECK-NEXT: "ResourcePressureInfo": [ +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 0, +# CHECK-NEXT: "ResourceIndex": 8, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 1, +# CHECK-NEXT: "ResourceIndex": 7, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 2, +# CHECK-NEXT: "ResourceIndex": 3, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 3, +# CHECK-NEXT: "ResourceIndex": 2, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 2, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 3, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 7, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 8, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: }, +# CHECK-NEXT: "SummaryView": { +# CHECK-NEXT: "BlockRThroughput": 1, +# CHECK-NEXT: "DispatchWidth": 4, +# CHECK-NEXT: "IPC": 3.883495145631068, +# CHECK-NEXT: "Instructions": 400, +# CHECK-NEXT: "Iterations": 100, +# CHECK-NEXT: "TotalCycles": 103, +# CHECK-NEXT: "TotaluOps": 400, +# CHECK-NEXT: "uOpsPerCycle": 3.883495145631068 +# CHECK-NEXT: }, +# CHECK-NEXT: "TimelineView": { +# CHECK-NEXT: "TimelineInfo": [ +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: } +# CHECK-NEXT: } +# CHECK-NEXT: } diff --git a/llvm/test/tools/llvm-mca/JSON/X86/views.s b/llvm/test/tools/llvm-mca/JSON/X86/views.s --- a/llvm/test/tools/llvm-mca/JSON/X86/views.s +++ b/llvm/test/tools/llvm-mca/JSON/X86/views.s @@ -14,162 +14,164 @@ add %edx, %edx # CHECK: { -# CHECK-NEXT: "DispatchStatistics": { -# CHECK-NEXT: "GROUP": 0, -# CHECK-NEXT: "LQ": 0, -# CHECK-NEXT: "RAT": 0, -# CHECK-NEXT: "RCU": 0, -# CHECK-NEXT: "SCHEDQ": 0, -# CHECK-NEXT: "SQ": 0, -# CHECK-NEXT: "USH": 0 -# CHECK-NEXT: }, -# CHECK-NEXT: "InstructionInfoView": { -# CHECK-NEXT: "InstructionList": [ -# CHECK-NEXT: { -# CHECK-NEXT: "Instruction": 0, -# CHECK-NEXT: "Latency": 1, -# CHECK-NEXT: "NumMicroOpcodes": 1, -# CHECK-NEXT: "RThroughput": 0.25, -# CHECK-NEXT: "hasUnmodeledSideEffects": false, -# CHECK-NEXT: "mayLoad": false, -# CHECK-NEXT: "mayStore": false -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "Instruction": 1, -# CHECK-NEXT: "Latency": 1, -# CHECK-NEXT: "NumMicroOpcodes": 1, -# CHECK-NEXT: "RThroughput": 0.25, -# CHECK-NEXT: "hasUnmodeledSideEffects": false, -# CHECK-NEXT: "mayLoad": false, -# CHECK-NEXT: "mayStore": false -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "Instruction": 2, -# CHECK-NEXT: "Latency": 1, -# CHECK-NEXT: "NumMicroOpcodes": 1, -# CHECK-NEXT: "RThroughput": 0.25, -# CHECK-NEXT: "hasUnmodeledSideEffects": false, -# CHECK-NEXT: "mayLoad": false, -# CHECK-NEXT: "mayStore": false -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "Instruction": 3, -# CHECK-NEXT: "Latency": 1, -# CHECK-NEXT: "NumMicroOpcodes": 1, -# CHECK-NEXT: "RThroughput": 0.25, -# CHECK-NEXT: "hasUnmodeledSideEffects": false, -# CHECK-NEXT: "mayLoad": false, -# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: "main": { +# CHECK-NEXT: "DispatchStatistics": { +# CHECK-NEXT: "GROUP": 0, +# CHECK-NEXT: "LQ": 0, +# CHECK-NEXT: "RAT": 0, +# CHECK-NEXT: "RCU": 0, +# CHECK-NEXT: "SCHEDQ": 0, +# CHECK-NEXT: "SQ": 0, +# CHECK-NEXT: "USH": 0 +# CHECK-NEXT: }, +# CHECK-NEXT: "InstructionInfoView": { +# CHECK-NEXT: "InstructionList": [ +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 0, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 1, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 2, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "Instruction": 3, +# CHECK-NEXT: "Latency": 1, +# CHECK-NEXT: "NumMicroOpcodes": 1, +# CHECK-NEXT: "RThroughput": 0.25, +# CHECK-NEXT: "hasUnmodeledSideEffects": false, +# CHECK-NEXT: "mayLoad": false, +# CHECK-NEXT: "mayStore": false +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: }, +# CHECK-NEXT: "Instructions and CPU resources": { +# CHECK-NEXT: "Instructions": [ +# CHECK-NEXT: "addl\t%eax, %eax", +# CHECK-NEXT: "addl\t%ebx, %ebx", +# CHECK-NEXT: "addl\t%ecx, %ecx", +# CHECK-NEXT: "addl\t%edx, %edx" +# CHECK-NEXT: ], +# CHECK-NEXT: "Resources": { +# CHECK-NEXT: "CPUName": "haswell", +# CHECK-NEXT: "Resources": [ +# CHECK-NEXT: "HWDivider", +# CHECK-NEXT: "HWFPDivider", +# CHECK-NEXT: "HWPort0", +# CHECK-NEXT: "HWPort1", +# CHECK-NEXT: "HWPort2", +# CHECK-NEXT: "HWPort3", +# CHECK-NEXT: "HWPort4", +# CHECK-NEXT: "HWPort5", +# CHECK-NEXT: "HWPort6", +# CHECK-NEXT: "HWPort7" +# CHECK-NEXT: ] # CHECK-NEXT: } -# CHECK-NEXT: ] -# CHECK-NEXT: }, -# CHECK-NEXT: "Instructions and CPU resources": { -# CHECK-NEXT: "Instructions": [ -# CHECK-NEXT: "addl\t%eax, %eax", -# CHECK-NEXT: "addl\t%ebx, %ebx", -# CHECK-NEXT: "addl\t%ecx, %ecx", -# CHECK-NEXT: "addl\t%edx, %edx" -# CHECK-NEXT: ], -# CHECK-NEXT: "Resources": { -# CHECK-NEXT: "CPUName": "haswell", -# CHECK-NEXT: "Resources": [ -# CHECK-NEXT: "HWDivider", -# CHECK-NEXT: "HWFPDivider", -# CHECK-NEXT: "HWPort0", -# CHECK-NEXT: "HWPort1", -# CHECK-NEXT: "HWPort2", -# CHECK-NEXT: "HWPort3", -# CHECK-NEXT: "HWPort4", -# CHECK-NEXT: "HWPort5", -# CHECK-NEXT: "HWPort6", -# CHECK-NEXT: "HWPort7" +# CHECK-NEXT: }, +# CHECK-NEXT: "ResourcePressureView": { +# CHECK-NEXT: "ResourcePressureInfo": [ +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 0, +# CHECK-NEXT: "ResourceIndex": 8, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 1, +# CHECK-NEXT: "ResourceIndex": 7, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 2, +# CHECK-NEXT: "ResourceIndex": 3, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 3, +# CHECK-NEXT: "ResourceIndex": 2, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 2, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 3, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 7, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "InstructionIndex": 4, +# CHECK-NEXT: "ResourceIndex": 8, +# CHECK-NEXT: "ResourceUsage": 1 +# CHECK-NEXT: } +# CHECK-NEXT: ] +# CHECK-NEXT: }, +# CHECK-NEXT: "SummaryView": { +# CHECK-NEXT: "BlockRThroughput": 1, +# CHECK-NEXT: "DispatchWidth": 4, +# CHECK-NEXT: "IPC": 3.883495145631068, +# CHECK-NEXT: "Instructions": 400, +# CHECK-NEXT: "Iterations": 100, +# CHECK-NEXT: "TotalCycles": 103, +# CHECK-NEXT: "TotaluOps": 400, +# CHECK-NEXT: "uOpsPerCycle": 3.883495145631068 +# CHECK-NEXT: }, +# CHECK-NEXT: "TimelineView": { +# CHECK-NEXT: "TimelineInfo": [ +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "CycleDispatched": 0, +# CHECK-NEXT: "CycleExecuted": 2, +# CHECK-NEXT: "CycleIssued": 1, +# CHECK-NEXT: "CycleReady": 0, +# CHECK-NEXT: "CycleRetired": 3 +# CHECK-NEXT: } # CHECK-NEXT: ] # CHECK-NEXT: } -# CHECK-NEXT: }, -# CHECK-NEXT: "ResourcePressureView": { -# CHECK-NEXT: "ResourcePressureInfo": [ -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 0, -# CHECK-NEXT: "ResourceIndex": 8, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 1, -# CHECK-NEXT: "ResourceIndex": 7, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 2, -# CHECK-NEXT: "ResourceIndex": 3, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 3, -# CHECK-NEXT: "ResourceIndex": 2, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 4, -# CHECK-NEXT: "ResourceIndex": 2, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 4, -# CHECK-NEXT: "ResourceIndex": 3, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 4, -# CHECK-NEXT: "ResourceIndex": 7, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "InstructionIndex": 4, -# CHECK-NEXT: "ResourceIndex": 8, -# CHECK-NEXT: "ResourceUsage": 1 -# CHECK-NEXT: } -# CHECK-NEXT: ] -# CHECK-NEXT: }, -# CHECK-NEXT: "SummaryView": { -# CHECK-NEXT: "BlockRThroughput": 1, -# CHECK-NEXT: "DispatchWidth": 4, -# CHECK-NEXT: "IPC": 3.883495145631068, -# CHECK-NEXT: "Instructions": 400, -# CHECK-NEXT: "Iterations": 100, -# CHECK-NEXT: "TotalCycles": 103, -# CHECK-NEXT: "TotaluOps": 400, -# CHECK-NEXT: "uOpsPerCycle": 3.883495145631068 -# CHECK-NEXT: }, -# CHECK-NEXT: "TimelineView": { -# CHECK-NEXT: "TimelineInfo": [ -# CHECK-NEXT: { -# CHECK-NEXT: "CycleDispatched": 0, -# CHECK-NEXT: "CycleExecuted": 2, -# CHECK-NEXT: "CycleIssued": 1, -# CHECK-NEXT: "CycleReady": 0, -# CHECK-NEXT: "CycleRetired": 3 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "CycleDispatched": 0, -# CHECK-NEXT: "CycleExecuted": 2, -# CHECK-NEXT: "CycleIssued": 1, -# CHECK-NEXT: "CycleReady": 0, -# CHECK-NEXT: "CycleRetired": 3 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "CycleDispatched": 0, -# CHECK-NEXT: "CycleExecuted": 2, -# CHECK-NEXT: "CycleIssued": 1, -# CHECK-NEXT: "CycleReady": 0, -# CHECK-NEXT: "CycleRetired": 3 -# CHECK-NEXT: }, -# CHECK-NEXT: { -# CHECK-NEXT: "CycleDispatched": 0, -# CHECK-NEXT: "CycleExecuted": 2, -# CHECK-NEXT: "CycleIssued": 1, -# CHECK-NEXT: "CycleReady": 0, -# CHECK-NEXT: "CycleRetired": 3 -# CHECK-NEXT: } -# CHECK-NEXT: ] # CHECK-NEXT: } # CHECK-NEXT: } diff --git a/llvm/tools/llvm-mca/PipelinePrinter.h b/llvm/tools/llvm-mca/PipelinePrinter.h --- a/llvm/tools/llvm-mca/PipelinePrinter.h +++ b/llvm/tools/llvm-mca/PipelinePrinter.h @@ -48,6 +48,7 @@ } void printReport(llvm::raw_ostream &OS) const; + json::Object getJSONReportRegion() const; }; } // namespace mca } // namespace llvm diff --git a/llvm/tools/llvm-mca/PipelinePrinter.cpp b/llvm/tools/llvm-mca/PipelinePrinter.cpp --- a/llvm/tools/llvm-mca/PipelinePrinter.cpp +++ b/llvm/tools/llvm-mca/PipelinePrinter.cpp @@ -17,19 +17,21 @@ namespace llvm { namespace mca { +json::Object PipelinePrinter::getJSONReportRegion() const { + json::Object JO; + for (const auto &V : Views) { + if (V->isSerializable()) { + JO.try_emplace(V->getNameAsString().str(), V->toJSON()); + } + } + return JO; +} + void PipelinePrinter::printReport(llvm::raw_ostream &OS) const { json::Object JO; for (const auto &V : Views) { - if ((OutputKind == View::OK_JSON)) { - if (V->isSerializable()) { - JO.try_emplace(V->getNameAsString().str(), V->toJSON()); - } - } else { V->printView(OS); - } } - if (OutputKind == View::OK_JSON) - OS << formatv("{0:2}", json::Value(std::move(JO))) << "\n"; } } // namespace mca. } // namespace llvm diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp --- a/llvm/tools/llvm-mca/llvm-mca.cpp +++ b/llvm/tools/llvm-mca/llvm-mca.cpp @@ -523,6 +523,7 @@ *STI, *MRI, mc::InitMCTargetOptionsFromFlags())); assert(MAB && "Unable to create asm backend!"); + json::Object JSONOutput; for (const std::unique_ptr &Region : Regions) { // Skip empty code regions. if (Region->empty()) @@ -530,7 +531,8 @@ // Don't print the header of this region if it is the default region, and // it doesn't have an end location. - if (Region->startLoc().isValid() || Region->endLoc().isValid()) { + if (!PrintJson && + (Region->startLoc().isValid() || Region->endLoc().isValid())) { TOF->os() << "\n[" << RegionIdx++ << "] Code Region"; StringRef Desc = Region->getDescription(); if (!Desc.empty()) @@ -590,7 +592,13 @@ if (!runPipeline(*P)) return 1; - Printer.printReport(TOF->os()); + if (PrintJson) + JSONOutput.try_emplace(!Region->getDescription().empty() + ? Region->getDescription().str() + : "main", + Printer.getJSONReportRegion()); + else + Printer.printReport(TOF->os()); continue; } @@ -659,12 +667,21 @@ if (!runPipeline(*P)) return 1; - Printer.printReport(TOF->os()); + if (PrintJson) + JSONOutput.try_emplace(!Region->getDescription().empty() + ? Region->getDescription().str() + : "main", + Printer.getJSONReportRegion()); + else + Printer.printReport(TOF->os()); // Clear the InstrBuilder internal state in preparation for another round. IB.clear(); } + if (PrintJson) + TOF->os() << formatv("{0:2}", json::Value(std::move(JSONOutput))) << "\n"; + TOF->keep(); return 0; }