diff --git a/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp b/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
--- a/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
@@ -23,7 +23,9 @@
 
 static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand) {
   return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
-         Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
+         Cand.SU->getInstr()->getOpcode() == PPC::ADDI8 ||
+         Cand.SU->getInstr()->getOpcode() == PPC::LI ||
+         Cand.SU->getInstr()->getOpcode() == PPC::LI8;
 }
 
 bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
@@ -32,15 +34,16 @@
   if (DisableAddiLoadHeuristic)
     return false;
 
-  SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
-  SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
-  if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
-    TryCand.Reason = Stall;
-    return true;
-  }
-  if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {
-    TryCand.Reason = NoCand;
-    return true;
+  if (Zone.isTop()) {
+    if (tryGreater(isADDIInstr(TryCand) && Cand.SU->getInstr()->mayLoad(),
+                  isADDIInstr(Cand) && TryCand.SU->getInstr()->mayLoad(),
+                  TryCand, Cand, Stall))
+      return TryCand.Reason != NoCand;
+  } else {
+    if (tryLess(isADDIInstr(TryCand) && Cand.SU->getInstr()->mayLoad(),
+                isADDIInstr(Cand) && TryCand.SU->getInstr()->mayLoad(),
+                TryCand, Cand, Stall))
+      return TryCand.Reason != NoCand;
   }
 
   return false;
@@ -167,9 +170,10 @@
   if (!EnableAddiHeuristic)
     return false;
 
-  if (isADDIInstr(TryCand) && !isADDIInstr(Cand)) {
-    TryCand.Reason = Stall;
-    return true;
+  if (tryGreater(isADDIInstr(TryCand) && Cand.SU->getInstr()->mayLoad(),
+                 isADDIInstr(Cand) && TryCand.SU->getInstr()->mayLoad(),
+                 TryCand, Cand, Stall)) {
+    return TryCand.Reason != NoCand;
   }
   return false;
 }
diff --git a/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll b/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
--- a/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
@@ -724,8 +724,8 @@
 ;
 ; CHECK-32-LABEL: conv2dlbTestuiVar:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -32
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 4, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    lwzx 3, 4, 3
 ; CHECK-32-NEXT:    stw 3, -4(1)
@@ -1523,8 +1523,8 @@
 define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
 ; CHECK-64-LABEL: insertVarI:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
@@ -1532,8 +1532,8 @@
 ;
 ; CHECK-32-LABEL: insertVarI:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stwx 3, 5, 4
 ; CHECK-32-NEXT:    lxv 34, -16(1)
diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll
--- a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll
@@ -11,8 +11,8 @@
 ;
 ; CHECK-32-LABEL: test1:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
@@ -30,8 +30,8 @@
 ;
 ; CHECK-32-LABEL: test2:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 4, 3
 ; CHECK-32-NEXT:    extsb 3, 3
@@ -51,8 +51,8 @@
 ;
 ; CHECK-32-LABEL: test3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
@@ -71,8 +71,8 @@
 ;
 ; CHECK-32-LABEL: test4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhax 3, 4, 3
 ; CHECK-32-NEXT:    blr
@@ -90,8 +90,8 @@
 ;
 ; CHECK-32-LABEL: test5:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
@@ -110,8 +110,8 @@
 ;
 ; CHECK-32-LABEL: test6:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll
--- a/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll
@@ -12,8 +12,8 @@
 ;
 ; CHECK-32-LABEL: test_add1:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
@@ -38,8 +38,8 @@
 ;
 ; CHECK-32-LABEL: test_add2:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
@@ -65,8 +65,8 @@
 ;
 ; CHECK-32-LABEL: test_add3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
@@ -92,8 +92,8 @@
 ;
 ; CHECK-32-LABEL: test_add4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
@@ -119,8 +119,8 @@
 ;
 ; CHECK-32-LABEL: test_add5:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
@@ -142,8 +142,8 @@
 ;
 ; CHECK-32-LABEL: test_add6:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll b/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
--- a/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
@@ -9,8 +9,8 @@
 define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testByte:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    clrldi 4, 4, 60
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stbx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
@@ -18,8 +18,8 @@
 ;
 ; CHECK-32-LABEL: testByte:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 6, 28
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stbx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
@@ -45,8 +45,8 @@
 define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testHalf:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 1, 28, 30
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    sthx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
@@ -54,8 +54,8 @@
 ;
 ; CHECK-32-LABEL: testHalf:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 6, 1, 28, 30
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    sthx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
@@ -82,8 +82,8 @@
 define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testWord:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
@@ -91,8 +91,8 @@
 ;
 ; CHECK-32-LABEL: testWord:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 6, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stwx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
@@ -154,8 +154,8 @@
 define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testDoubleword:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stdx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
@@ -262,8 +262,8 @@
 define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
 ; CHECK-64-LABEL: testFloat1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-DAG:     rlwinm 3, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 4, 1, -16
+; CHECK-64-NEXT:    rlwinm 3, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 4, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stfsx 1, 4, 3
 ; CHECK-64-NEXT:    lxv 34, -16(1)
@@ -302,8 +302,8 @@
 ; CHECK-64-LABEL: testFloat2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lwz 6, 0(3)
-; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
@@ -318,8 +318,8 @@
 ; CHECK-32-LABEL: testFloat2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 6, 0(3)
-; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    stwx 6, 7, 4
@@ -365,8 +365,8 @@
 ; CHECK-64-LABEL: testFloat3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
-; CHECK-64-DAG:         rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:    addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    lwzx 6, 3, 6
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
@@ -384,8 +384,8 @@
 ; CHECK-32-LABEL: testFloat3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 6, 1
-; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    lwzx 6, 3, 6
 ; CHECK-32-NEXT:    stxv 34, -32(1)
@@ -575,7 +575,7 @@
 define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {
 ; CHECK-64-LABEL: testDouble1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64:         rlwinm 3, 4, 3, 28, 28
+; CHECK-64-NEXT:    rlwinm 3, 4, 3, 28, 28
 ; CHECK-64-NEXT:    addi 4, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stfdx 1, 4, 3
@@ -584,8 +584,8 @@
 ;
 ; CHECK-32-LABEL: testDouble1:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
@@ -601,8 +601,8 @@
 ;
 ; CHECK-32-P10-LABEL: testDouble1:
 ; CHECK-32-P10:       # %bb.0: # %entry
-; CHECK-32-P10-DAG:     addi 4, 1, -16
-; CHECK-32-P10-DAG:     rlwinm 3, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    addi 4, 1, -16
 ; CHECK-32-P10-NEXT:    stxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-P10-NEXT:    lxv 34, -16(1)
@@ -616,8 +616,8 @@
 ; CHECK-64-LABEL: testDouble2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 6, 0(3)
-; CHECK-64-DAG:         rlwinm 4, 4, 3, 28, 28
-; CHECK-64-DAG:    addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stdx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
@@ -633,8 +633,8 @@
 ; CHECK-32-LABEL: testDouble2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfd 0, 0(3)
-; CHECK-32-NEXT:    addi 6, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-NEXT:    addi 6, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-NEXT:    stfdx 0, 6, 4
@@ -661,8 +661,8 @@
 ; CHECK-32-P10-LABEL: testDouble2:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    lfd 0, 0(3)
-; CHECK-32-P10-DAG:     addi 6, 1, -32
-; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-NEXT:    addi 6, 1, -32
 ; CHECK-32-P10-NEXT:    stxv 34, -32(1)
 ; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
@@ -688,8 +688,8 @@
 ; CHECK-64-LABEL: testDouble3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
-; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
-; CHECK-64-DAG:     addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    ldx 6, 3, 6
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stdx 6, 7, 4
diff --git a/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll b/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
--- a/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
+++ b/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
@@ -445,9 +445,9 @@
 define void @_Z14WriteStaticPtrv() {
 ; CHECK-LABEL: _Z14WriteStaticPtrv:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pld r3, _ZL3ptr@PCREL(0), 1
-; CHECK-NEXT:    li r4, 3
-; CHECK-NEXT:    stw r4, 0(r3)
+; CHECK-NEXT:    pld r4, _ZL3ptr@PCREL(0), 1
+; CHECK-NEXT:    li r3, 3
+; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load i32*, i32** @_ZL3ptr, align 8
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
--- a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
@@ -29,10 +29,10 @@
 ; CHECK-NEXT:    addi r3, r3, 4004
 ; CHECK-NEXT:    li r6, -3
 ; CHECK-NEXT:    li r7, -2
-; CHECK-NEXT:    li r8, -1
-; CHECK-NEXT:    iselgt r5, r4, r5
-; CHECK-NEXT:    mtctr r5
+; CHECK-NEXT:    iselgt r8, r4, r5
 ; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    mtctr r8
+; CHECK-NEXT:    li r8, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    ldx r9, r3, r6
@@ -110,10 +110,10 @@
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r5, 1
 ; CHECK-NEXT:    addi r6, r3, 4002
-; CHECK-NEXT:    li r7, -1
-; CHECK-NEXT:    iselgt r3, r4, r5
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    iselgt r7, r4, r5
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ldx r8, r6, r7
@@ -207,13 +207,13 @@
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r5, 1
 ; CHECK-NEXT:    addi r9, r3, 4002
+; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r6, -1
 ; CHECK-NEXT:    li r7, 3
 ; CHECK-NEXT:    li r8, 5
+; CHECK-NEXT:    iselgt r10, r4, r5
+; CHECK-NEXT:    mtctr r10
 ; CHECK-NEXT:    li r10, 9
-; CHECK-NEXT:    iselgt r3, r4, r5
-; CHECK-NEXT:    mtctr r3
-; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ldx r11, r9, r6
@@ -327,10 +327,10 @@
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    addi r3, r3, 3998
-; CHECK-NEXT:    li r7, -1
-; CHECK-NEXT:    iselgt r5, r4, r6
-; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    iselgt r7, r4, r6
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, -1
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ldu r8, 4(r3)
@@ -409,10 +409,10 @@
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    addi r5, r3, 4000
 ; CHECK-NEXT:    addi r3, r3, 4003
-; CHECK-NEXT:    li r7, -1
-; CHECK-NEXT:    iselgt r6, r4, r6
-; CHECK-NEXT:    mtctr r6
+; CHECK-NEXT:    iselgt r7, r4, r6
 ; CHECK-NEXT:    li r6, 0
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    lbzu r8, 1(r5)
@@ -496,10 +496,10 @@
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    addi r3, r3, 4001
 ; CHECK-NEXT:    addi r4, r4, 4001
-; CHECK-NEXT:    li r7, 9
-; CHECK-NEXT:    iselgt r6, r5, r6
-; CHECK-NEXT:    mtctr r6
+; CHECK-NEXT:    iselgt r7, r5, r6
 ; CHECK-NEXT:    li r6, 0
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, 9
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ld r8, 0(r3)
@@ -626,17 +626,17 @@
 ; CHECK-NEXT:    li r7, 1
 ; CHECK-NEXT:    addi r6, r3, 4009
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    iselgt r4, r4, r7
+; CHECK-NEXT:    iselgt r0, r4, r7
 ; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, -9
 ; CHECK-NEXT:    li r8, -7
 ; CHECK-NEXT:    li r9, -6
 ; CHECK-NEXT:    li r10, 1
 ; CHECK-NEXT:    li r11, 1
 ; CHECK-NEXT:    li r12, 1
-; CHECK-NEXT:    li r30, 1
 ; CHECK-NEXT:    ld r5, 0(r5)
-; CHECK-NEXT:    mtctr r4
-; CHECK-NEXT:    li r4, -9
+; CHECK-NEXT:    mtctr r0
+; CHECK-NEXT:    li r30, 1
 ; CHECK-NEXT:    li r29, 1
 ; CHECK-NEXT:    addi r5, r5, -1
 ; CHECK-NEXT:    b .LBB6_4
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
--- a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
@@ -44,16 +44,16 @@
 define dso_local void @WriteGlobalVarChar() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarChar:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valChar@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3
-; LE-NEXT:    stb r4, 0(r3)
+; LE-NEXT:    pld r4, valChar@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3
+; LE-NEXT:    stb r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarChar:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valChar@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3
-; BE-NEXT:    stb r4, 0(r3)
+; BE-NEXT:    pld r4, valChar@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3
+; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i8 3, i8* @valChar, align 1
@@ -85,16 +85,16 @@
 define dso_local void @WriteGlobalVarShort() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarShort:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valShort@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3
-; LE-NEXT:    sth r4, 0(r3)
+; LE-NEXT:    pld r4, valShort@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3
+; LE-NEXT:    sth r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarShort:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valShort@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3
-; BE-NEXT:    sth r4, 0(r3)
+; BE-NEXT:    pld r4, valShort@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3
+; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i16 3, i16* @valShort, align 2
@@ -125,16 +125,16 @@
 define dso_local void @WriteGlobalVarInt() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarInt:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valInt@got@pcrel(0), 1
-; LE-NEXT:    li r4, 33
-; LE-NEXT:    stw r4, 0(r3)
+; LE-NEXT:    pld r4, valInt@got@pcrel(0), 1
+; LE-NEXT:    li r3, 33
+; LE-NEXT:    stw r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarInt:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valInt@got@pcrel(0), 1
-; BE-NEXT:    li r4, 33
-; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    pld r4, valInt@got@pcrel(0), 1
+; BE-NEXT:    li r3, 33
+; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 33, i32* @valInt, align 4
@@ -165,16 +165,16 @@
 define dso_local void @WriteGlobalVarUnsigned() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarUnsigned:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
-; LE-NEXT:    li r4, 33
-; LE-NEXT:    stw r4, 0(r3)
+; LE-NEXT:    pld r4, valUnsigned@got@pcrel(0), 1
+; LE-NEXT:    li r3, 33
+; LE-NEXT:    stw r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarUnsigned:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
-; BE-NEXT:    li r4, 33
-; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    pld r4, valUnsigned@got@pcrel(0), 1
+; BE-NEXT:    li r3, 33
+; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 33, i32* @valUnsigned, align 4
@@ -206,16 +206,16 @@
 define dso_local void @WriteGlobalVarLong() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarLong:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valLong@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3333
-; LE-NEXT:    std r4, 0(r3)
+; LE-NEXT:    pld r4, valLong@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3333
+; LE-NEXT:    std r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarLong:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valLong@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3333
-; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    pld r4, valLong@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3333
+; BE-NEXT:    std r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i64 3333, i64* @valLong, align 8
@@ -246,22 +246,22 @@
 define dso_local void @WriteGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalPtr:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; LE-NEXT:    pld r4, ptr@got@pcrel(0), 1
 ; LE-NEXT:  .Lpcrel6:
-; LE-NEXT:    li r4, 3
+; LE-NEXT:    li r3, 3
 ; LE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
-; LE-NEXT:    ld r3, 0(r3)
-; LE-NEXT:    stw r4, 0(r3)
+; LE-NEXT:    ld r4, 0(r4)
+; LE-NEXT:    stw r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalPtr:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; BE-NEXT:    pld r4, ptr@got@pcrel(0), 1
 ; BE-NEXT:  .Lpcrel6:
-; BE-NEXT:    li r4, 3
+; BE-NEXT:    li r3, 3
 ; BE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
-; BE-NEXT:    ld r3, 0(r3)
-; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    ld r4, 0(r4)
+; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32*, i32** @ptr, align 8
@@ -307,16 +307,16 @@
 define dso_local void @WriteGlobalArray() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalArray:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, array@got@pcrel(0), 1
-; LE-NEXT:    li r4, 5
-; LE-NEXT:    stw r4, 12(r3)
+; LE-NEXT:    pld r4, array@got@pcrel(0), 1
+; LE-NEXT:    li r3, 5
+; LE-NEXT:    stw r3, 12(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalArray:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, array@got@pcrel(0), 1
-; BE-NEXT:    li r4, 5
-; BE-NEXT:    stw r4, 12(r3)
+; BE-NEXT:    pld r4, array@got@pcrel(0), 1
+; BE-NEXT:    li r3, 5
+; BE-NEXT:    stw r3, 12(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 5, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array, i64 0, i64 3), align 4
@@ -347,16 +347,16 @@
 define dso_local void @WriteGlobalStruct() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalStruct:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, structure@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3
-; LE-NEXT:    stw r4, 4(r3)
+; LE-NEXT:    pld r4, structure@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3
+; LE-NEXT:    stw r3, 4(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalStruct:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, structure@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3
-; BE-NEXT:    stw r4, 4(r3)
+; BE-NEXT:    pld r4, structure@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3
+; BE-NEXT:    stw r3, 4(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 3, i32* getelementptr inbounds (%struct.Struct, %struct.Struct* @structure, i64 0, i32 2), align 4
@@ -365,8 +365,7 @@
 
 define dso_local void @ReadFuncPtr() local_unnamed_addr  {
 ; LE-LABEL: ReadFuncPtr:
-; LE:         .localentry ReadFuncPtr, 1
-; LE-NEXT:  # %bb.0: # %entry
+; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
 ; LE-NEXT:  .Lpcrel9:
 ; LE-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
@@ -376,8 +375,7 @@
 ; LE-NEXT:    #TC_RETURNr8 ctr 0
 ;
 ; BE-LABEL: ReadFuncPtr:
-; BE:         .localentry ReadFuncPtr, 1
-; BE-NEXT:  # %bb.0: # %entry
+; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
 ; BE-NEXT:  .Lpcrel9:
 ; BE-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
diff --git a/llvm/test/CodeGen/PowerPC/pr48519.ll b/llvm/test/CodeGen/PowerPC/pr48519.ll
--- a/llvm/test/CodeGen/PowerPC/pr48519.ll
+++ b/llvm/test/CodeGen/PowerPC/pr48519.ll
@@ -190,8 +190,8 @@
 ; CHECK-P9:       # %bb.0: # %bb
 ; CHECK-P9-NEXT:    ld r3, 0(r3)
 ; CHECK-P9-NEXT:    cmpdi r3, 0
-; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    li r3, 0
+; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    crnot 4*cr5+lt, eq
 ; CHECK-P9-NEXT:    b .LBB2_2
 ; CHECK-P9-NEXT:    .p2align 5
diff --git a/llvm/test/CodeGen/PowerPC/sms-simple.ll b/llvm/test/CodeGen/PowerPC/sms-simple.ll
--- a/llvm/test/CodeGen/PowerPC/sms-simple.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-simple.ll
@@ -9,12 +9,12 @@
 define dso_local i32* @foo() local_unnamed_addr {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis r5, r2, y@toc@ha
-; CHECK-NEXT:    li r7, 340
-; CHECK-NEXT:    addi r3, r5, y@toc@l
-; CHECK-NEXT:    lwz r6, y@toc@l(r5)
+; CHECK-NEXT:    addis r4, r2, y@toc@ha
+; CHECK-NEXT:    li r5, 340
+; CHECK-NEXT:    lwz r6, y@toc@l(r4)
+; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    addis r5, r2, x@toc@ha
-; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    addi r3, r4, y@toc@l
 ; CHECK-NEXT:    addi r5, r5, x@toc@l
 ; CHECK-NEXT:    addi r4, r3, -8
 ; CHECK-NEXT:    addi r5, r5, -8
diff --git a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
--- a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
+++ b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
@@ -75,11 +75,11 @@
 define i64 @test_xaddrX4_loop(i8* %p) {
 ; CHECK-LABEL: test_xaddrX4_loop:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r5, 8
 ; CHECK-NEXT:    addi r4, r3, -8
-; CHECK-NEXT:    li r3, 8
-; CHECK-NEXT:    li r5, 3
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    mtctr r5
+; CHECK-NEXT:    li r5, 3
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB4_1: # %for.body
 ; CHECK-NEXT:    #
diff --git a/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll b/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
--- a/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
@@ -24,8 +24,8 @@
 ;
 ; CHECK-P9-LABEL: testByte:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    clrldi r3, r6, 60
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stbx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
@@ -53,8 +53,8 @@
 ;
 ; CHECK-P9-LABEL: testHalf:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 1, 28, 30
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    sthx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
@@ -82,8 +82,8 @@
 ;
 ; CHECK-P9-LABEL: testWord:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 2, 28, 29
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stwx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
@@ -139,8 +139,8 @@
 ;
 ; CHECK-P9-LABEL: testDoubleword:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 3, 28, 28
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stdx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
@@ -217,8 +217,8 @@
 ;
 ; CHECK-P9-LABEL: testFloat1:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 2, 28, 29
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stfsx f1, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
@@ -470,8 +470,8 @@
 ;
 ; CHECK-P9-LABEL: testDouble1:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 3, 28, 28
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stfdx f1, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)