diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9754,8 +9754,8 @@ "this builtin requires 'dsp r2' ASE, please use -mdspr2">; def err_mips_builtin_requires_msa : Error< "this builtin requires 'msa' ASE, please use -mmsa">; -def err_ppc_builtin_only_on_pwr7 : Error< - "this builtin is only valid on POWER7 or later CPUs">; +def err_ppc_builtin_only_on_arch : Error< + "this builtin is only valid on POWER%0 or later CPUs">; def err_ppc_invalid_use_mma_type : Error< "invalid use of PPC MMA type">; def err_x86_builtin_invalid_rounding : Error< diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -74,6 +74,9 @@ bool HasP10Vector = false; bool HasPCRelativeMemops = false; bool HasPrefixInstrs = false; + bool IsISA2_07 = false; + bool IsISA3_0 = false; + bool IsISA3_1 = false; protected: std::string ABI; diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -73,6 +73,12 @@ HasROPProtect = true; } else if (Feature == "+privileged") { HasPrivileged = true; + } else if (Feature == "+isa-v207-instructions") { + IsISA2_07 = true; + } else if (Feature == "+isa-v30-instructions") { + IsISA3_0 = true; + } else if (Feature == "+isa-v31-instructions") { + IsISA3_1 = true; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -378,6 +384,15 @@ .Case("e500", true) .Default(false); + Features["isa-v207-instructions"] = llvm::StringSwitch(CPU) + .Case("ppc64le", true) + .Case("pwr9", true) + .Case("pwr8", true) + .Default(false); + + Features["isa-v30-instructions"] = + llvm::StringSwitch(CPU).Case("pwr9", true).Default(false); + // Power10 includes all the same features as Power9 plus any features specific // to the Power10 core. if (CPU == "pwr10" || CPU == "power10") { @@ -434,6 +449,7 @@ Features["power10-vector"] = true; Features["pcrelative-memops"] = true; Features["prefix-instrs"] = true; + Features["isa-v31-instructions"] = true; return; } @@ -464,6 +480,9 @@ .Case("mma", HasMMA) .Case("rop-protect", HasROPProtect) .Case("privileged", HasPrivileged) + .Case("isa-v207-instructions", IsISA2_07) + .Case("isa-v30-instructions", IsISA3_0) + .Case("isa-v31-instructions", IsISA3_1) .Default(false); } diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3272,13 +3272,23 @@ return false; } -static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall, - StringRef FeatureToCheck, unsigned DiagID) { +static bool SemaArchFeatureCheck(Sema &S, CallExpr *TheCall, + StringRef FeatureToCheck, int Arch) { if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck)) - return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange(); + return S.Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_arch) + << Arch << TheCall->getSourceRange(); return false; } +// Commented out to avoid unused error during build. +// static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall, +// StringRef FeatureToCheck, unsigned DiagID) { +// if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck)) +// return S.Diag(TheCall->getBeginLoc(), DiagID) << +// TheCall->getSourceRange(); +// return false; +//} + bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall) { unsigned i = 0, l = 0, u = 0; @@ -3317,18 +3327,14 @@ case PPC::BI__builtin_divweu: case PPC::BI__builtin_divde: case PPC::BI__builtin_divdeu: - return SemaFeatureCheck(*this, TheCall, "extdiv", - diag::err_ppc_builtin_only_on_pwr7); + return SemaArchFeatureCheck(*this, TheCall, "extdiv", 7); case PPC::BI__builtin_bpermd: - return SemaFeatureCheck(*this, TheCall, "bpermd", - diag::err_ppc_builtin_only_on_pwr7); + return SemaArchFeatureCheck(*this, TheCall, "bpermd", 7); case PPC::BI__builtin_unpack_vector_int128: - return SemaFeatureCheck(*this, TheCall, "vsx", - diag::err_ppc_builtin_only_on_pwr7) || + return SemaArchFeatureCheck(*this, TheCall, "vsx", 7) || SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); case PPC::BI__builtin_pack_vector_int128: - return SemaFeatureCheck(*this, TheCall, "vsx", - diag::err_ppc_builtin_only_on_pwr7); + return SemaArchFeatureCheck(*this, TheCall, "vsx", 7); case PPC::BI__builtin_altivec_vgnb: return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7); case PPC::BI__builtin_altivec_vec_replace_elt: diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -210,9 +210,13 @@ def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", "Treat vector data stream cache control instructions as deprecated">; +def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", + "true", + "Enable instructions in ISA 2.07.">; def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", "true", - "Enable instructions in ISA 3.0.">; + "Enable instructions in ISA 3.0.", + [FeatureISA2_07]>; def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", "true", "Enable instructions in ISA 3.1.", diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1176,6 +1176,7 @@ : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; +def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; def HasFPU : Predicate<"Subtarget->hasFPU()">; def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -146,6 +146,7 @@ bool HasStoreFusion; bool HasAddiLoadFusion; bool HasAddisLoadFusion; + bool IsISA2_07; bool IsISA3_0; bool IsISA3_1; bool UseLongCalls; @@ -319,6 +320,7 @@ bool hasHTM() const { return HasHTM; } bool hasFloat128() const { return HasFloat128; } + bool isISA2_07() const { return IsISA2_07; } bool isISA3_0() const { return IsISA3_0; } bool isISA3_1() const { return IsISA3_1; } bool useLongCalls() const { return UseLongCalls; } diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -126,6 +126,7 @@ HasStoreFusion = false; HasAddiLoadFusion = false; HasAddisLoadFusion = false; + IsISA2_07 = false; IsISA3_0 = false; IsISA3_1 = false; UseLongCalls = false;