diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9756,6 +9756,8 @@ "this builtin requires 'msa' ASE, please use -mmsa">; def err_ppc_builtin_only_on_pwr7 : Error< "this builtin is only valid on POWER7 or later CPUs">; +def err_ppc_builtin_only_on_pwr8 : Error< + "this builtin is only valid on POWER8 or later CPUs">; def err_ppc_invalid_use_mma_type : Error< "invalid use of PPC MMA type">; def err_x86_builtin_invalid_rounding : Error< diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -74,6 +74,7 @@ bool HasP10Vector = false; bool HasPCRelativeMemops = false; bool HasPrefixInstrs = false; + bool IsISA2_07 = false; protected: std::string ABI; diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -422,6 +422,14 @@ return false; } + Features["isa-v207-instructions"] = llvm::StringSwitch(CPU) + .Case("pwr9", true) + .Case("ppc64le", true) + .Case("pwr8", true) + .Default(false); + Features["isa-v30-instructions"] = + llvm::StringSwitch(CPU).Case("pwr9", true).Default(false); + return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); } @@ -434,6 +442,9 @@ Features["power10-vector"] = true; Features["pcrelative-memops"] = true; Features["prefix-instrs"] = true; + Features["isa-v207-instructions"] = true; + Features["isa-v30-instructions"] = true; + Features["isa-v31-instructions"] = true; return; } @@ -464,6 +475,7 @@ .Case("mma", HasMMA) .Case("rop-protect", HasROPProtect) .Case("privileged", HasPrivileged) + .Case("isa-v207-instructions", IsISA2_07) .Default(false); } diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -210,9 +210,13 @@ def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", "Treat vector data stream cache control instructions as deprecated">; +def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", + "true", + "Enable instructions in ISA 2.07.">; def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", "true", - "Enable instructions in ISA 3.0.">; + "Enable instructions in ISA 3.0.", + [FeatureISA2_07]>; def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", "true", "Enable instructions in ISA 3.1.", @@ -327,7 +331,8 @@ FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic, - FeaturePredictableSelectIsExpensive + FeaturePredictableSelectIsExpensive, + FeatureISA2_07 ]; list P8SpecificFeatures = [FeatureAddiLoadFusion, diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -146,6 +146,7 @@ bool HasStoreFusion; bool HasAddiLoadFusion; bool HasAddisLoadFusion; + bool IsISA2_07; bool IsISA3_0; bool IsISA3_1; bool UseLongCalls; @@ -319,6 +320,7 @@ bool hasHTM() const { return HasHTM; } bool hasFloat128() const { return HasFloat128; } + bool isISA2_07() const { return IsISA2_07; } bool isISA3_0() const { return IsISA3_0; } bool isISA3_1() const { return IsISA3_1; } bool useLongCalls() const { return UseLongCalls; } diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -126,6 +126,7 @@ HasStoreFusion = false; HasAddiLoadFusion = false; HasAddisLoadFusion = false; + IsISA2_07 = false; IsISA3_0 = false; IsISA3_1 = false; UseLongCalls = false;