Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1833,6 +1833,14 @@ case Mips::BLEU: case Mips::BGEU: case Mips::BGTU: + case Mips::BLTL: + case Mips::BLEL: + case Mips::BGEL: + case Mips::BGTL: + case Mips::BLTUL: + case Mips::BLEUL: + case Mips::BGEUL: + case Mips::BGTUL: case Mips::SDivMacro: case Mips::UDivMacro: case Mips::DSDivMacro: @@ -1892,6 +1900,14 @@ case Mips::BLEU: case Mips::BGEU: case Mips::BGTU: + case Mips::BLTL: + case Mips::BLEL: + case Mips::BGEL: + case Mips::BGTL: + case Mips::BLTUL: + case Mips::BLEUL: + case Mips::BGEUL: + case Mips::BGTUL: return expandCondBranches(Inst, IDLoc, Instructions); case Mips::SDivMacro: return expandDiv(Inst, IDLoc, Instructions, false, true); @@ -2584,38 +2600,50 @@ const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr(); unsigned ZeroSrcOpcode, ZeroTrgOpcode; - bool ReverseOrderSLT, IsUnsigned, AcceptsEquality; + bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality; switch (PseudoOpcode) { case Mips::BLT: case Mips::BLTU: + case Mips::BLTL: + case Mips::BLTUL: AcceptsEquality = false; ReverseOrderSLT = false; - IsUnsigned = (PseudoOpcode == Mips::BLTU); + IsUnsigned = ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); + IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL)); ZeroSrcOpcode = Mips::BGTZ; ZeroTrgOpcode = Mips::BLTZ; break; case Mips::BLE: case Mips::BLEU: + case Mips::BLEL: + case Mips::BLEUL: AcceptsEquality = true; ReverseOrderSLT = true; - IsUnsigned = (PseudoOpcode == Mips::BLEU); + IsUnsigned = ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); + IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL)); ZeroSrcOpcode = Mips::BGEZ; ZeroTrgOpcode = Mips::BLEZ; break; case Mips::BGE: case Mips::BGEU: + case Mips::BGEL: + case Mips::BGEUL: AcceptsEquality = true; ReverseOrderSLT = false; - IsUnsigned = (PseudoOpcode == Mips::BGEU); + IsUnsigned = ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); + IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL)); ZeroSrcOpcode = Mips::BLEZ; ZeroTrgOpcode = Mips::BGEZ; break; case Mips::BGT: case Mips::BGTU: + case Mips::BGTL: + case Mips::BGTUL: AcceptsEquality = false; ReverseOrderSLT = true; - IsUnsigned = (PseudoOpcode == Mips::BGTU); + IsUnsigned = ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); + IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL)); ZeroSrcOpcode = Mips::BLTZ; ZeroTrgOpcode = Mips::BGTZ; break; @@ -2768,7 +2796,10 @@ SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? SrcReg : TrgReg)); Instructions.push_back(SetInst); - BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE); + if (!IsLikely) + BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE); + else + BranchInst.setOpcode(AcceptsEquality ? Mips::BEQL : Mips::BNEL); BranchInst.addOperand(MCOperand::createReg(ATRegNum)); BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -836,5 +836,6 @@ def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6; def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset), - !strconcat("b", "\t$offset")>, - MicroMipsR6Inst16; + !strconcat("b", "\t$offset")> { + string DecoderNamespace = "MicroMipsR6"; +} Index: lib/Target/Mips/MipsInstrFormats.td =================================================================== --- lib/Target/Mips/MipsInstrFormats.td +++ lib/Target/Mips/MipsInstrFormats.td @@ -132,7 +132,7 @@ // These are aliases that require C++ handling to convert to the target // instruction, while InstAliases can be handled directly by tblgen. class MipsAsmPseudoInst: - MipsInst { + MipsInst, PredicateControl { let isPseudo = 1; let Pattern = []; } Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1735,24 +1735,38 @@ def BLEU : CondBranchPseudo<"bleu">; def BGEU : CondBranchPseudo<"bgeu">; def BGTU : CondBranchPseudo<"bgtu">; +def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; +def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; +def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; +def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; +def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; +def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; +def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; +def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; + +// FIXME: Predicates are removed because instructions are matched regardless of +// predicates, because PredicateControl was not in the hierarchy. This was +// done to emit more precise error message from expansion function. +// Once the tablegen-erated errors are made better, this needs to be fixed and +// predicates needs to be restored. def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), - "div\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6; + "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), - "divu\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6; + "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), - "ddiv\t$rs, $rt">, ISA_MIPS64_NOT_64R6; + "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), - "ddivu\t$rs, $rt">, ISA_MIPS64_NOT_64R6; + "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), - "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6; + "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), - "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6; + "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions Index: test/MC/Mips/branch-pseudos-bad.s =================================================================== --- test/MC/Mips/branch-pseudos-bad.s +++ test/MC/Mips/branch-pseudos-bad.s @@ -19,3 +19,20 @@ # CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available bgtu $7, $8, local_label # CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + + bltl $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bltul $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + blel $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bleul $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgel $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgeul $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgtl $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgtul $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available Index: test/MC/Mips/branch-pseudos.s =================================================================== --- test/MC/Mips/branch-pseudos.s +++ test/MC/Mips/branch-pseudos.s @@ -187,3 +187,183 @@ # CHECK: bnez $zero, local_label # encoding: [0x14,0x00,A,A] # CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop + + bltl $7,$8,local_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltl $7,$8,global_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltl $7,$0,local_label +# CHECK: bltz $7, local_label # encoding: [0x04,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltl $0,$8,local_label +# CHECK: bgtz $8, local_label # encoding: [0x1d,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltl $0,$0,local_label +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + blel $7,$8,local_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + blel $7,$8,global_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + blel $7,$0,local_label +# CHECK: blez $7, local_label # encoding: [0x18,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + blel $0,$8,local_label +# CHECK: bgez $8, local_label # encoding: [0x05,0x01,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + blel $0,$0,local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + bgel $7,$8,local_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgel $7,$8,global_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgel $7,$0,local_label +# CHECK: bgez $7, local_label # encoding: [0x04,0xe1,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgel $0,$8,local_label +# CHECK: blez $8, local_label # encoding: [0x19,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgel $0,$0,local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + bgtl $7,$8,local_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtl $7,$8,global_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtl $7,$0,local_label +# CHECK: bgtz $7, local_label # encoding: [0x1c,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtl $0,$8,local_label +# CHECK: bltz $8, local_label # encoding: [0x05,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtl $0,$0,local_label +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + bltul $7,$8,local_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltul $7,$8,global_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltul $7,$0,local_label +# CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltul $0,$8,local_label +# CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bltul $0,$0,local_label +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + bleul $7,$8,local_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bleul $7,$8,global_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bleul $7,$0,local_label +# CHECK: beqz $7, local_label # encoding: [0x10,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bleul $0,$8,local_label +# CHECK: beqz $8, local_label # encoding: [0x11,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bleul $0,$0,local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + bgeul $7,$8,local_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgeul $7,$8,global_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgeul $7,$0,local_label +# CHECK: beqz $7, local_label # encoding: [0x10,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgeul $0,$8,local_label +# CHECK: beqz $8, local_label # encoding: [0x11,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgeul $0,$0,local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + + bgtul $7,$8,local_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtul $7,$8,global_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtul $7,$0,local_label +# CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtul $0,$8,local_label +# CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + bgtul $0,$0,local_label +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] Index: test/MC/Mips/mips32r6/invalid.s =================================================================== --- test/MC/Mips/mips32r6/invalid.s +++ test/MC/Mips/mips32r6/invalid.s @@ -2,17 +2,27 @@ # the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text +local_label: .set noreorder .set noat - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved + bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/mips64r6/invalid.s =================================================================== --- test/MC/Mips/mips64r6/invalid.s +++ test/MC/Mips/mips64r6/invalid.s @@ -2,15 +2,25 @@ # the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text +local_label: .set noreorder .set noat - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved + bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled