Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -89,6 +89,8 @@
 
   bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
                            MachineIRBuilder &B) const;
+  bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
+                      MachineIRBuilder &B) const;
 
   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
                       const ArgDescriptor *Arg,
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1628,6 +1628,9 @@
     .clampScalar(0, S32, S64)
     .lower();
 
+  getActionDefinitionsBuilder({G_ROTR, G_ROTL})
+    .custom();
+
   // TODO: Only Try to form v2s16 with legal packed instructions.
   getActionDefinitionsBuilder(G_FSHR)
     .legalFor({{S32, S32}})
@@ -1760,6 +1763,9 @@
     return legalizeFFloor(MI, MRI, B);
   case TargetOpcode::G_BUILD_VECTOR:
     return legalizeBuildVector(MI, MRI, B);
+  case TargetOpcode::G_ROTL:
+  case TargetOpcode::G_ROTR:
+    return legalizeRotate(MI, MRI, B);
   default:
     return false;
   }
@@ -2745,6 +2751,27 @@
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeRotate(
+  MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
+
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src0 = MI.getOperand(1).getReg();
+  Register Src1 = MI.getOperand(2).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  unsigned Opc = TargetOpcode::G_FSHR;
+
+  if (MI.getOpcode() == TargetOpcode::G_ROTL) {
+    if (isPowerOf2_64(DstTy.getScalarSizeInBits()))
+      Src1 = B.buildFNeg(DstTy, Src1).getReg(0);
+    else
+      Opc = TargetOpcode::G_FSHL;
+  }
+
+  B.buildInstr(Opc, {Dst}, {Src0, Src0, Src1});
+  MI.eraseFromParent();
+  return true;
+}
+
 // Check that this is a G_XOR x, -1
 static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI) {
   if (MI.getOpcode() != TargetOpcode::G_XOR)
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
@@ -0,0 +1,306 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=GFX,GFX6
+# RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=GFX,GFX8
+
+---
+name:            rotl_i16
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; GFX6-LABEL: name: rotl_i16
+    ; GFX6: liveins: $sgpr0, $sgpr1
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
+    ; GFX6: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+    ; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[FNEG]], [[C]]
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
+    ; GFX6: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[FNEG]], [[C1]]
+    ; GFX6: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
+    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
+    ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+    ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+    ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+    ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+    ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+    ; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC2]]
+    ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+    ; GFX6: $sgpr0 = COPY [[ANYEXT]](s32)
+    ; GFX8-LABEL: name: rotl_i16
+    ; GFX8: liveins: $sgpr0, $sgpr1
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
+    ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC1]]
+    ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+    ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[FNEG]], [[C]]
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
+    ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[FNEG]], [[C1]]
+    ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+    ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
+    ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND1]](s16)
+    ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
+    ; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[SHL1]], [[LSHR]]
+    ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+    ; GFX8: $sgpr0 = COPY [[ANYEXT]](s32)
+    %2:_(s32) = COPY $sgpr0
+    %0:_(s16) = G_TRUNC %2(s32)
+    %3:_(s32) = COPY $sgpr1
+    %1:_(s16) = G_TRUNC %3(s32)
+    %5:_(s16) = G_ROTL %0, %1(s16)
+    %4:_(s32) = G_ANYEXT %5(s16)
+    $sgpr0 = COPY %4
+
+...
+---
+name:            rotl_i32
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; GFX-LABEL: name: rotl_i32
+    ; GFX: liveins: $sgpr0, $sgpr1
+    ; GFX: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; GFX: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
+    ; GFX: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]
+    ; GFX: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY]], [[FNEG]](s32)
+    ; GFX: $sgpr0 = COPY [[FSHR]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = COPY $sgpr1
+    %2:_(s32) = G_ROTL %0, %1(s32)
+    $sgpr0 = COPY %2
+
+...
+---
+name:            rotl_i64
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+    ; GFX-LABEL: name: rotl_i64
+    ; GFX: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; GFX: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; GFX: [[COPY1:%[0-9]+]]:_(s64) = COPY $sgpr2_sgpr3
+    ; GFX: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
+    ; GFX: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+    ; GFX: [[AND:%[0-9]+]]:_(s64) = G_AND [[FNEG]], [[C]]
+    ; GFX: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+    ; GFX: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[FNEG]], [[C1]]
+    ; GFX: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
+    ; GFX: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; GFX: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s32)
+    ; GFX: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
+    ; GFX: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[TRUNC]](s32)
+    ; GFX: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64)
+    ; GFX: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC1]](s32)
+    ; GFX: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+    ; GFX: $sgpr0_sgpr1 = COPY [[OR]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s64) = COPY $sgpr2_sgpr3
+    %2:_(s64) = G_ROTL %0, %1(s64)
+    $sgpr0_sgpr1 = COPY %2
+
+...
+---
+name:            rotl_v4i32
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+    ; GFX-LABEL: name: rotl_v4i32
+    ; GFX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+    ; GFX: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    ; GFX: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+    ; GFX: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
+    ; GFX: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[UV]]
+    ; GFX: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[UV1]]
+    ; GFX: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[UV2]]
+    ; GFX: [[FNEG3:%[0-9]+]]:_(s32) = G_FNEG [[UV3]]
+    ; GFX: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+    ; GFX: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+    ; GFX: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV4]], [[UV8]], [[FNEG]](s32)
+    ; GFX: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[UV5]], [[UV9]], [[FNEG1]](s32)
+    ; GFX: [[FSHR2:%[0-9]+]]:_(s32) = G_FSHR [[UV6]], [[UV10]], [[FNEG2]](s32)
+    ; GFX: [[FSHR3:%[0-9]+]]:_(s32) = G_FSHR [[UV7]], [[UV11]], [[FNEG3]](s32)
+    ; GFX: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32), [[FSHR2]](s32), [[FSHR3]](s32)
+    ; GFX: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    %1:_(<4 x s32>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+    %2:_(<4 x s32>) = G_ROTL %0, %1(<4 x s32>)
+    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %2
+
+...
+---
+name:            rotr_i16
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; GFX6-LABEL: name: rotr_i16
+    ; GFX6: liveins: $sgpr0, $sgpr1
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+    ; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
+    ; GFX6: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
+    ; GFX6: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
+    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
+    ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+    ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+    ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
+    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+    ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
+    ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+    ; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC2]]
+    ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+    ; GFX6: $sgpr0 = COPY [[ANYEXT]](s32)
+    ; GFX8-LABEL: name: rotr_i16
+    ; GFX8: liveins: $sgpr0, $sgpr1
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
+    ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+    ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
+    ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]]
+    ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+    ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
+    ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND1]](s16)
+    ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
+    ; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[SHL1]], [[LSHR]]
+    ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+    ; GFX8: $sgpr0 = COPY [[ANYEXT]](s32)
+    %2:_(s32) = COPY $sgpr0
+    %0:_(s16) = G_TRUNC %2(s32)
+    %3:_(s32) = COPY $sgpr1
+    %1:_(s16) = G_TRUNC %3(s32)
+    %5:_(s16) = G_ROTR %0, %1(s16)
+    %4:_(s32) = G_ANYEXT %5(s16)
+    $sgpr0 = COPY %4
+
+...
+---
+name:            rotr_i32
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; GFX-LABEL: name: rotr_i32
+    ; GFX: liveins: $sgpr0, $sgpr1
+    ; GFX: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+    ; GFX: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
+    ; GFX: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY]], [[COPY1]](s32)
+    ; GFX: $sgpr0 = COPY [[FSHR]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = COPY $sgpr1
+    %2:_(s32) = G_ROTR %0, %1(s32)
+    $sgpr0 = COPY %2
+
+...
+---
+name:            rotr_i64
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+    ; GFX-LABEL: name: rotr_i64
+    ; GFX: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; GFX: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; GFX: [[COPY1:%[0-9]+]]:_(s64) = COPY $sgpr2_sgpr3
+    ; GFX: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+    ; GFX: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+    ; GFX: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+    ; GFX: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY1]], [[C1]]
+    ; GFX: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
+    ; GFX: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; GFX: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s32)
+    ; GFX: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
+    ; GFX: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[TRUNC]](s32)
+    ; GFX: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64)
+    ; GFX: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC1]](s32)
+    ; GFX: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
+    ; GFX: $sgpr0_sgpr1 = COPY [[OR]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s64) = COPY $sgpr2_sgpr3
+    %2:_(s64) = G_ROTR %0, %1(s64)
+    $sgpr0_sgpr1 = COPY %2
+
+...
+---
+name:            rotr_v4i32
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+
+    ; GFX-LABEL: name: rotr_v4i32
+    ; GFX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
+    ; GFX: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    ; GFX: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+    ; GFX: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+    ; GFX: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+    ; GFX: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
+    ; GFX: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV4]], [[UV8]](s32)
+    ; GFX: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[UV1]], [[UV5]], [[UV9]](s32)
+    ; GFX: [[FSHR2:%[0-9]+]]:_(s32) = G_FSHR [[UV2]], [[UV6]], [[UV10]](s32)
+    ; GFX: [[FSHR3:%[0-9]+]]:_(s32) = G_FSHR [[UV3]], [[UV7]], [[UV11]](s32)
+    ; GFX: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32), [[FSHR2]](s32), [[FSHR3]](s32)
+    ; GFX: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    %1:_(<4 x s32>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
+    %2:_(<4 x s32>) = G_ROTR %0, %1(<4 x s32>)
+    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %2
+
+...