Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4504,7 +4504,7 @@
   else
     return SDValue();
 
-  SDValue Load = DAG.getLoad(MVT::f32, DL, DAG.getEntryNode(),
+  SDValue Load = DAG.getLoad(MVT::f32, DL, Op.getOperand(0),
                              LoadNode->getBasePtr(), MachinePointerInfo());
   SDValue Chain = Load.getValue(1);
   SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load);
Index: llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
===================================================================
--- llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
+++ llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
@@ -284,6 +284,7 @@
 ; CHECK-LE:       // %bb.0:
 ; CHECK-LE-NEXT:    sub sp, sp, #16 // =16
 ; CHECK-LE-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-LE-NEXT:    str w0, [sp, #12]
 ; CHECK-LE-NEXT:    ldr s0, [sp, #12]
 ; CHECK-LE-NEXT:    ushll v0.8h, v0.8b, #0
 ; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $q0
@@ -294,6 +295,7 @@
 ; CHECK-BE:       // %bb.0:
 ; CHECK-BE-NEXT:    sub sp, sp, #16 // =16
 ; CHECK-BE-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-BE-NEXT:    str w0, [sp, #12]
 ; CHECK-BE-NEXT:    ldr s0, [sp, #12]
 ; CHECK-BE-NEXT:    rev32 v0.8b, v0.8b
 ; CHECK-BE-NEXT:    ushll v0.8h, v0.8b, #0