diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -74,6 +74,11 @@ Changes to TableGen ------------------- +Changes to the AArch64 Backend +-------------------------- + +* Introduced support for Armv9-A's Realm Management Extension. + Changes to the ARM Backend -------------------------- diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -475,6 +475,10 @@ defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; +defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>; +defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>; +defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>; +defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>; // Armv8.4-A Translation Lookaside Buffer Instructions (TLBI) let Requires = ["AArch64::FeatureTLB_RMI"] in { @@ -743,6 +747,11 @@ def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>; } +// v9a Realm Management Extension registers +def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>; +def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>; +def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>; + //===---------------------- // Write-only regs //===---------------------- diff --git a/llvm/test/MC/AArch64/arm64-aliases.s b/llvm/test/MC/AArch64/arm64-aliases.s --- a/llvm/test/MC/AArch64/arm64-aliases.s +++ b/llvm/test/MC/AArch64/arm64-aliases.s @@ -511,6 +511,14 @@ ; CHECK: tlbi vmalls12e1 sys #4, c8, c3, #6 ; CHECK: tlbi vmalls12e1is + sys #6, c8, c4, #3 +; CHECK: tlbi rpaos + sys #6, c8, c4, #7 +; CHECK: tlbi rpalos + sys #6, c8, c1, #4 +; CHECK: tlbi paallos + sys #6, c8, c7, #4 +; CHECK: tlbi paall ic ialluis ; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5] @@ -625,6 +633,14 @@ ; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5] tlbi vmalls12e1is ; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5] + tlbi rpaos, x0 +; CHECK: tlbi rpaos, x0 ; encoding: [0x60,0x84,0x0e,0xd5] + tlbi rpalos, x0 +; CHECK: tlbi rpalos, x0 ; encoding: [0xe0,0x84,0x0e,0xd5] + tlbi paallos +; CHECK: tlbi paallos ; encoding: [0x9f,0x81,0x0e,0xd5] + tlbi paall +; CHECK: tlbi paall ; encoding: [0x9f,0x87,0x0e,0xd5] ;----------------------------------------------------------------------------- ; 5.8.5 Vector Arithmetic aliases diff --git a/llvm/test/MC/AArch64/armv9a-rme.s b/llvm/test/MC/AArch64/armv9a-rme.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9a-rme.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple aarch64-arm-none-eabi -show-encoding %s 2>&1 | FileCheck %s + +# CHECK: msr MFAR_EL3, x0 // encoding: [0xa0,0x60,0x1e,0xd5] +# CHECK: msr GPCCR_EL3, x0 // encoding: [0xc0,0x21,0x1e,0xd5] +# CHECK: msr GPTBR_EL3, x0 // encoding: [0x80,0x21,0x1e,0xd5] +msr MFAR_EL3, x0 +msr GPCCR_EL3, x0 +msr GPTBR_EL3, x0 + +# CHECK: mrs x0, MFAR_EL3 // encoding: [0xa0,0x60,0x3e,0xd5] +# CHECK: mrs x0, GPCCR_EL3 // encoding: [0xc0,0x21,0x3e,0xd5] +# CHECK: mrs x0, GPTBR_EL3 // encoding: [0x80,0x21,0x3e,0xd5] +mrs x0, MFAR_EL3 +mrs x0, GPCCR_EL3 +mrs x0, GPTBR_EL3 diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -3461,6 +3461,10 @@ tlbi VALE3 tlbi VMALLS12E1, x15 tlbi VAALE1 + tlbi RPAOS + tlbi RPALOS + tlbi PAALLOS, x25 + tlbi PAALL, x25 // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2E1IS // CHECK-ERROR-NEXT: ^ @@ -3557,6 +3561,18 @@ // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAALE1 // CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register +// CHECK-ERROR-NEXT: tlbi RPAOS +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register +// CHECK-ERROR-NEXT: tlbi RPALOS +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register +// CHECK-ERROR-NEXT: tlbi PAALLOS, x25 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register +// CHECK-ERROR-NEXT: tlbi PAALL, x25 +// CHECK-ERROR-NEXT: ^ // For the MSR/MRS instructions, first make sure read-only and // write-only registers actually are. diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -3653,6 +3653,10 @@ tlbi VALE3, x24 tlbi VMALLS12E1 tlbi VAALE1, x25 + tlbi RPAOS, x0 + tlbi RPALOS, x0 + tlbi PAALLOS + tlbi PAALL // CHECK: tlbi ipas2e1is, x4 // encoding: [0x24,0x80,0x0c,0xd5] // CHECK: tlbi ipas2le1is, x9 // encoding: [0xa9,0x80,0x0c,0xd5] // CHECK: tlbi vmalle1is // encoding: [0x1f,0x83,0x08,0xd5] @@ -3685,6 +3689,10 @@ // CHECK: tlbi vale3, x24 // encoding: [0xb8,0x87,0x0e,0xd5] // CHECK: tlbi vmalls12e1 // encoding: [0xdf,0x87,0x0c,0xd5] // CHECK: tlbi vaale1, x25 // encoding: [0xf9,0x87,0x08,0xd5] +// CHECK: tlbi rpaos, x0 // encoding: [0x60,0x84,0x0e,0xd5] +// CHECK: tlbi rpalos, x0 // encoding: [0xe0,0x84,0x0e,0xd5] +// CHECK: tlbi paallos // encoding: [0x9f,0x81,0x0e,0xd5] +// CHECK: tlbi paall // encoding: [0x9f,0x87,0x0e,0xd5] msr TEECR32_EL1, x12 msr OSDTRRX_EL1, x12 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple aarch64-arm-none-eabi -disassemble %s 2>&1 | FileCheck %s + +# CHECK: mrs x0, MFAR_EL3 +# CHECK: mrs x0, GPCCR_EL3 +# CHECK: mrs x0, GPTBR_EL3 +[0xa0,0x60,0x3e,0xd5] +[0xc0,0x21,0x3e,0xd5] +[0x80,0x21,0x3e,0xd5]