Index: llvm/docs/LangRef.rst =================================================================== --- llvm/docs/LangRef.rst +++ llvm/docs/LangRef.rst @@ -9611,9 +9611,9 @@ """""""""" Memory is allocated; a pointer is returned. The allocated memory is -uninitialized, and loading from uninitialized memory produces an undefined -value. The operation itself is undefined if there is insufficient stack -space for the allocation.'``alloca``'d memory is automatically released +uninitialized, and loading from uninitialized memory produces a :ref:`poison +value `. The operation itself is undefined if there is insufficient +stack space for the allocation.'``alloca``'d memory is automatically released when the function returns. The '``alloca``' instruction is commonly used to represent automatic variables that must have an address available. When the function returns (either with the ``ret`` or ``resume`` instructions), Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp =================================================================== --- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp +++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp @@ -490,8 +490,8 @@ less_first()); if (I == StoresByIndex.begin()) { if (StoresByIndex.empty()) - // If there are no stores, the load takes the undef value. - LI->replaceAllUsesWith(UndefValue::get(LI->getType())); + // If there are no stores, the load takes the poison value. + LI->replaceAllUsesWith(PoisonValue::get(LI->getType())); else // There is no store before this load, bail out (load may be affected // by the following stores - see main comment). @@ -640,12 +640,12 @@ LBI.clear(); - // Set the incoming values for the basic block to be null values for all of + // Set the incoming values for the basic block to be poison values for all of // the alloca's. We do this in case there is a load of a value that has not - // been stored yet. In this case, it will get this null value. + // been stored yet. In this case, it will get this poison value. RenamePassData::ValVector Values(Allocas.size()); for (unsigned i = 0, e = Allocas.size(); i != e; ++i) - Values[i] = UndefValue::get(Allocas[i]->getAllocatedType()); + Values[i] = PoisonValue::get(Allocas[i]->getAllocatedType()); // When handling debug info, treat all incoming values as if they have unknown // locations until proven otherwise. @@ -767,9 +767,9 @@ BasicBlock::iterator BBI = BB->begin(); while ((SomePHI = dyn_cast(BBI++)) && SomePHI->getNumIncomingValues() == NumBadPreds) { - Value *UndefVal = UndefValue::get(SomePHI->getType()); + Value *PoisonVal = PoisonValue::get(SomePHI->getType()); for (BasicBlock *Pred : Preds) - SomePHI->addIncoming(UndefVal, Pred); + SomePHI->addIncoming(PoisonVal, Pred); } } Index: llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll +++ llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll @@ -76,7 +76,7 @@ ; OPT-LABEL: @vector_write_read_bitcast_to_float( ; OPT-NOT: alloca ; OPT: bb2: -; OPT: %tmp.sroa.0.0 = phi <6 x float> [ undef, %bb ], [ %0, %bb2 ] +; OPT: %tmp.sroa.0.0 = phi <6 x float> [ poison, %bb ], [ %0, %bb2 ] ; OPT: %0 = insertelement <6 x float> %tmp.sroa.0.0, float %tmp73, i32 %tmp10 ; OPT: .preheader: ; OPT: %bc = bitcast <6 x float> %0 to <6 x i32> @@ -153,7 +153,7 @@ ; OPT-LABEL: @vector_write_read_bitcast_to_double( ; OPT-NOT: alloca ; OPT: bb2: -; OPT: %tmp.sroa.0.0 = phi <6 x double> [ undef, %bb ], [ %0, %bb2 ] +; OPT: %tmp.sroa.0.0 = phi <6 x double> [ poison, %bb ], [ %0, %bb2 ] ; OPT: %0 = insertelement <6 x double> %tmp.sroa.0.0, double %tmp73, i32 %tmp10 ; OPT: .preheader: ; OPT: %bc = bitcast <6 x double> %0 to <6 x i64> @@ -219,7 +219,7 @@ ; OPT-LABEL: @vector_write_read_bitcast_to_i64( ; OPT-NOT: alloca ; OPT: bb2: -; OPT: %tmp.sroa.0.0 = phi <6 x i64> [ undef, %bb ], [ %0, %bb2 ] +; OPT: %tmp.sroa.0.0 = phi <6 x i64> [ poison, %bb ], [ %0, %bb2 ] ; OPT: %0 = insertelement <6 x i64> %tmp.sroa.0.0, i64 %tmp6, i32 %tmp9 ; OPT: .preheader: ; OPT: %1 = extractelement <6 x i64> %0, i32 %tmp18 Index: llvm/test/Transforms/Mem2Reg/debug-alloca-vla-1.ll =================================================================== --- llvm/test/Transforms/Mem2Reg/debug-alloca-vla-1.ll +++ llvm/test/Transforms/Mem2Reg/debug-alloca-vla-1.ll @@ -19,7 +19,7 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG10:![0-9]+]] ; CHECK: for.cond: -; CHECK-NEXT: [[VLA1_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ] +; CHECK-NEXT: [[VLA1_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ] ; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[VLA1_0]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] ; CHECK-NEXT: [[T0]] = add i32 [[VLA1_0]], 1 ; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[T0]], metadata [[META11]], metadata !DIExpression()), !dbg [[DBG19]] Index: llvm/test/Transforms/Mem2Reg/debug-alloca-vla-2.ll =================================================================== --- llvm/test/Transforms/Mem2Reg/debug-alloca-vla-2.ll +++ llvm/test/Transforms/Mem2Reg/debug-alloca-vla-2.ll @@ -22,7 +22,7 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG10:![0-9]+]] ; CHECK: for.cond: -; CHECK-NEXT: [[VLA1_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ] +; CHECK-NEXT: [[VLA1_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[T0:%.*]], [[FOR_COND]] ] ; CHECK-NEXT: [[T0]] = add i32 [[VLA1_0]], 1 ; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 undef, metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] ; CHECK-NEXT: br label [[FOR_COND]], !dbg [[DBG10]] Index: llvm/test/Transforms/Mem2Reg/pr24179.ll =================================================================== --- llvm/test/Transforms/Mem2Reg/pr24179.ll +++ llvm/test/Transforms/Mem2Reg/pr24179.ll @@ -13,7 +13,7 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[T_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[N:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[T_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[N:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[C:%.*]] = call i1 @use(i32 [[T_0]]) ; CHECK-NEXT: [[N]] = call i32 @def(i32 7) ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] @@ -42,7 +42,7 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[C:%.*]] = call i1 @use(i32 undef) +; CHECK-NEXT: [[C:%.*]] = call i1 @use(i32 poison) ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] ; CHECK: exit: ; CHECK-NEXT: ret void Index: llvm/test/Transforms/Mem2Reg/undef-order.ll =================================================================== --- llvm/test/Transforms/Mem2Reg/undef-order.ll +++ llvm/test/Transforms/Mem2Reg/undef-order.ll @@ -45,7 +45,7 @@ ; CHECK: Block16: ; CHECK-NEXT: br label [[JOIN]] ; CHECK: Join: -; CHECK-NEXT: [[VAL_0:%.*]] = phi i32 [ 1, [[STORE1]] ], [ 2, [[STORE2]] ], [ undef, [[BLOCK1:%.*]] ], [ undef, [[BLOCK2:%.*]] ], [ undef, [[BLOCK3:%.*]] ], [ undef, [[BLOCK4:%.*]] ], [ undef, [[BLOCK5:%.*]] ], [ undef, [[BLOCK6:%.*]] ], [ undef, [[BLOCK7:%.*]] ], [ undef, [[BLOCK8:%.*]] ], [ undef, [[BLOCK9:%.*]] ], [ undef, [[BLOCK10:%.*]] ], [ undef, [[BLOCK11:%.*]] ], [ undef, [[BLOCK12:%.*]] ], [ undef, [[BLOCK13:%.*]] ], [ undef, [[BLOCK14:%.*]] ], [ undef, [[BLOCK15:%.*]] ], [ undef, [[BLOCK16:%.*]] ] +; CHECK-NEXT: [[VAL_0:%.*]] = phi i32 [ 1, [[STORE1]] ], [ 2, [[STORE2]] ], [ poison, [[BLOCK1:%.*]] ], [ poison, [[BLOCK2:%.*]] ], [ poison, [[BLOCK3:%.*]] ], [ poison, [[BLOCK4:%.*]] ], [ poison, [[BLOCK5:%.*]] ], [ poison, [[BLOCK6:%.*]] ], [ poison, [[BLOCK7:%.*]] ], [ poison, [[BLOCK8:%.*]] ], [ poison, [[BLOCK9:%.*]] ], [ poison, [[BLOCK10:%.*]] ], [ poison, [[BLOCK11:%.*]] ], [ poison, [[BLOCK12:%.*]] ], [ poison, [[BLOCK13:%.*]] ], [ poison, [[BLOCK14:%.*]] ], [ poison, [[BLOCK15:%.*]] ], [ poison, [[BLOCK16:%.*]] ] ; CHECK-NEXT: ret i32 [[VAL_0]] ; Entry: Index: llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll =================================================================== --- llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll +++ llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll @@ -42,7 +42,7 @@ ; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4 ; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4 ; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4 -; CHECK-NEXT: ret i32 undef +; CHECK-NEXT: ret i32 poison ; entry: %retval = alloca i32, align 4 Index: llvm/test/Transforms/SROA/addrspacecast.ll =================================================================== --- llvm/test/Transforms/SROA/addrspacecast.ll +++ llvm/test/Transforms/SROA/addrspacecast.ll @@ -172,11 +172,11 @@ define i64 @alloca_addrspacecast_bitcast_volatile_store(i64 %X) { ; CHECK-LABEL: @alloca_addrspacecast_bitcast_volatile_store( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A:%.*]] = alloca [8 x i8] +; CHECK-NEXT: [[A:%.*]] = alloca [8 x i8], align 1 ; CHECK-NEXT: [[A_CAST:%.*]] = addrspacecast [8 x i8]* [[A]] to [8 x i8] addrspace(1)* ; CHECK-NEXT: [[B:%.*]] = bitcast [8 x i8] addrspace(1)* [[A_CAST]] to i64 addrspace(1)* -; CHECK-NEXT: store volatile i64 [[X:%.*]], i64 addrspace(1)* [[B]] -; CHECK-NEXT: [[Z:%.*]] = load i64, i64 addrspace(1)* [[B]] +; CHECK-NEXT: store volatile i64 [[X:%.*]], i64 addrspace(1)* [[B]], align 4 +; CHECK-NEXT: [[Z:%.*]] = load i64, i64 addrspace(1)* [[B]], align 4 ; CHECK-NEXT: ret i64 [[Z]] ; entry: @@ -192,11 +192,11 @@ define i64 @alloca_addrspacecast_bitcast_volatile_load(i64 %X) { ; CHECK-LABEL: @alloca_addrspacecast_bitcast_volatile_load( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A:%.*]] = alloca [8 x i8] +; CHECK-NEXT: [[A:%.*]] = alloca [8 x i8], align 1 ; CHECK-NEXT: [[A_CAST:%.*]] = addrspacecast [8 x i8]* [[A]] to [8 x i8] addrspace(1)* ; CHECK-NEXT: [[B:%.*]] = bitcast [8 x i8] addrspace(1)* [[A_CAST]] to i64 addrspace(1)* -; CHECK-NEXT: store i64 [[X:%.*]], i64 addrspace(1)* [[B]] -; CHECK-NEXT: [[Z:%.*]] = load volatile i64, i64 addrspace(1)* [[B]] +; CHECK-NEXT: store i64 [[X:%.*]], i64 addrspace(1)* [[B]], align 4 +; CHECK-NEXT: [[Z:%.*]] = load volatile i64, i64 addrspace(1)* [[B]], align 4 ; CHECK-NEXT: ret i64 [[Z]] ; entry: @@ -214,12 +214,12 @@ define i32 @volatile_memset() { ; CHECK-LABEL: @volatile_memset( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A:%.*]] = alloca [4 x i8] +; CHECK-NEXT: [[A:%.*]] = alloca [4 x i8], align 1 ; CHECK-NEXT: [[PTR:%.*]] = getelementptr [4 x i8], [4 x i8]* [[A]], i32 0, i32 0 ; CHECK-NEXT: [[ASC:%.*]] = addrspacecast i8* [[PTR]] to i8 addrspace(1)* ; CHECK-NEXT: call void @llvm.memset.p1i8.i32(i8 addrspace(1)* [[ASC]], i8 42, i32 4, i1 true) ; CHECK-NEXT: [[IPTR:%.*]] = bitcast i8* [[PTR]] to i32* -; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[IPTR]] +; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[IPTR]], align 4 ; CHECK-NEXT: ret i32 [[VAL]] ; entry: @@ -236,11 +236,11 @@ define void @volatile_memcpy(i8* %src, i8* %dst) { ; CHECK-LABEL: @volatile_memcpy( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A:%.*]] = alloca [4 x i8] +; CHECK-NEXT: [[A:%.*]] = alloca [4 x i8], align 1 ; CHECK-NEXT: [[PTR:%.*]] = getelementptr [4 x i8], [4 x i8]* [[A]], i32 0, i32 0 ; CHECK-NEXT: [[ASC:%.*]] = addrspacecast i8* [[PTR]] to i8 addrspace(1)* -; CHECK-NEXT: call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* [[ASC]], i8* [[SRC:%.*]], i32 4, i1 true), !tbaa !0 -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p1i8.i32(i8* [[DST:%.*]], i8 addrspace(1)* [[ASC]], i32 4, i1 true), !tbaa !3 +; CHECK-NEXT: call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* [[ASC]], i8* [[SRC:%.*]], i32 4, i1 true), !tbaa [[TBAA0:![0-9]+]] +; CHECK-NEXT: call void @llvm.memcpy.p0i8.p1i8.i32(i8* [[DST:%.*]], i8 addrspace(1)* [[ASC]], i32 4, i1 true), !tbaa [[TBAA3:![0-9]+]] ; CHECK-NEXT: ret void ; entry: @@ -289,7 +289,7 @@ define void @select_addrspacecast_gv(i1 %a, i1 %b) { ; CHECK-LABEL: @select_addrspacecast_gv( ; CHECK-NEXT: [[COND_SROA_SPECULATE_LOAD_FALSE:%.*]] = load i64, i64 addrspace(1)* @gv, align 8 -; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 [[COND_SROA_SPECULATE_LOAD_FALSE]] +; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 poison, i64 [[COND_SROA_SPECULATE_LOAD_FALSE]] ; CHECK-NEXT: ret void ; %c = alloca i64, align 8 @@ -303,7 +303,7 @@ define i8 @select_addrspacecast_i8() { ; CHECK-LABEL: @select_addrspacecast_i8( -; CHECK-NEXT: [[RET_SROA_SPECULATED:%.*]] = select i1 undef, i8 undef, i8 undef +; CHECK-NEXT: [[RET_SROA_SPECULATED:%.*]] = select i1 undef, i8 poison, i8 poison ; CHECK-NEXT: ret i8 [[RET_SROA_SPECULATED]] ; %a = alloca i8 Index: llvm/test/Transforms/SROA/basictest.ll =================================================================== --- llvm/test/Transforms/SROA/basictest.ll +++ llvm/test/Transforms/SROA/basictest.ll @@ -1251,7 +1251,7 @@ ; via integers can be promoted away. ; CHECK-LABEL: @PR14059.1( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast double undef to i64 +; CHECK-NEXT: [[TMP0:%.*]] = bitcast double poison to i64 ; CHECK-NEXT: [[X_SROA_0_I_0_INSERT_MASK:%.*]] = and i64 [[TMP0]], -4294967296 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[X_SROA_0_I_0_INSERT_MASK]] to double ; CHECK-NEXT: [[TMP2:%.*]] = bitcast double [[TMP1]] to i64 @@ -1481,7 +1481,7 @@ ; CHECK-LABEL: @PR14572.2( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast <3 x i8> [[X:%.*]] to i24 -; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i8 undef to i32 +; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i8 poison to i32 ; CHECK-NEXT: [[A_SROA_2_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_2_0_INSERT_EXT]], 24 ; CHECK-NEXT: [[A_SROA_2_0_INSERT_MASK:%.*]] = and i32 undef, 16777215 ; CHECK-NEXT: [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_SHIFT]] @@ -1619,7 +1619,7 @@ define void @PR15805(i1 %a, i1 %b) { ; CHECK-LABEL: @PR15805( -; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 undef +; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 poison, i64 poison ; CHECK-NEXT: ret void ; @@ -1638,7 +1638,7 @@ ; CHECK-LABEL: @PR15805.1( ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 undef +; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 poison, i64 poison ; CHECK-NEXT: br i1 undef, label [[LOOP:%.*]], label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: ret void @@ -1882,7 +1882,7 @@ ; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i16, align 4 ; CHECK-NEXT: store volatile i16 42, i16* [[A_SROA_0]], align 4 ; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_LOAD:%.*]] = load i16, i16* [[A_SROA_0]], align 4 -; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 undef to i32 +; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 poison to i32 ; CHECK-NEXT: [[A_SROA_3_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_3_0_INSERT_EXT]], 16 ; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i32 undef, 65535 ; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_SHIFT]] @@ -1920,7 +1920,7 @@ ; CHECK-NEXT: [[A_SROA_31:%.*]] = alloca i8, align 4 ; CHECK-NEXT: store volatile i16 42, i16* [[A_SROA_0]], align 8 ; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_LOAD:%.*]] = load i16, i16* [[A_SROA_0]], align 8 -; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 undef to i32 +; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i16 poison to i32 ; CHECK-NEXT: [[A_SROA_3_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_3_0_INSERT_EXT]], 16 ; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i32 undef, 65535 ; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_SHIFT]] @@ -2136,7 +2136,7 @@ ; CHECK: bb3: ; CHECK-NEXT: br label [[BB5]] ; CHECK: bb4: -; CHECK-NEXT: store i32 undef, i32* [[TMP0]], align 4 +; CHECK-NEXT: store i32 poison, i32* [[TMP0]], align 4 ; CHECK-NEXT: br label [[BB5]] ; CHECK: bb5: ; CHECK-NEXT: [[SUB]] = add i32 [[I_02]], -1 Index: llvm/test/Transforms/SROA/phi-and-select.ll =================================================================== --- llvm/test/Transforms/SROA/phi-and-select.ll +++ llvm/test/Transforms/SROA/phi-and-select.ll @@ -321,7 +321,7 @@ ; CHECK: else: ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: -; CHECK-NEXT: [[PHI_SROA_SPECULATED:%.*]] = phi i32 [ undef, [[ELSE]] ], [ [[PHI_SROA_SPECULATE_LOAD_THEN]], [[THEN]] ] +; CHECK-NEXT: [[PHI_SROA_SPECULATED:%.*]] = phi i32 [ poison, [[ELSE]] ], [ [[PHI_SROA_SPECULATE_LOAD_THEN]], [[THEN]] ] ; CHECK-NEXT: ret i32 [[PHI_SROA_SPECULATED]] ; @@ -350,7 +350,7 @@ ; CHECK-NEXT: store i32 0, i32* [[PTR:%.*]], align 4 ; CHECK-NEXT: [[TEST:%.*]] = icmp ne i32 [[B:%.*]], 0 ; CHECK-NEXT: [[LOADED_SROA_SPECULATE_LOAD_FALSE:%.*]] = load i32, i32* [[PTR]], align 4 -; CHECK-NEXT: [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], i32 undef, i32 [[LOADED_SROA_SPECULATE_LOAD_FALSE]] +; CHECK-NEXT: [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], i32 poison, i32 [[LOADED_SROA_SPECULATE_LOAD_FALSE]] ; CHECK-NEXT: ret i32 [[LOADED_SROA_SPECULATED]] ; Index: llvm/test/Transforms/SROA/phi-gep.ll =================================================================== --- llvm/test/Transforms/SROA/phi-gep.ll +++ llvm/test/Transforms/SROA/phi-gep.ll @@ -493,7 +493,7 @@ ; CHECK: bb.3: ; CHECK-NEXT: br label [[BB_4]] ; CHECK: bb.4: -; CHECK-NEXT: [[PHI_SROA_PHI_SROA_SPECULATED:%.*]] = phi i32 [ undef, [[BB_3]] ], [ undef, [[BB_2]] ], [ undef, [[BB_1:%.*]] ], [ undef, [[BB_1]] ] +; CHECK-NEXT: [[PHI_SROA_PHI_SROA_SPECULATED:%.*]] = phi i32 [ poison, [[BB_3]] ], [ poison, [[BB_2]] ], [ poison, [[BB_1:%.*]] ], [ poison, [[BB_1]] ] ; CHECK-NEXT: ret i32 [[PHI_SROA_PHI_SROA_SPECULATED]] ; bb.1: Index: llvm/test/Transforms/SROA/phi-with-duplicate-pred.ll =================================================================== --- llvm/test/Transforms/SROA/phi-with-duplicate-pred.ll +++ llvm/test/Transforms/SROA/phi-with-duplicate-pred.ll @@ -21,7 +21,7 @@ ; CHECK: if.else: ; CHECK-NEXT: br label [[LBL1]] ; CHECK: lbl1: -; CHECK-NEXT: [[G_0_SROA_SPECULATED:%.*]] = phi i16 [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ undef, [[IF_ELSE]] ] +; CHECK-NEXT: [[G_0_SROA_SPECULATED:%.*]] = phi i16 [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ poison, [[IF_ELSE]] ] ; CHECK-NEXT: unreachable ; CHECK: cleanup7: ; CHECK-NEXT: ret void Index: llvm/test/Transforms/SROA/pr37267.ll =================================================================== --- llvm/test/Transforms/SROA/pr37267.ll +++ llvm/test/Transforms/SROA/pr37267.ll @@ -45,14 +45,14 @@ define i16 @f2() { ; CHECK-LABEL: @f2( ; CHECK-NEXT: bb1: -; CHECK-NEXT: [[A_3_SROA_2_2_INSERT_EXT:%.*]] = zext i16 undef to i32 +; CHECK-NEXT: [[A_3_SROA_2_2_INSERT_EXT:%.*]] = zext i16 poison to i32 ; CHECK-NEXT: [[A_3_SROA_2_2_INSERT_MASK:%.*]] = and i32 undef, -65536 ; CHECK-NEXT: [[A_3_SROA_2_2_INSERT_INSERT:%.*]] = or i32 [[A_3_SROA_2_2_INSERT_MASK]], [[A_3_SROA_2_2_INSERT_EXT]] -; CHECK-NEXT: [[A_3_SROA_0_2_INSERT_EXT:%.*]] = zext i16 undef to i32 +; CHECK-NEXT: [[A_3_SROA_0_2_INSERT_EXT:%.*]] = zext i16 poison to i32 ; CHECK-NEXT: [[A_3_SROA_0_2_INSERT_SHIFT:%.*]] = shl i32 [[A_3_SROA_0_2_INSERT_EXT]], 16 ; CHECK-NEXT: [[A_3_SROA_0_2_INSERT_MASK:%.*]] = and i32 [[A_3_SROA_2_2_INSERT_INSERT]], 65535 ; CHECK-NEXT: [[A_3_SROA_0_2_INSERT_INSERT:%.*]] = or i32 [[A_3_SROA_0_2_INSERT_MASK]], [[A_3_SROA_0_2_INSERT_SHIFT]] -; CHECK-NEXT: [[RC:%.*]] = add i16 2, undef +; CHECK-NEXT: [[RC:%.*]] = add i16 2, poison ; CHECK-NEXT: ret i16 [[RC]] ; Index: llvm/test/Transforms/SROA/scalable-vectors.ll =================================================================== --- llvm/test/Transforms/SROA/scalable-vectors.ll +++ llvm/test/Transforms/SROA/scalable-vectors.ll @@ -73,7 +73,7 @@ ; CHECK-NEXT: [[RETVAL_COERCE:%.*]] = alloca , align 16 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast * [[RETVAL_COERCE]] to i8* ; CHECK-NEXT: [[RETVAL_0__SROA_CAST:%.*]] = bitcast i8* [[TMP1]] to <16 x i32>* -; CHECK-NEXT: store <16 x i32> undef, <16 x i32>* [[RETVAL_0__SROA_CAST]], align 16 +; CHECK-NEXT: store <16 x i32> poison, <16 x i32>* [[RETVAL_0__SROA_CAST]], align 16 ; CHECK-NEXT: [[TMP2:%.*]] = load , * [[RETVAL_COERCE]], align 16 ; CHECK-NEXT: ret [[TMP2]] ; Index: llvm/test/Transforms/SROA/slice-width.ll =================================================================== --- llvm/test/Transforms/SROA/slice-width.ll +++ llvm/test/Transforms/SROA/slice-width.ll @@ -102,7 +102,7 @@ ; CHECK-NEXT: [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST_SROA_CAST:%.*]] = bitcast %S.vec3float* [[X:%.*]] to <3 x float>* ; CHECK-NEXT: [[TMP1_SROA_0_0_COPYLOAD:%.*]] = load <3 x float>, <3 x float>* [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST_SROA_CAST]], align 4 ; CHECK-NEXT: [[TMP1_SROA_0_0_VEC_EXPAND:%.*]] = shufflevector <3 x float> [[TMP1_SROA_0_0_COPYLOAD]], <3 x float> poison, <4 x i32> -; CHECK-NEXT: [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> , <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> undef +; CHECK-NEXT: [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> , <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> poison ; CHECK-NEXT: [[TMP2:%.*]] = alloca [[S_VEC3FLOAT:%.*]], align 4 ; CHECK-NEXT: [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST2_SROA_CAST:%.*]] = bitcast %S.vec3float* [[TMP2]] to <3 x float>* ; CHECK-NEXT: [[TMP1_SROA_0_0_VEC_EXTRACT:%.*]] = shufflevector <4 x float> [[TMP1_SROA_0_0_VECBLEND]], <4 x float> poison, <3 x i32> Index: llvm/test/Transforms/SROA/vector-promotion.ll =================================================================== --- llvm/test/Transforms/SROA/vector-promotion.ll +++ llvm/test/Transforms/SROA/vector-promotion.ll @@ -262,7 +262,7 @@ define <4 x i32> @test_subvec_store() { ; CHECK-LABEL: @test_subvec_store( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = select <4 x i1> , <4 x i32> , <4 x i32> undef +; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = select <4 x i1> , <4 x i32> , <4 x i32> poison ; CHECK-NEXT: [[A_4_VECBLEND:%.*]] = select <4 x i1> , <4 x i32> , <4 x i32> [[A_0_VECBLEND]] ; CHECK-NEXT: [[A_8_VECBLEND:%.*]] = select <4 x i1> , <4 x i32> , <4 x i32> [[A_4_VECBLEND]] ; CHECK-NEXT: [[A_12_VEC_INSERT:%.*]] = insertelement <4 x i32> [[A_8_VECBLEND]], i32 3, i32 3 @@ -328,7 +328,7 @@ define <4 x float> @test_subvec_memset() { ; CHECK-LABEL: @test_subvec_memset( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = select <4 x i1> , <4 x float> , <4 x float> undef +; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = select <4 x i1> , <4 x float> , <4 x float> poison ; CHECK-NEXT: [[A_4_VECBLEND:%.*]] = select <4 x i1> , <4 x float> , <4 x float> [[A_0_VECBLEND]] ; CHECK-NEXT: [[A_8_VECBLEND:%.*]] = select <4 x i1> , <4 x float> , <4 x float> [[A_4_VECBLEND]] ; CHECK-NEXT: [[A_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[A_8_VECBLEND]], float 0x38E0E0E0E0000000, i32 3 @@ -364,7 +364,7 @@ ; CHECK-NEXT: [[A_0_X_SROA_CAST:%.*]] = bitcast i8* [[X:%.*]] to <2 x float>* ; CHECK-NEXT: [[A_0_COPYLOAD:%.*]] = load <2 x float>, <2 x float>* [[A_0_X_SROA_CAST]], align 1 ; CHECK-NEXT: [[A_0_VEC_EXPAND:%.*]] = shufflevector <2 x float> [[A_0_COPYLOAD]], <2 x float> poison, <4 x i32> -; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = select <4 x i1> , <4 x float> [[A_0_VEC_EXPAND]], <4 x float> undef +; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = select <4 x i1> , <4 x float> [[A_0_VEC_EXPAND]], <4 x float> poison ; CHECK-NEXT: [[A_4_Y_SROA_CAST:%.*]] = bitcast i8* [[Y:%.*]] to <2 x float>* ; CHECK-NEXT: [[A_4_COPYLOAD:%.*]] = load <2 x float>, <2 x float>* [[A_4_Y_SROA_CAST]], align 1 ; CHECK-NEXT: [[A_4_VEC_EXPAND:%.*]] = shufflevector <2 x float> [[A_4_COPYLOAD]], <2 x float> poison, <4 x i32> @@ -411,7 +411,7 @@ ; CHECK-LABEL: @PR14212( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast <3 x i8> undef to i24 -; CHECK-NEXT: [[RETVAL_SROA_2_0_INSERT_EXT:%.*]] = zext i8 undef to i32 +; CHECK-NEXT: [[RETVAL_SROA_2_0_INSERT_EXT:%.*]] = zext i8 poison to i32 ; CHECK-NEXT: [[RETVAL_SROA_2_0_INSERT_SHIFT:%.*]] = shl i32 [[RETVAL_SROA_2_0_INSERT_EXT]], 24 ; CHECK-NEXT: [[RETVAL_SROA_2_0_INSERT_MASK:%.*]] = and i32 undef, 16777215 ; CHECK-NEXT: [[RETVAL_SROA_2_0_INSERT_INSERT:%.*]] = or i32 [[RETVAL_SROA_2_0_INSERT_MASK]], [[RETVAL_SROA_2_0_INSERT_SHIFT]] @@ -458,7 +458,7 @@ ; CHECK-LABEL: @PR14349.2( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i8> [[X:%.*]] to i16 -; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i16 undef to i32 +; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i16 poison to i32 ; CHECK-NEXT: [[A_SROA_2_0_INSERT_SHIFT:%.*]] = shl i32 [[A_SROA_2_0_INSERT_EXT]], 16 ; CHECK-NEXT: [[A_SROA_2_0_INSERT_MASK:%.*]] = and i32 undef, 65535 ; CHECK-NEXT: [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_SHIFT]] @@ -543,7 +543,7 @@ ; on a single load with a vector type. ; CHECK-LABEL: @test9( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[A_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i32 0 +; CHECK-NEXT: [[A_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0 ; CHECK-NEXT: [[A_SROA_0_4_VEC_INSERT:%.*]] = insertelement <2 x i32> [[A_SROA_0_0_VEC_INSERT]], i32 [[Y:%.*]], i32 1 ; CHECK-NEXT: ret <2 x i32> [[A_SROA_0_4_VEC_INSERT]] ;