Index: llvm/lib/Target/M68k/GlSel/M68kCallLowering.h
===================================================================
--- llvm/lib/Target/M68k/GlSel/M68kCallLowering.h
+++ llvm/lib/Target/M68k/GlSel/M68kCallLowering.h
@@ -43,6 +43,32 @@
 
   bool enableBigEndian() const override;
 };
+struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
+
+  M68kIncomingValueHandler(MachineIRBuilder &MIRBuilder,
+                           MachineRegisterInfo &MRI)
+      : CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}
+
+  uint64_t StackUsed;
+
+private:
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+                        CCValAssign &VA) override;
+
+  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
+                            MachinePointerInfo &MPO, CCValAssign &VA) override;
+
+  Register getStackAddress(uint64_t Size, int64_t Offset,
+                           MachinePointerInfo &MPO,
+                           ISD::ArgFlagsTy Flags) override;
+};
+
+struct FormalArgHandler : public M68kIncomingValueHandler {
+
+public:
+  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
+      : M68kIncomingValueHandler(MIRBuilder, MRI) {}
+};
 
 } // end namespace llvm
 
Index: llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp
===================================================================
--- llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp
+++ llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp
@@ -15,12 +15,17 @@
 #include "M68kCallLowering.h"
 #include "M68kISelLowering.h"
 #include "M68kInstrInfo.h"
+#include "M68kSubtarget.h"
+#include "M68kTargetMachine.h"
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
+
 using namespace llvm;
 
 M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
     : CallLowering(&TLI) {}
-
 bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                    const Value *Val, ArrayRef<Register> VRegs,
                                    FunctionLoweringInfo &FLI,
@@ -36,11 +41,50 @@
                                             const Function &F,
                                             ArrayRef<ArrayRef<Register>> VRegs,
                                             FunctionLoweringInfo &FLI) const {
+  MachineFunction &MF = MIRBuilder.getMF();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  const auto &DL = F.getParent()->getDataLayout();
+  auto &TLI = *getTLI<M68kTargetLowering>();
 
-  if (F.arg_empty())
-    return true;
+  SmallVector<ArgInfo, 8> SplitArgs;
+  unsigned I = 0;
+  for (const auto &Arg : F.args()) {
+    ArgInfo OrigArg{VRegs[I], Arg.getType()};
+    setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
+    SplitArgs.push_back(OrigArg);
+    ++I;
+  }
 
-  return false;
+  CCAssignFn *AssignFn =
+      TLI.getCCAssignGnForCall(F.getCallingConv(), false, F.isVarArg());
+  IncomingValueAssigner ArgAssigner(AssignFn);
+  FormalArgHandler ArgHandler(MIRBuilder, MRI);
+  return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
+                                       MIRBuilder, F.getCallingConv(),
+                                       F.isVarArg());
+}
+
+void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
+                                                Register PhysReg,
+                                                CCValAssign &VA) {
+  MIRBuilder.getMRI()->addLiveIn(PhysReg);
+  MIRBuilder.getMBB().addLiveIn(PhysReg);
+  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
+}
+
+void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
+                                                    Register Addr,
+                                                    uint64_t Size,
+                                                    MachinePointerInfo &MPO,
+                                                    CCValAssign &VA) {
+  llvm_unreachable("unimeplemented");
+}
+
+Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
+                                                   int64_t Offset,
+                                                   MachinePointerInfo &MPO,
+                                                   ISD::ArgFlagsTy Flags) {
+  llvm_unreachable("unimeplemented");
 }
 
 bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
Index: llvm/lib/Target/M68k/M68kISelLowering.h
===================================================================
--- llvm/lib/Target/M68k/M68kISelLowering.h
+++ llvm/lib/Target/M68k/M68kISelLowering.h
@@ -171,6 +171,9 @@
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *MBB) const override;
 
+  CCAssignFn *getCCAssignGnForCall(CallingConv::ID CC, bool Return,
+                                   bool IsVarArg) const;
+
 private:
   unsigned GetAlignedArgumentStackSize(unsigned StackSize,
                                        SelectionDAG &DAG) const;
Index: llvm/lib/Target/M68k/M68kISelLowering.cpp
===================================================================
--- llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -3412,3 +3412,9 @@
     return NULL;
   }
 }
+
+CCAssignFn *M68kTargetLowering::getCCAssignGnForCall(CallingConv::ID CC,
+                                                     bool Return,
+                                                     bool IsVarArg) const {
+  return CC_M68k_C;
+}
Index: llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
===================================================================
--- llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
+++ llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
@@ -5,3 +5,40 @@
 define void @noArgRetVoid() {
   ret void
 }
+
+define void @test_arg_lowering1(i8 %x, i8 %y) {
+  ; CHECK-LABEL: name: test_arg_lowering1
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD:%[0-9]+]]:_(s32) = G_LOAD [[G_FRAME_INDEX]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD]](s32)
+  ; CHECK:   [[G_FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD:%[0-9]+]]:_(s32) = G_LOAD [[G_FRAME_INDEX]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering2(i16 %x, i16 %y) {
+  ; CHECK-LABEL: name: test_arg_lowering2
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD:%[0-9]+]]:_(s32) = G_LOAD [[G_FRAME_INDEX]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD]](s32)
+  ; CHECK:   [[G_FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD:%[0-9]+]]:_(s32) = G_LOAD [[G_FRAME_INDEX]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering3(i32 %x, i32 %y) {
+  ; CHECK-LABEL: name: test_arg_lowering3
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   {{%.*}} G_LOAD [[G_FRAME_INDEX]](p0)
+  ; CHECK:   [[G_FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   {{%.*}} G_LOAD [[G_FRAME_INDEX]](p0)
+  ; CHECK:   RTS
+  ret void
+}