[GlobalISel] NFC: Change LLT::changeNumElements to LLT::changeElementCount.

[aemerson]

LGTM.

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

if (CastOpc == TargetOpcode::G_TRUNC) {
         //  %6:_(s32), %7:_(s32), %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %0
         //  %2:_(s8) = G_TRUNC %6
         //  %3:_(s8) = G_TRUNC %7
         //  %4:_(s8) = G_TRUNC %8
         //  %5:_(s8) = G_TRUNC %9
 
         unsigned UnmergeNumElts =
             DestTy.isVector() ? CastSrcTy.getNumElements() / NumDefs : 1;
-        LLT UnmergeTy = CastSrcTy.changeNumElements(UnmergeNumElts);
+        LLT UnmergeTy = CastSrcTy.changeElementCount(
+            ElementCount::getFixed(UnmergeNumElts));
 
         if (isInstUnsupported(
                 {TargetOpcode::G_UNMERGE_VALUES, {UnmergeTy, CastSrcTy}}))
           return false;
 
         Builder.setInstr(MI);
         auto NewUnmerge = Builder.buildUnmerge(UnmergeTy, CastSrcReg);
 

llvm/include/llvm/Support/LowLevelTypeImpl.h

public:
   /// for pointer types. For pointer types, use changeElementType.
   LLT changeElementSize(unsigned NewEltSize) const {
     assert(!getScalarType().isPointer() &&
            "invalid to directly change element size for pointers");
     return isVector() ? LLT::vector(getElementCount(), NewEltSize)
                       : LLT::scalar(NewEltSize);
   }
 
-  /// Return a vector or scalar with the same element type and the new number of
-  /// elements.
-  LLT changeNumElements(unsigned NewNumElts) const {
-    assert((!isVector() || !isScalable()) &&
-           "Cannot use changeNumElements on a scalable vector");
-    return LLT::scalarOrVector(ElementCount::getFixed(NewNumElts),
-                               getScalarType());
+  /// Return a vector or scalar with the same element type and the new element
+  /// count.
+  LLT changeElementCount(ElementCount EC) const {
+    return LLT::scalarOrVector(EC, getScalarType());
   }
 
   /// Return a type that is \p Factor times smaller. Reduces the number of
   /// elements if this is a vector, or the bitwidth for scalar/pointers. Does
   /// not attempt to handle cases that aren't evenly divisible.
   LLT divide(int Factor) const {
     assert(Factor != 1);
     if (isVector()) {
-      assert(getNumElements() % Factor == 0);
+      assert(getElementCount().isKnownMultipleOf(Factor));
       return scalarOrVector(getElementCount().divideCoefficientBy(Factor),
                             getElementType());
     }
 
     assert(getSizeInBits() % Factor == 0);
     return scalar(getSizeInBits() / Factor);
   }
 

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

if (PartLLT.isVector()) {
 
     // If PartLLT is a mismatched vector in both number of elements and element
     // size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
     // have the same elt type, i.e. v4s32.
     if (PartLLT.getSizeInBits() > LLTy.getSizeInBits() &&
         PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
         Regs.size() == 1) {
       LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
-                      .changeNumElements(PartLLT.getNumElements() * 2);
+                      .changeElementCount(PartLLT.getElementCount() * 2);
       CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);
       PartLLT = NewTy;
     }
 
     if (LLTy.getScalarType() == PartLLT.getElementType()) {
       mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
     } else {
       unsigned I = 0;

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle(
   if (DstTy != Src2Ty)
     return UnableToLegalize;
 
   if (!isPowerOf2_32(DstTy.getNumElements()))
     return UnableToLegalize;
 
   // We only support splitting a shuffle into 2, so adjust NarrowTy accordingly.
   // Further legalization attempts will be needed to do split further.
-  NarrowTy = DstTy.changeNumElements(DstTy.getNumElements() / 2);
+  NarrowTy =
+      DstTy.changeElementCount(DstTy.getElementCount().divideCoefficientBy(2));
   unsigned NewElts = NarrowTy.getNumElements();
 
   SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs;
   extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs);
   extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs);
   Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0],
                         SplitSrc2Regs[1]};
 

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

bool AArch64LegalizerInfo::legalizeVectorTrunc(
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
   LLT DstTy = MRI.getType(DstReg);
   LLT SrcTy = MRI.getType(SrcReg);
   assert(isPowerOf2_32(DstTy.getSizeInBits()) &&
          isPowerOf2_32(SrcTy.getSizeInBits()));
 
   // Split input type.
-  LLT SplitSrcTy = SrcTy.changeNumElements(SrcTy.getNumElements() / 2);
+  LLT SplitSrcTy =
+      SrcTy.changeElementCount(SrcTy.getElementCount().divideCoefficientBy(2));
   // First, split the source into two smaller vectors.
   SmallVector<Register, 2> SplitSrcs;
   extractParts(SrcReg, MRI, MIRBuilder, SplitSrcTy, 2, SplitSrcs);
 
   // Truncate the splits into intermediate narrower elements.
   LLT InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits() * 2);
   for (unsigned I = 0; I < SplitSrcs.size(); ++I)
     SplitSrcs[I] = MIRBuilder.buildTrunc(InterTy, SplitSrcs[I]).getReg(0);

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

bool applyDupLane(MachineInstr &MI, MachineRegisterInfo &MRI,
 
   Register DupSrc = MI.getOperand(1).getReg();
   // For types like <2 x s32>, we can use G_DUPLANE32, with a <4 x s32> source.
   // To do this, we can use a G_CONCAT_VECTORS to do the widening.
   if (SrcTy == LLT::fixed_vector(2, LLT::scalar(32))) {
     assert(MRI.getType(MI.getOperand(0).getReg()).getNumElements() == 2 &&
            "Unexpected dest elements");
     auto Undef = B.buildUndef(SrcTy);
-    DupSrc = B.buildConcatVectors(SrcTy.changeNumElements(4),
-                                  {Src1Reg, Undef.getReg(0)})
+    DupSrc = B.buildConcatVectors(
+                  SrcTy.changeElementCount(ElementCount::getFixed(4)),
                  .getReg(0);
   }
   B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane});
   MI.eraseFromParent();
   return true;
 }
 
 static bool matchBuildVectorToDup(MachineInstr &MI, MachineRegisterInfo &MRI) {

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

static cl::opt<bool> EnableNewLegality(
   cl::ReallyHidden);
 
 static constexpr unsigned MaxRegisterSize = 1024;
 
 // Round the number of elements to the next power of two elements
 static LLT getPow2VectorType(LLT Ty) {
   unsigned NElts = Ty.getNumElements();
   unsigned Pow2NElts = 1 <<  Log2_32_Ceil(NElts);
-  return Ty.changeNumElements(Pow2NElts);
+  return Ty.changeElementCount(ElementCount::getFixed(Pow2NElts));
 }
 
 // Round the number of bits to the next power of two bits
 static LLT getPow2ScalarType(LLT Ty) {
   unsigned Bits = Ty.getSizeInBits();
   unsigned Pow2Bits = 1 <<  Log2_32_Ceil(Bits);
   return LLT::scalar(Pow2Bits);
 }
if (Ty.getSizeInBits() == 32) {
     B.buildLoad(DstReg, GOTAddr, *GOTMMO);
 
   MI.eraseFromParent();
   return true;
 }
 
 static LLT widenToNextPowerOf2(LLT Ty) {
   if (Ty.isVector())
-    return Ty.changeNumElements(PowerOf2Ceil(Ty.getNumElements()));
+    return Ty.changeElementCount(
+        ElementCount::getFixed(PowerOf2Ceil(Ty.getNumElements())));
   return LLT::scalar(PowerOf2Ceil(Ty.getSizeInBits()));
 }
 
 bool AMDGPULegalizerInfo::legalizeLoad(LegalizerHelper &Helper,
                                        MachineInstr &MI) const {
   MachineIRBuilder &B = Helper.MIRBuilder;
   MachineRegisterInfo &MRI = *B.getMRI();
   GISelChangeObserver &Observer = Helper.Observer;
bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   // Confirm that the return type is large enough for the dmask specified
   if (NumElts < DMaskLanes)
     return false;
 
   if (NumElts > 4 || DMaskLanes > 4)
     return false;
 
   const unsigned AdjustedNumElts = DMaskLanes == 0 ? 1 : DMaskLanes;
-  const LLT AdjustedTy = Ty.changeNumElements(AdjustedNumElts);
+  const LLT AdjustedTy =
+      Ty.changeElementCount(ElementCount::getFixed(AdjustedNumElts));
 
   // The raw dword aligned data component of the load. The only legal cases
   // where this matters should be when using the packed D16 format, for
   // s16 -> <2 x s16>, and <3 x s16> -> <4 x s16>,
   LLT RoundedTy;
 
   // S32 vector to to cover all data, plus TFE result element.
   LLT TFETy;

llvm/unittests/CodeGen/LowLevelTypeTest.cpp

TEST(LowLevelTypeTest, ChangeNumElements) {
   const LLT V2P0 = LLT::fixed_vector(2, P0);
   const LLT V3P0 = LLT::fixed_vector(3, P0);
 
   const LLT S64 = LLT::scalar(64);
   const LLT V2S64 = LLT::fixed_vector(2, 64);
   const LLT V3S64 = LLT::fixed_vector(3, 64);
 
   // Vector to scalar
-  EXPECT_EQ(S64, V2S64.changeNumElements(1));
+  EXPECT_EQ(S64, V2S64.changeElementCount(ElementCount::getFixed(1)));
 
   // Vector to vector
-  EXPECT_EQ(V3S64, V2S64.changeNumElements(3));
+  EXPECT_EQ(V3S64, V2S64.changeElementCount(ElementCount::getFixed(3)));
 
   // Scalar to vector
-  EXPECT_EQ(V2S64, S64.changeNumElements(2));
+  EXPECT_EQ(V2S64, S64.changeElementCount(ElementCount::getFixed(2)));
 
-  EXPECT_EQ(P0, V2P0.changeNumElements(1));
-  EXPECT_EQ(V3P0, V2P0.changeNumElements(3));
-  EXPECT_EQ(V2P0, P0.changeNumElements(2));
+  EXPECT_EQ(P0, V2P0.changeElementCount(ElementCount::getFixed(1)));
+  EXPECT_EQ(V3P0, V2P0.changeElementCount(ElementCount::getFixed(3)));
+  EXPECT_EQ(V2P0, P0.changeElementCount(ElementCount::getFixed(2)));
+
+  const LLT NXV2S64 = LLT::scalable_vector(2, 64);
+  const LLT NXV3S64 = LLT::scalable_vector(3, 64);
+  const LLT NXV2P0 = LLT::scalable_vector(2, P0);
+
+  // Scalable vector to scalar
+  EXPECT_EQ(S64, NXV2S64.changeElementCount(ElementCount::getFixed(1)));
+  EXPECT_EQ(P0, NXV2P0.changeElementCount(ElementCount::getFixed(1)));
+
+  // Fixed-width vector to scalable vector
+  EXPECT_EQ(NXV3S64, V2S64.changeElementCount(ElementCount::getScalable(3)));
+
+  // Scalable vector to fixed-width vector
+  EXPECT_EQ(V3P0, NXV2P0.changeElementCount(ElementCount::getFixed(3)));
+
+  // Scalar to scalable vector
+  EXPECT_EQ(NXV2S64, S64.changeElementCount(ElementCount::getScalable(2)));
+  EXPECT_EQ(NXV2P0, P0.changeElementCount(ElementCount::getScalable(2)));
 }
 
 #ifdef GTEST_HAS_DEATH_TEST
 #ifndef NDEBUG
 
 // Invalid to directly change the element size for pointers.
 TEST(LowLevelTypeTest, ChangeElementTypeDeath) {
   const LLT P0 = LLT::pointer(0, 32);