Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -970,6 +970,13 @@
           (SH2ADD GPR:$rs1, GPR:$rs2)>;
 def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), GPR:$rs2),
           (SH3ADD GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(add (mul GPR:$rs1, (XLenVT 6)), GPR:$rs2),
+          (SH1ADD GPR:$rs1, (SH2ADD GPR:$rs1, GPR:$rs2))>;
+def : Pat<(add (mul GPR:$rs1, (XLenVT 10)), GPR:$rs2),
+          (SH1ADD GPR:$rs1, (SH3ADD GPR:$rs1, GPR:$rs2))>;
+def : Pat<(add (mul GPR:$rs1, (XLenVT 12)), GPR:$rs2),
+          (SH2ADD GPR:$rs1, (SH3ADD GPR:$rs1, GPR:$rs2))>;
 } // Predicates = [HasStdExtZba]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
Index: llvm/test/CodeGen/RISCV/rv32zba.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32zba.ll
+++ llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -91,16 +91,14 @@
 ;
 ; RV32IB-LABEL: addmul6:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 6
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh2add a1, a0, a1
+; RV32IB-NEXT:    sh1add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul6:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 6
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh2add a1, a0, a1
+; RV32IBA-NEXT:    sh1add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 6
   %d = add i32 %c, %b
@@ -117,16 +115,14 @@
 ;
 ; RV32IB-LABEL: addmul10:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 10
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh3add a1, a0, a1
+; RV32IB-NEXT:    sh1add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul10:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 10
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh3add a1, a0, a1
+; RV32IBA-NEXT:    sh1add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 10
   %d = add i32 %c, %b
@@ -143,16 +139,14 @@
 ;
 ; RV32IB-LABEL: addmul12:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 12
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh3add a1, a0, a1
+; RV32IB-NEXT:    sh2add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul12:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 12
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh3add a1, a0, a1
+; RV32IBA-NEXT:    sh2add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 12
   %d = add i32 %c, %b
Index: llvm/test/CodeGen/RISCV/rv64zba.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zba.ll
+++ llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -381,16 +381,14 @@
 ;
 ; RV64IB-LABEL: addmul6:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 6
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh2add a1, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul6:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 6
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh2add a1, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 6
   %d = add i64 %c, %b
@@ -407,16 +405,14 @@
 ;
 ; RV64IB-LABEL: addmul10:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 10
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh3add a1, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul10:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 10
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh3add a1, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 10
   %d = add i64 %c, %b
@@ -433,96 +429,16 @@
 ;
 ; RV64IB-LABEL: addmul12:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 12
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh3add a1, a0, a1
+; RV64IB-NEXT:    sh2add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul12:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 12
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh3add a1, a0, a1
+; RV64IBA-NEXT:    sh2add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 12
   %d = add i64 %c, %b
   ret i64 %d
 }
-
-define i32 @addmulw6(i32 signext %a, i32 signext %b) {
-; RV64I-LABEL: addmulw6:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a2, zero, 6
-; RV64I-NEXT:    mul a0, a0, a2
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: addmulw6:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 6
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    addw a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBA-LABEL: addmulw6:
-; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 6
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    addw a0, a0, a1
-; RV64IBA-NEXT:    ret
-  %c = mul i32 %a, 6
-  %d = add i32 %c, %b
-  ret i32 %d
-}
-
-define i32 @addmulw10(i32 signext %a, i32 signext %b) {
-; RV64I-LABEL: addmulw10:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a2, zero, 10
-; RV64I-NEXT:    mul a0, a0, a2
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: addmulw10:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 10
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    addw a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBA-LABEL: addmulw10:
-; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 10
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    addw a0, a0, a1
-; RV64IBA-NEXT:    ret
-  %c = mul i32 %a, 10
-  %d = add i32 %c, %b
-  ret i32 %d
-}
-
-define i32 @addmulw12(i32 signext %a, i32 signext %b) {
-; RV64I-LABEL: addmulw12:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a2, zero, 12
-; RV64I-NEXT:    mul a0, a0, a2
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: addmulw12:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 12
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    addw a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBA-LABEL: addmulw12:
-; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 12
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    addw a0, a0, a1
-; RV64IBA-NEXT:    ret
-  %c = mul i32 %a, 12
-  %d = add i32 %c, %b
-  ret i32 %d
-}