diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6738,8 +6738,8 @@
   return true;
 }
 
-static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
-                                                    bool IsPPC64) {
+static const TargetRegisterClass *
+getRegClassForSVT(MVT::SimpleValueType SVT, bool IsPPC64, bool HasP8Vector) {
   assert((IsPPC64 || SVT != MVT::i64) &&
          "i64 should have been split for 32-bit codegen.");
 
@@ -6751,9 +6751,9 @@
   case MVT::i64:
     return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
   case MVT::f32:
-    return &PPC::F4RCRegClass;
+    return HasP8Vector ? &PPC::VSSRCRegClass : &PPC::F4RCRegClass;
   case MVT::f64:
-    return &PPC::F8RCRegClass;
+    return HasP8Vector ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass;
   case MVT::v4f32:
   case MVT::v4i32:
   case MVT::v8i16:
@@ -6929,7 +6929,8 @@
         assert(VA.getValNo() == OriginalValNo &&
                "ValNo mismatch between custom MemLoc and RegLoc.");
         MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy;
-        MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+        MF.addLiveIn(VA.getLocReg(),
+                     getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector()));
       };
 
       HandleMemLoc();
@@ -7068,8 +7069,9 @@
 
     if (VA.isRegLoc() && !VA.needsCustom()) {
       MVT::SimpleValueType SVT = ValVT.SimpleTy;
-      unsigned VReg =
-          MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+      unsigned VReg = MF.addLiveIn(
+          VA.getLocReg(),
+          getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector()));
       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
       if (ValVT.isScalarInteger() &&
           (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
diff --git a/llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll b/llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll
@@ -0,0 +1,72 @@
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff  -verify-machineinstrs -mcpu=pwr8 -stop-after=machine-cp \
+; RUN:   -debug-only=isel -o - 2>&1 %s | FileCheck %s --check-prefix=POWR8
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff  -verify-machineinstrs -mcpu=pwr7 -stop-after=machine-cp \
+; RUN:   -debug-only=isel -o - 2>&1 %s | FileCheck %s --check-prefix=POWR7
+
+define float @vssr(float %a, float %b, float %c, float %d, float %e) {
+entry:
+  %add = fadd float %a, %b
+  %add1 = fadd float %add, %c
+  %add2 = fadd float %add1, %d
+  %add3 = fadd float %add2, %e
+  ret float %add3
+}
+
+; POWR8-LABEL:  MachineFunction at end of ISel
+; POWR8-NOT:  f4rc
+; POWR8:      %4:vssrc = COPY $f5
+; POWR8:      %3:vssrc = COPY $f4
+; POWR8:      %2:vssrc = COPY $f3
+; POWR8:      %1:vssrc = COPY $f2
+; POWR8:      %0:vssrc = COPY $f1
+; POWR8:      %5:vssrc = nofpexcept XSADDSP %0:vssrc, %1:vssrc
+; POWR8:      %6:vssrc = nofpexcept XSADDSP killed %5:vssrc, %2:vssrc
+; POWR8:      %7:vssrc = nofpexcept XSADDSP killed %6:vssrc, %3:vssrc
+; POWR8:      %8:vssrc = nofpexcept XSADDSP killed %7:vssrc, %4:vssrc
+; POWR8:      $f1 = COPY %8:vssrc
+
+; POWR7-LABEL:  MachineFunction at end of ISel
+; POWR7:      %4:f4rc = COPY $f5
+; POWR7:      %3:f4rc = COPY $f4
+; POWR7:      %2:f4rc = COPY $f3
+; POWR7:      %1:f4rc = COPY $f2
+; POWR7:      %0:f4rc = COPY $f1
+; POWR7:      %5:f4rc = nofpexcept FADDS %0:f4rc, %1:f4rc, implicit $rm
+; POWR7:      %6:f4rc = nofpexcept FADDS killed %5:f4rc, %2:f4rc, implicit $rm
+; POWR7:      %7:f4rc = nofpexcept FADDS killed %6:f4rc, %3:f4rc, implicit $rm
+; POWR7:      %8:f4rc = nofpexcept FADDS killed %7:f4rc, %4:f4rc, implicit $rm
+; POWR7:      $f1 = COPY %8:f4rc
+
+define double @vsfr(double %a, double %b, double %c, double %d, double %e) {
+entry:
+  %add = fadd double %a, %b
+  %add1 = fadd double %add, %c
+  %add2 = fadd double %add1, %d
+  %add3 = fadd double %add2, %e
+  ret double %add3
+}
+
+; POWR8-LABEL:  MachineFunction at end of ISel
+; POWR8-NOT:    f8rc
+; POWR8:        %4:vsfrc = COPY $f5
+; POWR8:        %3:vsfrc = COPY $f4
+; POWR8:        %2:vsfrc = COPY $f3
+; POWR8:        %1:vsfrc = COPY $f2
+; POWR8:        %0:vsfrc = COPY $f1
+; POWR8:        %5:vsfrc = nofpexcept XSADDDP %0:vsfrc, %1:vsfrc, implicit $rm
+; POWR8:        %6:vsfrc = nofpexcept XSADDDP killed %5:vsfrc, %2:vsfrc, implicit $rm
+; POWR8:        %7:vsfrc = nofpexcept XSADDDP killed %6:vsfrc, %3:vsfrc, implicit $rm
+; POWR8:        %8:vsfrc = nofpexcept XSADDDP killed %7:vsfrc, %4:vsfrc, implicit $rm
+; POWR8:        $f1 = COPY %8:vsfrc
+
+; POWR7-LABEL:  MachineFunction at end of ISel
+; POWR7:        %4:f8rc = COPY $f5
+; POWR7:        %3:f8rc = COPY $f4
+; POWR7:        %2:f8rc = COPY $f3
+; POWR7:        %1:f8rc = COPY $f2
+; POWR7:        %0:f8rc = COPY $f1
+; POWR7:        %5:vsfrc = nofpexcept XSADDDP %0:f8rc, %1:f8rc, implicit $rm
+; POWR7:        %6:vsfrc = nofpexcept XSADDDP killed %5:vsfrc, %2:f8rc, implicit $rm
+; POWR7:        %7:vsfrc = nofpexcept XSADDDP killed %6:vsfrc, %3:f8rc, implicit $rm
+; POWR7:        %8:vsfrc = nofpexcept XSADDDP killed %7:vsfrc, %4:f8rc, implicit $rm
+; POWR7:        $f1 = COPY %8:vsfrc