Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -114,6 +114,9 @@ "AvoidMOVsShifterOperand", "true", "Avoid movs instructions with shifter operand">; +def FeatureRestrictedIT : SubtargetFeature<"restrict-it", "RestrictIT", "true", + "Restrict generation of IT blocks">; + // Some processors perform return stack prediction. CodeGen should avoid issue // "normal" call instructions to callees which do not return. def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", Index: lib/Target/ARM/ARMSubtarget.cpp =================================================================== --- lib/Target/ARM/ARMSubtarget.cpp +++ lib/Target/ARM/ARMSubtarget.cpp @@ -43,23 +43,6 @@ UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden); -enum ITMode { - DefaultIT, - RestrictedIT, - NoRestrictedIT -}; - -static cl::opt -IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), - cl::ZeroOrMore, - cl::values(clEnumValN(DefaultIT, "arm-default-it", - "Generate IT block based on arch"), - clEnumValN(RestrictedIT, "arm-restrict-it", - "Disallow deprecated IT based on ARMv8"), - clEnumValN(NoRestrictedIT, "arm-no-restrict-it", - "Allow IT blocks based on ARMv7"), - clEnumValEnd)); - /// initializeSubtargetDependencies - Initializes using a CPU and feature string /// so that we can use initializer lists for subtarget initialization. ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU, @@ -145,6 +128,7 @@ UseNaClTrap = false; GenLongCalls = false; UnsafeFPMath = false; + RestrictIT = false; } void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { @@ -192,18 +176,6 @@ else SupportsTailCall = !isThumb1Only(); - switch (IT) { - case DefaultIT: - RestrictIT = hasV8Ops(); - break; - case RestrictedIT: - RestrictIT = true; - break; - case NoRestrictedIT: - RestrictIT = false; - break; - } - // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default. const FeatureBitset &Bits = getFeatureBits(); if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters Index: test/CodeGen/ARM/2013-05-05-IfConvertBug.ll =================================================================== --- test/CodeGen/ARM/2013-05-05-IfConvertBug.ll +++ test/CodeGen/ARM/2013-05-05-IfConvertBug.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s -; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-V8 %s +; RUN: llc < %s -mtriple=thumbv8 -mattr=+restrict-it | FileCheck -check-prefix=CHECK-V8 %s +; RUN: llc < %s -mtriple=thumbv7 -mattr=+restrict-it | FileCheck -check-prefix=CHECK-V8 %s ; rdar://13782395 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { Index: test/CodeGen/ARM/2014-08-04-muls-it.ll =================================================================== --- test/CodeGen/ARM/2014-08-04-muls-it.ll +++ test/CodeGen/ARM/2014-08-04-muls-it.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple thumbv7-eabi -arm-restrict-it -filetype asm -o - %s \ +; RUN: llc -mtriple thumbv7-eabi -mattr=+restrict-it -filetype asm -o - %s \ ; RUN: | FileCheck %s define arm_aapcscc i32 @function(i32 %i, i32 %j) { Index: test/CodeGen/ARM/arm-and-tst-peephole.ll =================================================================== --- test/CodeGen/ARM/arm-and-tst-peephole.ll +++ test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=thumb-eabi -arm-atomic-cfg-tidy=0 %s -o - | FileCheck -check-prefix=THUMB %s ; RUN: llc -mtriple=thumb-eabi -arm-atomic-cfg-tidy=0 -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ ; RUN: | FileCheck -check-prefix=T2 %s -; RUN: llc -mtriple=thumbv8-eabi -arm-atomic-cfg-tidy=0 %s -o - | FileCheck -check-prefix=V8 %s +; RUN: llc -mtriple=thumbv8-eabi -arm-atomic-cfg-tidy=0 -mattr=+restrict-it %s -o - | FileCheck -check-prefix=V8 %s ; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified. Index: test/CodeGen/ARM/ifcvt-branch-weight.ll =================================================================== --- test/CodeGen/ARM/ifcvt-branch-weight.ll +++ test/CodeGen/ARM/ifcvt-branch-weight.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv8 -print-machineinstrs=if-converter -arm-atomic-cfg-tidy=0 -o /dev/null 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 -print-machineinstrs=if-converter -arm-atomic-cfg-tidy=0 -mattr=+restrict-it -o /dev/null 2>&1 | FileCheck %s %struct.S = type { i8* (i8*)*, [1 x i8] } define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { Index: test/CodeGen/ARM/thumb2-it-block.ll =================================================================== --- test/CodeGen/ARM/thumb2-it-block.ll +++ test/CodeGen/ARM/thumb2-it-block.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8 -mattr=+restrict-it %s -o - | FileCheck %s ; PR11107 define i32 @test(i32 %a, i32 %b) { Index: test/CodeGen/Thumb2/restict-it-fnattr.ll =================================================================== --- /dev/null +++ test/CodeGen/Thumb2/restict-it-fnattr.ll @@ -0,0 +1,61 @@ +; RUN: llc < %s -mtriple=thumbv7 -mcpu=cortex-a8 | FileCheck %s -check-prefix=NO-OPTION +; RUN: llc < %s -mtriple=thumbv7 -mcpu=cortex-a8 -mattr=+restrict-it | FileCheck %s -check-prefix=RESTRICT-IT + +; NO-OPTION-LABEL: {{\_?}}no_restrict_it: +; NO-OPTION: itt gt +; NO-OPTION-NEXT: addgt +; NO-OPTION-NEXT: addgt + +; RESTRICT-IT-LABEL: {{\_?}}no_restrict_it: +; RESTRICT-IT: it gt +; RESTRICT-IT-NEXT: addgt +; RESTRICT-IT: it gt +; RESTRICT-IT-NEXT: addgt + +define i32 @no_restrict_it(i32 %a, i32 %b) { +entry: + %cmp = icmp sgt i32 %a, 5 + br i1 %cmp, label %if.then, label %if.end + +if.then: + %add0 = add nsw i32 %a, 1 + %add1 = add nsw i32 %b, 2 + br label %if.end + +if.end: + %t0.0 = phi i32 [ %add0, %if.then ], [ %a, %entry ] + %t1.0 = phi i32 [ %add1, %if.then ], [ %b, %entry ] + %mul = mul nsw i32 %t1.0, %t0.0 + ret i32 %mul +} + +; NO-OPTION-LABEL: {{\_?}}restrict_it: +; NO-OPTION: it gt +; NO-OPTION-NEXT: addgt +; NO-OPTION: it gt +; NO-OPTION-NEXT: addgt + +; RESTRICT-IT-LABEL: {{\_?}}restrict_it: +; RESTRICT-IT: it gt +; RESTRICT-IT-NEXT: addgt +; RESTRICT-IT: it gt +; RESTRICT-IT-NEXT: addgt + +define i32 @restrict_it(i32 %a, i32 %b) #0 { +entry: + %cmp = icmp sgt i32 %a, 5 + br i1 %cmp, label %if.then, label %if.end + +if.then: + %add0 = add nsw i32 %a, 1 + %add1 = add nsw i32 %b, 2 + br label %if.end + +if.end: + %t0.0 = phi i32 [ %add0, %if.then ], [ %a, %entry ] + %t1.0 = phi i32 [ %add1, %if.then ], [ %b, %entry ] + %mul = mul nsw i32 %t1.0, %t0.0 + ret i32 %mul +} + +attributes #0 = { "target-features"="+restrict-it" } Index: test/CodeGen/Thumb2/thumb2-ifcvt1.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-ifcvt1.ll +++ test/CodeGen/Thumb2/thumb2-ifcvt1.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it |FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: t1: ; CHECK: ittt ne Index: test/CodeGen/Thumb2/thumb2-ifcvt2.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-ifcvt2.ll +++ test/CodeGen/Thumb2/thumb2-ifcvt2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-atomic-cfg-tidy=0 -arm-default-it | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8-apple-ios -arm-atomic-cfg-tidy=0 -arm-no-restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s define void @foo(i32 %X, i32 %Y) { entry: Index: test/CodeGen/Thumb2/thumb2-ifcvt3.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 -arm-default-it | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8-apple-darwin -arm-atomic-cfg-tidy=0 -arm-no-restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8-apple-darwin -arm-atomic-cfg-tidy=0 | FileCheck %s ; There shouldn't be a unconditional branch at end of bb52. ; rdar://7184787 Index: test/CodeGen/Thumb2/v8_IT_1.ll =================================================================== --- test/CodeGen/Thumb2/v8_IT_1.ll +++ test/CodeGen/Thumb2/v8_IT_1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv8 -mattr=+neon | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7 -mattr=+neon -arm-restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 -mattr=+neon -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -mattr=+neon -mattr=+restrict-it | FileCheck %s ;CHECK-LABEL: select_s_v_v: ;CHECK-NOT: it Index: test/CodeGen/Thumb2/v8_IT_2.ll =================================================================== --- test/CodeGen/Thumb2/v8_IT_2.ll +++ test/CodeGen/Thumb2/v8_IT_2.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -mattr=+restrict-it | FileCheck %s %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } Index: test/CodeGen/Thumb2/v8_IT_3.ll =================================================================== --- test/CodeGen/Thumb2/v8_IT_3.ll +++ test/CodeGen/Thumb2/v8_IT_3.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -arm-restrict-it | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC -; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -arm-restrict-it -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC +; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 -mattr=+restrict-it -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC +; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -mattr=+restrict-it -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC %struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* } %struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 } Index: test/CodeGen/Thumb2/v8_IT_4.ll =================================================================== --- test/CodeGen/Thumb2/v8_IT_4.ll +++ test/CodeGen/Thumb2/v8_IT_4.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -arm-restrict-it | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -regalloc=basic | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -regalloc=basic -arm-restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -regalloc=basic -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -regalloc=basic -mattr=+restrict-it | FileCheck %s %"struct.__gnu_cxx::__normal_iterator, std::allocator > >" = type { i8* } %"struct.__gnu_cxx::new_allocator" = type <{ i8 }> Index: test/CodeGen/Thumb2/v8_IT_5.ll =================================================================== --- test/CodeGen/Thumb2/v8_IT_5.ll +++ test/CodeGen/Thumb2/v8_IT_5.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -arm-restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 -mattr=+restrict-it | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -mattr=+restrict-it | FileCheck %s ; CHECK: it ne ; CHECK-NEXT: cmpne ; CHECK-NEXT: bne [[JUMPTARGET:.LBB[0-9]+_[0-9]+]]