diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1321,7 +1321,7 @@ unsigned AddrSpace) const; /// \returns True if it is legal to vectorize the given reduction kind. - bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, + bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const; /// \returns The new vector factor value if the target doesn't support \p @@ -1705,7 +1705,7 @@ virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const = 0; - virtual bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, + virtual bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const = 0; virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, @@ -2254,7 +2254,7 @@ return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment, AddrSpace); } - bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, + bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const override { return Impl.isLegalToVectorizeReduction(RdxDesc, VF); } diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -715,7 +715,7 @@ return true; } - bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, + bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const { return true; } diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h --- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h +++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h @@ -370,12 +370,13 @@ /// required to implement the reduction. /// Fast-math-flags are propagated using the RecurrenceDescriptor. Value *createTargetReduction(IRBuilderBase &B, const TargetTransformInfo *TTI, - RecurrenceDescriptor &Desc, Value *Src); + const RecurrenceDescriptor &Desc, Value *Src); /// Create an ordered reduction intrinsic using the given recurrence /// descriptor \p Desc. -Value *createOrderedReduction(IRBuilderBase &B, RecurrenceDescriptor &Desc, - Value *Src, Value *Start); +Value *createOrderedReduction(IRBuilderBase &B, + const RecurrenceDescriptor &Desc, Value *Src, + Value *Start); /// Get the intersection (logical and) of all of the potential IR flags /// of each scalar operation (VL) that will be converted into a vector (I). diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -999,7 +999,7 @@ } bool TargetTransformInfo::isLegalToVectorizeReduction( - RecurrenceDescriptor RdxDesc, ElementCount VF) const { + const RecurrenceDescriptor &RdxDesc, ElementCount VF) const { return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -292,7 +292,7 @@ bool supportsScalableVectors() const { return ST->hasSVE(); } - bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, + bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const; InstructionCost getArithmeticReductionCost( diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -1664,8 +1664,8 @@ return Considerable; } -bool AArch64TTIImpl::isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, - ElementCount VF) const { +bool AArch64TTIImpl::isLegalToVectorizeReduction( + const RecurrenceDescriptor &RdxDesc, ElementCount VF) const { if (!VF.isScalable()) return true; diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -148,7 +148,7 @@ return VPLegalization(VPLegalization::Legal, VPLegalization::Legal); } - bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, + bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const { if (!ST->hasStdExtV()) return false; diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp --- a/llvm/lib/Transforms/Utils/LoopUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp @@ -1000,7 +1000,8 @@ Value *llvm::createTargetReduction(IRBuilderBase &B, const TargetTransformInfo *TTI, - RecurrenceDescriptor &Desc, Value *Src) { + const RecurrenceDescriptor &Desc, + Value *Src) { // TODO: Support in-order reductions based on the recurrence descriptor. // All ops in the reduction inherit fast-math-flags from the recurrence // descriptor. @@ -1010,8 +1011,8 @@ } Value *llvm::createOrderedReduction(IRBuilderBase &B, - RecurrenceDescriptor &Desc, Value *Src, - Value *Start) { + const RecurrenceDescriptor &Desc, + Value *Src, Value *Start) { assert(Desc.getRecurrenceKind() == RecurKind::FAdd && "Unexpected reduction kind"); assert(Src->getType()->isVectorTy() && "Expected a vector type"); diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp @@ -921,7 +921,7 @@ // have the isOrdered flag set, which indicates that we can move the // reduction operations in-loop. return (all_of(getReductionVars(), [&](auto &Reduction) -> bool { - RecurrenceDescriptor RdxDesc = Reduction.second; + const RecurrenceDescriptor &RdxDesc = Reduction.second; return !RdxDesc.hasExactFPMath() || RdxDesc.isOrdered(); })); } diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -598,7 +598,7 @@ void fixReduction(VPWidenPHIRecipe *Phi, VPTransformState &State); /// Clear NSW/NUW flags from reduction instructions if necessary. - void clearReductionWrapFlags(RecurrenceDescriptor &RdxDesc, + void clearReductionWrapFlags(const RecurrenceDescriptor &RdxDesc, VPTransformState &State); /// Fixup the LCSSA phi nodes in the unique exit block. This simply @@ -1310,7 +1310,7 @@ /// RdxDesc. This is true if the -enable-strict-reductions flag is passed, /// the IsOrdered flag of RdxDesc is set and we do not allow reordering /// of FP operations. - bool useOrderedReductions(RecurrenceDescriptor &RdxDesc) { + bool useOrderedReductions(const RecurrenceDescriptor &RdxDesc) { return EnableStrictReductions && !Hints->allowReordering() && RdxDesc.isOrdered(); } @@ -1515,7 +1515,7 @@ /// variables found for the given VF. bool canVectorizeReductions(ElementCount VF) { return (all_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { - RecurrenceDescriptor RdxDesc = Reduction.second; + const RecurrenceDescriptor &RdxDesc = Reduction.second; return TTI.isLegalToVectorizeReduction(RdxDesc, VF); })); } @@ -4331,7 +4331,7 @@ // Get it's reduction variable descriptor. assert(Legal->isReductionVariable(OrigPhi) && "Unable to find the reduction variable"); - RecurrenceDescriptor RdxDesc = *PhiR->getRecurrenceDescriptor(); + const RecurrenceDescriptor &RdxDesc = *PhiR->getRecurrenceDescriptor(); RecurKind RK = RdxDesc.getRecurrenceKind(); TrackingVH ReductionStartValue = RdxDesc.getRecurrenceStartValue(); @@ -4512,7 +4512,7 @@ OrigPhi->setIncomingValue(IncomingEdgeBlockIdx, LoopExitInst); } -void InnerLoopVectorizer::clearReductionWrapFlags(RecurrenceDescriptor &RdxDesc, +void InnerLoopVectorizer::clearReductionWrapFlags(const RecurrenceDescriptor &RdxDesc, VPTransformState &State) { RecurKind RK = RdxDesc.getRecurrenceKind(); if (RK != RecurKind::Add && RK != RecurKind::Mul) @@ -6273,7 +6273,7 @@ if (auto *PN = dyn_cast(&I)) { if (!Legal->isReductionVariable(PN)) continue; - RecurrenceDescriptor RdxDesc = Legal->getReductionVars()[PN]; + const RecurrenceDescriptor &RdxDesc = Legal->getReductionVars()[PN]; if (PreferInLoopReductions || useOrderedReductions(RdxDesc) || TTI.preferInLoopReduction(RdxDesc.getOpcode(), RdxDesc.getRecurrenceType(), @@ -7173,7 +7173,7 @@ while (!isa(ReductionPhi)) ReductionPhi = InLoopReductionImmediateChains[ReductionPhi]; - RecurrenceDescriptor RdxDesc = + const RecurrenceDescriptor &RdxDesc = Legal->getReductionVars()[cast(ReductionPhi)]; InstructionCost BaseCost = TTI.getArithmeticReductionCost( RdxDesc.getOpcode(), VectorTy, false, CostKind);