Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -128,6 +128,49 @@
                                    SDLoc(N), N->getValueType(0));
 }]>;
 
+// Check if (and r, i) can be optimized to (BCLRI (BCLRI r, i0), i1),
+// in which i = ~((1<<i0) | (1<<i1)).
+def BCLRITwoBitsMask : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  // The immediate should not be a simm12.
+  if (isInt<12>(N->getSExtValue()))
+    return false;
+  // The immediate must have exactly two bits clear.
+  uint64_t I = static_cast<uint64_t>(~N->getSExtValue());
+  return countPopulation(I) == 2;
+}]>;
+
+def BCLRITwoBitsMaskLow : SDNodeXForm<imm, [{
+  uint64_t I = static_cast<uint64_t>(~N->getSExtValue());
+  return CurDAG->getTargetConstant(countTrailingZeros(I), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def BCLRITwoBitsMaskHigh : SDNodeXForm<imm, [{
+  uint64_t I = static_cast<uint64_t>(~N->getSExtValue());
+  return CurDAG->getTargetConstant(63 - countLeadingZeros(I), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+// Check if (and r, i) can be optimized to (BCLRI (ANDI r, i0), i1),
+// in which i = i0 & ~(1<<i1).
+def BCLRIANDIMask : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  // The immediate should not be a simm12.
+  if (isInt<12>(N->getSExtValue()))
+    return false;
+  // There should be only one clear bit from bit 11 to the top.
+  uint64_t I = static_cast<uint64_t>(~N->getSExtValue());
+  return isPowerOf2_64(I & ~0x7ff);
+}]>;
+
+def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue() & 0x7ff | ~0x7ff,
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
@@ -777,6 +820,12 @@
 def : Pat<(xor GPR:$r, BSETINVORIMask:$i),
           (BINVI (XORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
+def : Pat<(and GPR:$r, BCLRITwoBitsMask:$i),
+          (BCLRI (BCLRI GPR:$r, (BCLRITwoBitsMaskLow BCLRITwoBitsMask:$i)),
+                 (BCLRITwoBitsMaskHigh BCLRITwoBitsMask:$i))>;
+def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
+          (BCLRI (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i)),
+                 (BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>;
 }
 
 // There's no encoding for roli in the the 'B' extension as it can be
Index: llvm/test/CodeGen/RISCV/rv32zbs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -560,16 +560,14 @@
 ;
 ; RV32IB-LABEL: sbclri_i32_large0:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    lui a1, 1044480
-; RV32IB-NEXT:    addi a1, a1, -256
-; RV32IB-NEXT:    and a0, a0, a1
+; RV32IB-NEXT:    andi a0, a0, -256
+; RV32IB-NEXT:    bclri a0, a0, 24
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_large0:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    lui a1, 1044480
-; RV32IBS-NEXT:    addi a1, a1, -256
-; RV32IBS-NEXT:    and a0, a0, a1
+; RV32IBS-NEXT:    andi a0, a0, -256
+; RV32IBS-NEXT:    bclri a0, a0, 24
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -16777472
   ret i32 %and
@@ -585,16 +583,14 @@
 ;
 ; RV32IB-LABEL: sbclri_i32_large1:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    lui a1, 1044464
-; RV32IB-NEXT:    addi a1, a1, -1
-; RV32IB-NEXT:    and a0, a0, a1
+; RV32IB-NEXT:    bclri a0, a0, 16
+; RV32IB-NEXT:    bclri a0, a0, 24
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_large1:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    lui a1, 1044464
-; RV32IBS-NEXT:    addi a1, a1, -1
-; RV32IBS-NEXT:    and a0, a0, a1
+; RV32IBS-NEXT:    bclri a0, a0, 16
+; RV32IBS-NEXT:    bclri a0, a0, 24
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -16842753
   ret i32 %and
Index: llvm/test/CodeGen/RISCV/rv64zbs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -810,16 +810,14 @@
 ;
 ; RV64IB-LABEL: sbclri_i64_large0:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a1, 1044480
-; RV64IB-NEXT:    addiw a1, a1, -256
-; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    andi a0, a0, -256
+; RV64IB-NEXT:    bclri a0, a0, 24
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_large0:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    lui a1, 1044480
-; RV64IBS-NEXT:    addiw a1, a1, -256
-; RV64IBS-NEXT:    and a0, a0, a1
+; RV64IBS-NEXT:    andi a0, a0, -256
+; RV64IBS-NEXT:    bclri a0, a0, 24
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -16777472
   ret i64 %and
@@ -835,16 +833,14 @@
 ;
 ; RV64IB-LABEL: sbclri_i64_large1:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a1, 1044464
-; RV64IB-NEXT:    addiw a1, a1, -1
-; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    bclri a0, a0, 16
+; RV64IB-NEXT:    bclri a0, a0, 24
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_large1:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    lui a1, 1044464
-; RV64IBS-NEXT:    addiw a1, a1, -1
-; RV64IBS-NEXT:    and a0, a0, a1
+; RV64IBS-NEXT:    bclri a0, a0, 16
+; RV64IBS-NEXT:    bclri a0, a0, 24
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -16842753
   ret i64 %and