diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -839,6 +839,7 @@
       setOperationAction(ISD::SETCC, VT, Legal);
       for (auto CC : RVPCCToExpand)
         setCondCodeAction(CC, VT, Expand);
+      setOperationAction(ISD::VSELECT, VT, Legal);
 
       // Promote load and store operations.
       setOperationAction(ISD::LOAD, VT, Promote);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1392,3 +1392,24 @@
 def : Pat<(XVEI16VT (setule (XVEI16VT GPR:$rs1), GPR:$rs2)),
           (UCMPLE16 GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZpn]
+
+// max, min
+let Predicates = [HasStdExtZpn] in {
+def : Pat<(vselect (XVEI8VT (setlt (XVEI8VT GPR:$rs1), GPR:$rs2)), GPR:$rs2, GPR:$rs1),
+          (SMAX8 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(vselect (XVEI8VT (setle (XVEI8VT GPR:$rs1), GPR:$rs2)), GPR:$rs2, GPR:$rs1),
+          (SMAX8 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(vselect (XVEI8VT (setlt (XVEI8VT GPR:$rs1), GPR:$rs2)), GPR:$rs1, GPR:$rs2),
+          (SMIN8 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(vselect (XVEI8VT (setle (XVEI8VT GPR:$rs1), GPR:$rs2)), GPR:$rs1, GPR:$rs2),
+          (SMIN8 GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(vselect (XVEI16VT (setlt (XVEI16VT GPR:$rs1), GPR:$rs2)), GPR:$rs2, GPR:$rs1),
+          (SMAX16 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(vselect (XVEI16VT (setle (XVEI16VT GPR:$rs1), GPR:$rs2)), GPR:$rs2, GPR:$rs1),
+          (SMAX16 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(vselect (XVEI16VT (setlt (XVEI16VT GPR:$rs1), GPR:$rs2)), GPR:$rs1, GPR:$rs2),
+          (SMIN16 GPR:$rs1, GPR:$rs2)>;
+def : Pat<(vselect (XVEI16VT (setle (XVEI16VT GPR:$rs1), GPR:$rs2)), GPR:$rs1, GPR:$rs2),
+          (SMIN16 GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtZpn]
diff --git a/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll b/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll
--- a/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll
+++ b/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll
@@ -9,22 +9,12 @@
 define i32 @smaxv4i8_1(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv4i8_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a2, a0, a1
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smax8 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i8_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -37,22 +27,12 @@
 define i32 @smaxv4i8_2(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv4i8_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a2, a0, a1
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smax8 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i8_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -65,22 +45,12 @@
 define i32 @smaxv4i8_3(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv4i8_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a2, a1, a0
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smax8 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i8_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -93,22 +63,12 @@
 define i32 @smaxv4i8_4(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv4i8_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a2, a1, a0
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smax8 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i8_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -121,27 +81,13 @@
 define i64 @smaxv8i8_1(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv8i8_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a4, a0, a2
-; RV32-NEXT:    scmplt8 a5, a1, a3
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smax8 a1, a1, a3
+; RV32-NEXT:    smax8 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv8i8_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -154,27 +100,13 @@
 define i64 @smaxv8i8_2(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv8i8_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a4, a0, a2
-; RV32-NEXT:    scmple8 a5, a1, a3
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smax8 a1, a1, a3
+; RV32-NEXT:    smax8 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv8i8_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -187,27 +119,13 @@
 define i64 @smaxv8i8_3(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv8i8_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a4, a2, a0
-; RV32-NEXT:    scmplt8 a5, a3, a1
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smax8 a1, a3, a1
+; RV32-NEXT:    smax8 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv8i8_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -220,27 +138,13 @@
 define i64 @smaxv8i8_4(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv8i8_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a4, a2, a0
-; RV32-NEXT:    scmple8 a5, a3, a1
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smax8 a1, a3, a1
+; RV32-NEXT:    smax8 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv8i8_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -255,22 +159,12 @@
 define i32 @sminv4i8_1(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv4i8_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a2, a0, a1
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smin8 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i8_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -283,22 +177,12 @@
 define i32 @sminv4i8_2(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv4i8_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a2, a0, a1
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smin8 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i8_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -311,22 +195,12 @@
 define i32 @sminv4i8_3(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv4i8_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a2, a1, a0
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smin8 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i8_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -339,22 +213,12 @@
 define i32 @sminv4i8_4(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv4i8_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a2, a1, a0
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smin8 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i8_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -367,27 +231,13 @@
 define i64 @sminv8i8_1(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv8i8_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a4, a0, a2
-; RV32-NEXT:    scmplt8 a5, a1, a3
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smin8 a1, a1, a3
+; RV32-NEXT:    smin8 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv8i8_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -400,27 +250,13 @@
 define i64 @sminv8i8_2(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv8i8_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a4, a0, a2
-; RV32-NEXT:    scmple8 a5, a1, a3
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smin8 a1, a1, a3
+; RV32-NEXT:    smin8 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv8i8_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin8 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -433,27 +269,13 @@
 define i64 @sminv8i8_3(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv8i8_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt8 a4, a2, a0
-; RV32-NEXT:    scmplt8 a5, a3, a1
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smin8 a1, a3, a1
+; RV32-NEXT:    smin8 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv8i8_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt8 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -466,27 +288,13 @@
 define i64 @sminv8i8_4(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv8i8_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple8 a4, a2, a0
-; RV32-NEXT:    scmple8 a5, a3, a1
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smin8 a1, a3, a1
+; RV32-NEXT:    smin8 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv8i8_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple8 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin8 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -501,22 +309,12 @@
 define i32 @smaxv2i16_1(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv2i16_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a2, a0, a1
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smax16 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv2i16_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -529,22 +327,12 @@
 define i32 @smaxv2i16_2(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv2i16_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a2, a0, a1
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smax16 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv2i16_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -557,22 +345,12 @@
 define i32 @smaxv2i16_3(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv2i16_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a2, a1, a0
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smax16 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv2i16_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -585,22 +363,12 @@
 define i32 @smaxv2i16_4(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: smaxv2i16_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a2, a1, a0
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smax16 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv2i16_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -613,27 +381,13 @@
 define i64 @smaxv4i16_1(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv4i16_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a4, a0, a2
-; RV32-NEXT:    scmplt16 a5, a1, a3
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smax16 a1, a1, a3
+; RV32-NEXT:    smax16 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i16_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -646,27 +400,13 @@
 define i64 @smaxv4i16_2(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv4i16_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a4, a0, a2
-; RV32-NEXT:    scmple16 a5, a1, a3
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smax16 a1, a1, a3
+; RV32-NEXT:    smax16 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i16_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a0, a1
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smax16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -679,27 +419,13 @@
 define i64 @smaxv4i16_3(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv4i16_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a4, a2, a0
-; RV32-NEXT:    scmplt16 a5, a3, a1
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smax16 a1, a3, a1
+; RV32-NEXT:    smax16 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i16_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -712,27 +438,13 @@
 define i64 @smaxv4i16_4(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: smaxv4i16_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a4, a2, a0
-; RV32-NEXT:    scmple16 a5, a3, a1
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smax16 a1, a3, a1
+; RV32-NEXT:    smax16 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smaxv4i16_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a1, a0
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smax16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -747,22 +459,12 @@
 define i32 @sminv2i16_1(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv2i16_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a2, a0, a1
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smin16 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv2i16_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -775,22 +477,12 @@
 define i32 @sminv2i16_2(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv2i16_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a2, a0, a1
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    smin16 a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv2i16_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -803,22 +495,12 @@
 define i32 @sminv2i16_3(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv2i16_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a2, a1, a0
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smin16 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv2i16_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -831,22 +513,12 @@
 define i32 @sminv2i16_4(i32 %a, i32 %b) nounwind {
 ; RV32-LABEL: sminv2i16_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a2, a1, a0
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    addi a3, zero, -1
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    smin16 a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv2i16_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -859,27 +531,13 @@
 define i64 @sminv4i16_1(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv4i16_1:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a4, a0, a2
-; RV32-NEXT:    scmplt16 a5, a1, a3
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smin16 a1, a1, a3
+; RV32-NEXT:    smin16 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i16_1:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -892,27 +550,13 @@
 define i64 @sminv4i16_2(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv4i16_2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a4, a0, a2
-; RV32-NEXT:    scmple16 a5, a1, a3
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    or a1, a1, a3
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a2, a2, a3
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    smin16 a1, a1, a3
+; RV32-NEXT:    smin16 a0, a0, a2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i16_2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    smin16 a0, a0, a1
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -925,27 +569,13 @@
 define i64 @sminv4i16_3(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv4i16_3:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmplt16 a4, a2, a0
-; RV32-NEXT:    scmplt16 a5, a3, a1
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smin16 a1, a3, a1
+; RV32-NEXT:    smin16 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i16_3:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmplt16 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -958,27 +588,13 @@
 define i64 @sminv4i16_4(i64 %a, i64 %b) nounwind {
 ; RV32-LABEL: sminv4i16_4:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    scmple16 a4, a2, a0
-; RV32-NEXT:    scmple16 a5, a3, a1
-; RV32-NEXT:    and a3, a3, a5
-; RV32-NEXT:    addi a6, zero, -1
-; RV32-NEXT:    xor a5, a5, a6
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    and a2, a2, a4
-; RV32-NEXT:    xor a3, a4, a6
-; RV32-NEXT:    and a0, a0, a3
-; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    smin16 a1, a3, a1
+; RV32-NEXT:    smin16 a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: sminv4i16_4:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    scmple16 a2, a1, a0
-; RV64-NEXT:    and a1, a1, a2
-; RV64-NEXT:    addi a3, zero, -1
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    smin16 a0, a1, a0
 ; RV64-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>