diff --git a/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll b/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvp/vector-maxmin.ll
@@ -0,0 +1,989 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=RV64
+
+; smax8
+
+define i32 @smaxv4i8_1(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv4i8_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a2, a0, a1
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i8_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp slt <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp2, <4 x i8> %tmp1
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i32 @smaxv4i8_2(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv4i8_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a2, a0, a1
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i8_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp sle <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp2, <4 x i8> %tmp1
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i32 @smaxv4i8_3(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv4i8_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a2, a1, a0
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i8_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp sgt <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp1, <4 x i8> %tmp2
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i32 @smaxv4i8_4(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv4i8_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a2, a1, a0
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i8_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp sge <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp1, <4 x i8> %tmp2
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i64 @smaxv8i8_1(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv8i8_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a4, a0, a2
+; RV32-NEXT:    scmplt8 a5, a1, a3
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv8i8_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp slt <8 x i8> %tmp1, %tmp2
+  %select = select <8x i1> %cmp, <8 x i8> %tmp2, <8 x i8> %tmp1
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+define i64 @smaxv8i8_2(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv8i8_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a4, a0, a2
+; RV32-NEXT:    scmple8 a5, a1, a3
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv8i8_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp sle <8 x i8> %tmp1, %tmp2
+  %select = select <8 x i1> %cmp, <8 x i8> %tmp2, <8 x i8> %tmp1
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+define i64 @smaxv8i8_3(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv8i8_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a4, a2, a0
+; RV32-NEXT:    scmplt8 a5, a3, a1
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv8i8_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp sgt <8 x i8> %tmp1, %tmp2
+  %select = select <8 x i1> %cmp, <8 x i8> %tmp1, <8 x i8> %tmp2
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+define i64 @smaxv8i8_4(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv8i8_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a4, a2, a0
+; RV32-NEXT:    scmple8 a5, a3, a1
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv8i8_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp sge <8 x i8> %tmp1, %tmp2
+  %select = select <8 x i1> %cmp, <8 x i8> %tmp1, <8 x i8> %tmp2
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+; smin8
+
+define i32 @sminv4i8_1(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv4i8_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a2, a0, a1
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i8_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp slt <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp1, <4 x i8> %tmp2
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i32 @sminv4i8_2(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv4i8_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a2, a0, a1
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i8_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp sle <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp1, <4 x i8> %tmp2
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i32 @sminv4i8_3(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv4i8_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a2, a1, a0
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i8_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp sgt <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp2, <4 x i8> %tmp1
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i32 @sminv4i8_4(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv4i8_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a2, a1, a0
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i8_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %cmp = icmp sge <4 x i8> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i8> %tmp2, <4 x i8> %tmp1
+  %res = bitcast <4 x i8> %select to i32
+  ret i32 %res
+}
+
+define i64 @sminv8i8_1(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv8i8_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a4, a0, a2
+; RV32-NEXT:    scmplt8 a5, a1, a3
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv8i8_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp slt <8 x i8> %tmp1, %tmp2
+  %select = select <8x i1> %cmp, <8 x i8> %tmp1, <8 x i8> %tmp2
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+define i64 @sminv8i8_2(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv8i8_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a4, a0, a2
+; RV32-NEXT:    scmple8 a5, a1, a3
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv8i8_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp sle <8 x i8> %tmp1, %tmp2
+  %select = select <8 x i1> %cmp, <8 x i8> %tmp1, <8 x i8> %tmp2
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+define i64 @sminv8i8_3(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv8i8_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt8 a4, a2, a0
+; RV32-NEXT:    scmplt8 a5, a3, a1
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv8i8_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt8 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp sgt <8 x i8> %tmp1, %tmp2
+  %select = select <8 x i1> %cmp, <8 x i8> %tmp2, <8 x i8> %tmp1
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+define i64 @sminv8i8_4(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv8i8_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple8 a4, a2, a0
+; RV32-NEXT:    scmple8 a5, a3, a1
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv8i8_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple8 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %cmp = icmp sge <8 x i8> %tmp1, %tmp2
+  %select = select <8 x i1> %cmp, <8 x i8> %tmp2, <8 x i8> %tmp1
+  %res = bitcast <8 x i8> %select to i64
+  ret i64 %res
+}
+
+; smax16
+
+define i32 @smaxv2i16_1(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv2i16_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a2, a0, a1
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv2i16_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp slt <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp2, <2 x i16> %tmp1
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i32 @smaxv2i16_2(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv2i16_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a2, a0, a1
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv2i16_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp sle <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp2, <2 x i16> %tmp1
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i32 @smaxv2i16_3(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv2i16_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a2, a1, a0
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv2i16_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp sgt <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp1, <2 x i16> %tmp2
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i32 @smaxv2i16_4(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: smaxv2i16_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a2, a1, a0
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv2i16_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp sge <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp1, <2 x i16> %tmp2
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i64 @smaxv4i16_1(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv4i16_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a4, a0, a2
+; RV32-NEXT:    scmplt16 a5, a1, a3
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i16_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp slt <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp2, <4 x i16> %tmp1
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+define i64 @smaxv4i16_2(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv4i16_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a4, a0, a2
+; RV32-NEXT:    scmple16 a5, a1, a3
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i16_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a0, a1
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp sle <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp2, <4 x i16> %tmp1
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+define i64 @smaxv4i16_3(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv4i16_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a4, a2, a0
+; RV32-NEXT:    scmplt16 a5, a3, a1
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i16_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp sgt <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp1, <4 x i16> %tmp2
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+define i64 @smaxv4i16_4(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: smaxv4i16_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a4, a2, a0
+; RV32-NEXT:    scmple16 a5, a3, a1
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: smaxv4i16_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a1, a0
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp sge <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp1, <4 x i16> %tmp2
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+; smin16
+
+define i32 @sminv2i16_1(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv2i16_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a2, a0, a1
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv2i16_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp slt <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp1, <2 x i16> %tmp2
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i32 @sminv2i16_2(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv2i16_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a2, a0, a1
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv2i16_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp sle <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp1, <2 x i16> %tmp2
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i32 @sminv2i16_3(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv2i16_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a2, a1, a0
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv2i16_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp sgt <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp2, <2 x i16> %tmp1
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i32 @sminv2i16_4(i32 %a, i32 %b) nounwind {
+; RV32-LABEL: sminv2i16_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a2, a1, a0
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    addi a3, zero, -1
+; RV32-NEXT:    xor a2, a2, a3
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv2i16_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %cmp = icmp sge <2 x i16> %tmp1, %tmp2
+  %select = select <2 x i1> %cmp, <2 x i16> %tmp2, <2 x i16> %tmp1
+  %res = bitcast <2 x i16> %select to i32
+  ret i32 %res
+}
+
+define i64 @sminv4i16_1(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv4i16_1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a4, a0, a2
+; RV32-NEXT:    scmplt16 a5, a1, a3
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i16_1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp slt <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp1, <4 x i16> %tmp2
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+define i64 @sminv4i16_2(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv4i16_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a4, a0, a2
+; RV32-NEXT:    scmple16 a5, a1, a3
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    or a1, a1, a3
+; RV32-NEXT:    and a0, a0, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a2, a2, a3
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i16_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a0, a1
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp sle <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp1, <4 x i16> %tmp2
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+define i64 @sminv4i16_3(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv4i16_3:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmplt16 a4, a2, a0
+; RV32-NEXT:    scmplt16 a5, a3, a1
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i16_3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmplt16 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp sgt <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp2, <4 x i16> %tmp1
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}
+
+define i64 @sminv4i16_4(i64 %a, i64 %b) nounwind {
+; RV32-LABEL: sminv4i16_4:
+; RV32:       # %bb.0:
+; RV32-NEXT:    scmple16 a4, a2, a0
+; RV32-NEXT:    scmple16 a5, a3, a1
+; RV32-NEXT:    and a3, a3, a5
+; RV32-NEXT:    addi a6, zero, -1
+; RV32-NEXT:    xor a5, a5, a6
+; RV32-NEXT:    and a1, a1, a5
+; RV32-NEXT:    or a1, a3, a1
+; RV32-NEXT:    and a2, a2, a4
+; RV32-NEXT:    xor a3, a4, a6
+; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sminv4i16_4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    scmple16 a2, a1, a0
+; RV64-NEXT:    and a1, a1, a2
+; RV64-NEXT:    addi a3, zero, -1
+; RV64-NEXT:    xor a2, a2, a3
+; RV64-NEXT:    and a0, a0, a2
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %cmp = icmp sge <4 x i16> %tmp1, %tmp2
+  %select = select <4 x i1> %cmp, <4 x i16> %tmp2, <4 x i16> %tmp1
+  %res = bitcast <4 x i16> %select to i64
+  ret i64 %res
+}