diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
    CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
@@ -47,6 +47,18 @@
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -100,6 +100,18 @@
   Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
   Builder.defineMacro("__compare_and_swaplp",
                       "__builtin_ppc_compare_and_swaplp");
+  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+  Builder.defineMacro("__tw", "__builtin_ppc_tw");
+  Builder.defineMacro("__trap", "__builtin_ppc_trap");
+  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3261,6 +3261,8 @@
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_ppc_tdw:
+  case PPC::BI__builtin_ppc_trapd:
     return true;
   }
   return false;
@@ -3341,6 +3343,10 @@
      return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_ppc_tw:
+    return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
+  case PPC::BI__builtin_ppc_tdw:
+    return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
@@ -0,0 +1,120 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+double test_fcfid(double a) {
+  // CHECK-LABEL: test_fcfid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfid(double %a)
+  return __builtin_ppc_fcfid(a);
+}
+
+double test_xl_fcfid(double a) {
+  // CHECK-LABEL: test_xl_fcfid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfid(double %a)
+  return __fcfid(a);
+}
+
+double test_fcfud(double a) {
+  // CHECK-LABEL: test_fcfud
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfud(double %a)
+  return __builtin_ppc_fcfud(a);
+}
+
+double test_xl_fcfud(double a) {
+  // CHECK-LABEL: test_xl_fcfud
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fcfud(double %a)
+  return __fcfud(a);
+}
+
+double test_fctid(double a) {
+  // CHECK-LABEL: test_fctid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctid(double %a)
+  return __builtin_ppc_fctid(a);
+}
+
+double test_xl_fctid(double a) {
+  // CHECK-LABEL: test_xl_fctid
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctid(double %a)
+  return __fctid(a);
+}
+
+double test_fctidz(double a) {
+  // CHECK-LABEL: test_fctidz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctidz(double %a)
+  return __builtin_ppc_fctidz(a);
+}
+
+double test_xl_fctidz(double a) {
+  // CHECK-LABEL: test_xl_fctidz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctidz(double %a)
+  return __fctidz(a);
+}
+
+double test_fctiw(double a) {
+  // CHECK-LABEL: test_fctiw
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiw(double %a)
+  return __builtin_ppc_fctiw(a);
+}
+
+double test_xl_fctiw(double a) {
+  // CHECK-LABEL: test_xl_fctiw
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiw(double %a)
+  return __fctiw(a);
+}
+
+double test_fctiwz(double a) {
+  // CHECK-LABEL: test_fctiwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiwz(double %a)
+  return __builtin_ppc_fctiwz(a);
+}
+
+double test_xl_fctiwz(double a) {
+  // CHECK-LABEL: test_xl_fctiwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctiwz(double %a)
+  return __fctiwz(a);
+}
+
+double test_fctudz(double a) {
+  // CHECK-LABEL: test_fctudz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctudz(double %a)
+  return __builtin_ppc_fctudz(a);
+}
+
+double test_xl_fctudz(double a) {
+  // CHECK-LABEL: test_xl_fctudz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctudz(double %a)
+  return __fctudz(a);
+}
+
+double test_fctuwz(double a) {
+  // CHECK-LABEL: test_fctuwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctuwz(double %a)
+  return __builtin_ppc_fctuwz(a);
+}
+
+double test_xl_fctuwz(double a) {
+  // CHECK-LABEL: test_xl_fctuwz
+  // CHECK-NEXT: entry:
+  // CHECK: double @llvm.ppc.fctuwz(double %a)
+  return __fctuwz(a);
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,19 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN:   -Wall -Werror -verify %s
+
+long long lla, llb;
+int ia, ib;
+
+void test_trap(void) {
+#ifdef __PPC64__
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+#endif
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c b/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s -check-prefixes=CHECK
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64,CHECK
+
+long long lla, llb;
+double da;
+int ia, ib;
+
+#ifdef __ppc64__
+// tdw
+void test_xl_tdw(void) {
+// CHECK64: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 1)
+
+  __tdw(lla, llb, 1);
+}
+
+void test_tdw(void) {
+// CHECK64: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 13)
+
+  __builtin_ppc_tdw(lla, llb, 13);
+}
+#endif
+
+// td
+void test_tw(void) {
+// CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
+
+  __builtin_ppc_tw(ia, ib, 1);
+}
+
+void test_xl_tw(void) {
+// CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
+
+  __tw(ia, ib, 1);
+}
+
+// trap
+void test_trap(void) {
+// CHECK: void @llvm.ppc.trap(i32 %0)
+  __builtin_ppc_trap(ia);
+}
+
+void test_xl_trap(void) {
+// CHECK: void @llvm.ppc.trap(i32 %0)
+  __trap(ia);
+}
+
+#ifdef __PPC64__
+// trapd
+void test_trapd(void) {
+// CHECK64: void @llvm.ppc.trapd(i64 %conv)
+  __builtin_ppc_trapd(da);
+}
+
+void test_xl_trapd(void) {
+// CHECK64: void @llvm.ppc.trapd(i64 %conv)
+  __trapd(da);
+}
+#endif
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -112,9 +112,45 @@
       : GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
 
+  // Intrinsics defined to maintain XL compatibility
+  def int_ppc_tdw
+      : GCCBuiltin<"__builtin_ppc_tdw">,
+        Intrinsic <[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
+  def int_ppc_tw
+      : GCCBuiltin<"__builtin_ppc_tw">,
+        Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
+  def int_ppc_trapd
+      : GCCBuiltin<"__builtin_ppc_trapd">,
+        Intrinsic <[], [llvm_i64_ty], []>;
+  def int_ppc_trap
+      : GCCBuiltin<"__builtin_ppc_trap">,
+        Intrinsic <[], [llvm_i32_ty], []>;
+  def int_ppc_fcfid
+      : GCCBuiltin<"__builtin_ppc_fcfid">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fcfud
+      : GCCBuiltin<"__builtin_ppc_fcfud">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctid
+      : GCCBuiltin<"__builtin_ppc_fctid">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctidz
+      : GCCBuiltin<"__builtin_ppc_fctidz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctiw
+      : GCCBuiltin<"__builtin_ppc_fctiw">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctiwz
+      : GCCBuiltin<"__builtin_ppc_fctiwz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctudz
+      : GCCBuiltin<"__builtin_ppc_fctudz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fctuwz
+      : GCCBuiltin<"__builtin_ppc_fctuwz">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
 }
 
-
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
   class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1720,3 +1720,17 @@
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
 
 } // IsISA3_0
+
+// tdne
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 3),
+          (TD 24, $A, $B)>;
+// tweq, but we can use tdeq instead
+// as XL produces a tweq <regA>, <regA>.
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31),
+          (TD 4, $A, $B)>;
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
+          (TD $IMM, $A, $B)>;
+
+// trapd
+def : Pat<(int_ppc_trapd g8rc:$A),
+          (TDI 24, $A, 0)>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2230,6 +2230,15 @@
 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
                  "td $to, $rA, $rB", IIC_IntTrapD, []>;
 
+def : InstAlias<"tdlle $rA, $rB", (TD 6, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdlge $rA, $rB", (TD 5, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdge $rA, $rB", (TD 12, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdle $rA, $rB", (TD 20, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"twlle $rA, $rB", (TW 6, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twlge $rA, $rB", (TW 5, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twge $rA, $rB", (TW 12, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twle $rA, $rB", (TW 20, gprc:$rA, gprc:$rB)>;
+
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.
 //
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2836,3 +2836,32 @@
     def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
               (VINSD $vDi, !mul(i, 8), $rA)>;
 }
+
+// XL Compatibility
+// twne
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, 3),
+          (TW 24, $A, $B)>;
+// tweq
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, 31),
+          (TW 4, $A, $B)>;
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
+          (TW $IMM, $A, $B)>;
+def : Pat<(int_ppc_trap gprc:$A),
+          (TWI 24, $A, 0)>;
+
+def : Pat<(int_ppc_fcfid f64:$A),
+        (XSCVSXDDP $A)>;
+def : Pat<(int_ppc_fcfud f64:$A),
+        (XSCVUXDDP $A)>;
+def : Pat<(int_ppc_fctid f64:$A),
+        (FCTID $A)>;
+def : Pat<(int_ppc_fctidz f64:$A),
+        (XSCVDPSXDS $A)>;
+def : Pat<(int_ppc_fctiw f64:$A),
+        (FCTIW $A)>;
+def : Pat<(int_ppc_fctiwz f64:$A),
+        (XSCVDPSXWS $A)>;
+def : Pat<(int_ppc_fctudz f64:$A),
+        (XSCVDPUXDS $A)>;
+def : Pat<(int_ppc_fctuwz f64:$A),
+        (XSCVDPUXWS $A)>;
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+declare double @llvm.ppc.fcfid(double %a)
+define dso_local double @test_fcfid(double %a) {
+; CHECK-64-LABEL: test_fcfid:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    xscvsxddp 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fcfid:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    xscvsxddp 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fcfid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fcfud(double %a)
+define dso_local double @test_fcfud(double %a) {
+; CHECK-64-LABEL: test_fcfud:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    xscvuxddp 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fcfud:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    xscvuxddp 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fcfud(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctid(double %a)
+define dso_local double @test_fctid(double %a) {
+; CHECK-64-LABEL: test_fctid:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctid:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctidz(double %a)
+define dso_local double @test_fctidz(double %a) {
+; CHECK-64-LABEL: test_fctidz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctidz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctiw(double %a)
+define dso_local double @test_fctiw(double %a) {
+; CHECK-64-LABEL: test_fctiw:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctiw:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctiwz(double %a)
+define dso_local double @test_fctiwz(double %a) {
+; CHECK-64-LABEL: test_fctiwz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctiwz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctudz(double %a)
+define dso_local double @test_fctudz(double %a) {
+; CHECK-64-LABEL: test_fctudz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctudz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
+
+declare double @llvm.ppc.fctuwz(double %a)
+define dso_local double @test_fctuwz(double %a) {
+; CHECK-64-LABEL: test_fctuwz:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    fctid 1, 1
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_fctuwz:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    fctid 1, 1
+; CHECK-32-NEXT:    blr
+  %1 = call double @llvm.ppc.fctid(double %a)
+  ret double %1
+}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -0,0 +1,128 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+; tdw
+declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
+define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__tdwllt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwllt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdllt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__tdweq(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdeq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__tdwlge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 5, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__tdwlle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 6, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__tdwgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__tdwge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 12, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__tdwlt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdlt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__tdwle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 20, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__tdwne24(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwne24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdne 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tdweq31(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdeq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw_no_match:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 13, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
+  ret void
+}
+
+; trapd
+declare void @llvm.ppc.trapd(i64 %a)
+define dso_local void @test__trapd(i64 %a) {
+; CHECK-LABEL: test__trapd:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdnei 3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.trapd(i64 %a)
+  ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twllt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twne 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tweq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 5, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 6, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twgt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 12, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twlt 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 20, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twne 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tweq 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tw 13, 3, 4
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twnei 3, 0
+; CHECK-NEXT:    blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}