diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -340,8 +340,8 @@
     llvm_unreachable("function must be called with COPY-like instruction");
   }
 
-  assert(Def.getSubReg() == 0 &&
-         "Should not have subregister defs in machine SSA phase");
+  unsigned SubIdx = Def.getSubReg();
+  DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
   DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
   return DefinedLanes;
 }
@@ -406,9 +406,9 @@
   if (DefMI.isImplicitDef() || Def.isDead())
     return LaneBitmask::getNone();
 
-  assert(Def.getSubReg() == 0 &&
-         "Should not have subregister defs in machine SSA phase");
-  return MRI->getMaxLaneMaskForVReg(Reg);
+  unsigned SubReg = Def.getSubReg();
+  return SubReg != 0 ? TRI->getSubRegIndexLaneMask(SubReg)
+                     : MRI->getMaxLaneMaskForVReg(Reg);
 }
 
 LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
diff --git a/llvm/test/CodeGen/PowerPC/detect-dead-lanes-subreg-assertion.ll b/llvm/test/CodeGen/PowerPC/detect-dead-lanes-subreg-assertion.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/detect-dead-lanes-subreg-assertion.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s
+
+declare i64 @strlen() local_unnamed_addr
+
+define dso_local fastcc void @check_format_info_main() unnamed_addr {
+; CHECK-LABEL: check_format_info_main:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    b .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.end40
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    bl strlen
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    addi 5, 3, 1
+; CHECK-NEXT:    stb 4, 0(3)
+; CHECK-NEXT:    extsw 5, 5
+; CHECK-NEXT:    stb 4, 0(5)
+; CHECK-NEXT:  .LBB0_2: # %if.then32
+entry:
+  switch i8 undef, label %if.end40 [
+    i8 0, label %if.then32
+  ]
+
+if.then32:                                        ; preds = %entry
+  unreachable
+
+if.end40:                                         ; preds = %entry
+  %call413 = call i64 @strlen()
+  %sext1679 = shl i64 %call413, 32
+  %idxprom418 = ashr exact i64 %sext1679, 32
+  %arrayidx419 = getelementptr inbounds [256 x i8], [256 x i8]* null, i64 0, i64 %idxprom418
+  store i8 0, i8* %arrayidx419, align 1
+  %sext1680 = add i64 %sext1679, 4294967296
+  %idxprom420 = ashr exact i64 %sext1680, 32
+  %arrayidx421 = getelementptr inbounds [256 x i8], [256 x i8]* null, i64 0, i64 %idxprom420
+  store i8 0, i8* %arrayidx421, align 1
+  unreachable
+}