diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43866,6 +43866,10 @@ assert(N->getOperand(1).getValueType() == MVT::i8 && "Unexpected shift amount type"); + // (shift undef, X) -> 0 + if (N0.isUndef()) + return DAG.getConstant(0, SDLoc(N), VT); + // Out of range logical bit shifts are guaranteed to be zero. // Out of range arithmetic bit shifts splat the sign bit. unsigned ShiftVal = N->getConstantOperandVal(1); diff --git a/llvm/test/CodeGen/X86/vec_shift5.ll b/llvm/test/CodeGen/X86/vec_shift5.ll --- a/llvm/test/CodeGen/X86/vec_shift5.ll +++ b/llvm/test/CodeGen/X86/vec_shift5.ll @@ -176,16 +176,16 @@ ; X86-LABEL: test17: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: pslld $6, %xmm0 -; X86-NEXT: movdqa %xmm0, (%eax) -; X86-NEXT: pslld $7, %xmm0 +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, (%eax) +; X86-NEXT: xorps %xmm0, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: test17: ; X64: # %bb.0: -; X64-NEXT: pslld $6, %xmm0 -; X64-NEXT: movdqa %xmm0, (%rdi) -; X64-NEXT: pslld $7, %xmm0 +; X64-NEXT: xorps %xmm0, %xmm0 +; X64-NEXT: movaps %xmm0, (%rdi) +; X64-NEXT: xorps %xmm0, %xmm0 ; X64-NEXT: retq %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 6) store <4 x i32> %a, <4 x i32>* %dummy @@ -197,16 +197,16 @@ ; X86-LABEL: test18: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: pslld $3, %xmm0 -; X86-NEXT: movdqa %xmm0, (%eax) -; X86-NEXT: pslld $1, %xmm0 +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, (%eax) +; X86-NEXT: xorps %xmm0, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: test18: ; X64: # %bb.0: -; X64-NEXT: pslld $3, %xmm0 -; X64-NEXT: movdqa %xmm0, (%rdi) -; X64-NEXT: pslld $1, %xmm0 +; X64-NEXT: xorps %xmm0, %xmm0 +; X64-NEXT: movaps %xmm0, (%rdi) +; X64-NEXT: xorps %xmm0, %xmm0 ; X64-NEXT: retq %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 3) store <4 x i32> %a, <4 x i32>* %dummy