Index: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h =================================================================== --- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h +++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h @@ -27,7 +27,7 @@ /// MCSubtargetInfo - Generic base class for all target subtargets. /// class MCSubtargetInfo { - std::string TargetTriple; // Target triple + Triple TargetTriple; // Target triple std::string CPU; // CPU being targeted. ArrayRef ProcFeatures; // Processor feature list ArrayRef ProcDesc; // Processor descriptions @@ -45,20 +45,17 @@ FeatureBitset FeatureBits; // Feature bits for current CPU + FS public: - void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, + void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef PF, ArrayRef PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, - const MCReadAdvanceEntry *RA, - const InstrStage *IS, + const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP); /// getTargetTriple - Return the target triple string. - StringRef getTargetTriple() const { - return TargetTriple; - } + const Triple &getTargetTriple() const { return TargetTriple; } /// getCPU - Return the CPU string. StringRef getCPU() const { Index: llvm/trunk/include/llvm/Support/TargetRegistry.h =================================================================== --- llvm/trunk/include/llvm/Support/TargetRegistry.h +++ llvm/trunk/include/llvm/Support/TargetRegistry.h @@ -98,7 +98,7 @@ typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, + typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT, StringRef CPU, StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)( @@ -334,18 +334,18 @@ /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// - /// \param Triple This argument is used to determine the target machine + /// \param TheTriple This argument is used to determine the target machine /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. /// \param CPU This specifies the name of the target CPU. /// \param Features This specifies the string representation of the /// additional target features. - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, + MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const { if (!MCSubtargetInfoCtorFn) return nullptr; - return MCSubtargetInfoCtorFn(Triple, CPU, Features); + return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features); } /// createTargetMachine - Create a target specific machine implementation @@ -1056,7 +1056,7 @@ } private: - static MCSubtargetInfo *Allocator(StringRef /*TT*/, StringRef /*CPU*/, + static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/, StringRef /*FS*/) { return new MCSubtargetInfoImpl(); } Index: llvm/trunk/lib/MC/MCSubtargetInfo.cpp =================================================================== --- llvm/trunk/lib/MC/MCSubtargetInfo.cpp +++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp @@ -34,17 +34,12 @@ CPUSchedModel = MCSchedModel::GetDefaultSchedModel(); } -void -MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, - ArrayRef PF, - ArrayRef PD, - const SubtargetInfoKV *ProcSched, - const MCWriteProcResEntry *WPR, - const MCWriteLatencyEntry *WL, - const MCReadAdvanceEntry *RA, - const InstrStage *IS, - const unsigned *OC, - const unsigned *FP) { +void MCSubtargetInfo::InitMCSubtargetInfo( + const Triple &TT, StringRef C, StringRef FS, + ArrayRef PF, ArrayRef PD, + const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, + const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, + const InstrStage *IS, const unsigned *OC, const unsigned *FP) { TargetTriple = TT; CPU = C; ProcFeatures = PF; Index: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h @@ -29,6 +29,7 @@ namespace llvm { class GlobalValue; class StringRef; +class Triple; class AArch64Subtarget : public AArch64GenSubtargetInfo { protected: @@ -71,7 +72,7 @@ public: /// This constructor initializes the data members to match that /// of the specified triple. - AArch64Subtarget(const std::string &TT, const std::string &CPU, + AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian); Index: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp @@ -42,14 +42,12 @@ return *this; } -AArch64Subtarget::AArch64Subtarget(const std::string &TT, - const std::string &CPU, +AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian) : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), - HasV8_1aOps(false), - HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), - HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), + HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false), + HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {} Index: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -156,7 +156,8 @@ // creation will depend on the TM and the code generation flags on the // function that reside in TargetOptions. resetTargetOptions(F); - I = llvm::make_unique(TargetTriple, CPU, FS, *this, isLittle); + I = llvm::make_unique(Triple(TargetTriple), CPU, FS, + *this, isLittle); } return I.get(); } Index: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -41,7 +41,7 @@ } static MCSubtargetInfo * -createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { +createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); if (CPU.empty()) Index: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp @@ -564,7 +564,7 @@ // anyhow. // FIXME: For ifunc related functions we could iterate over and look // for a feature string that doesn't match the default one. - StringRef TT = TM.getTargetTriple(); + const Triple TT(TM.getTargetTriple()); StringRef CPU = TM.getTargetCPU(); StringRef FS = TM.getTargetFeatureString(); std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.h =================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h @@ -237,8 +237,8 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle); + ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + const ARMBaseTargetMachine &TM, bool IsLittle); /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp @@ -106,7 +106,7 @@ return new ARMFrameLowering(STI); } -ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, +ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle) : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), @@ -187,8 +187,7 @@ // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. - std::string ArchFS = - ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString); + std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString); if (!FS.empty()) { if (!ArchFS.empty()) ArchFS = (Twine(ArchFS) + "," + FS).str(); Index: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp @@ -180,7 +180,7 @@ CPU, FS, Options, RM, CM, OL), TargetABI(computeTargetABI(Triple(TT), CPU, Options)), TLOF(createTLOF(Triple(getTargetTriple()))), - Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { + Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) { // Default to triple-appropriate float ABI if (Options.FloatABIType == FloatABI::Default) @@ -221,7 +221,8 @@ // creation will depend on the TM and the code generation flags on the // function that reside in TargetOptions. resetTargetOptions(F); - I = llvm::make_unique(TargetTriple, CPU, FS, *this, isLittle); + I = llvm::make_unique(Triple(TargetTriple), CPU, FS, *this, + isLittle); } return I.get(); } Index: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h =================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -24,7 +24,7 @@ bool IsLittleEndian; // Big or little endian. public: ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle) - : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT.str(), "", "")), + : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), isThumbMode(TT.getArchName().startswith("thumb")), IsLittleEndian(IsLittle) {} Index: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h =================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -40,12 +40,12 @@ extern Target TheARMBETarget, TheThumbBETarget; namespace ARM_MC { - std::string ParseARMTriple(StringRef TT, StringRef CPU); +std::string ParseARMTriple(const Triple &TT, StringRef CPU); - /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. - /// do not need to go through TargetRegistry. - MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS); +/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. +/// do not need to go through TargetRegistry. +MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, + StringRef FS); } MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); Index: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -130,16 +130,13 @@ #define GET_SUBTARGETINFO_MC_DESC #include "ARMGenSubtargetInfo.inc" - -std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { - Triple triple(TT); - - bool isThumb = triple.getArch() == Triple::thumb || - triple.getArch() == Triple::thumbeb; +std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { + bool isThumb = + TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb; bool NoCPU = CPU == "generic" || CPU.empty(); std::string ARMArchFeature; - switch (triple.getSubArch()) { + switch (TT.getSubArch()) { default: llvm_unreachable("invalid sub-architecture for ARM"); case Triple::ARMSubArch_v8: @@ -240,7 +237,7 @@ ARMArchFeature += ",+thumb-mode"; } - if (triple.isOSNaCl()) { + if (TT.isOSNaCl()) { if (ARMArchFeature.empty()) ARMArchFeature = "+nacl-trap"; else @@ -250,8 +247,8 @@ return ARMArchFeature; } -MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, + StringRef CPU, StringRef FS) { std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); if (!FS.empty()) { if (!ArchFS.empty()) Index: llvm/trunk/lib/Target/BPF/BPFSubtarget.h =================================================================== --- llvm/trunk/lib/Target/BPF/BPFSubtarget.h +++ llvm/trunk/lib/Target/BPF/BPFSubtarget.h @@ -38,8 +38,8 @@ public: // This constructor initializes the data members to match that // of the specified triple. - BPFSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, const TargetMachine &TM); + BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + const TargetMachine &TM); // ParseSubtargetFeatures - Parses features string setting specified // subtarget options. Definition of function is auto generated by tblgen. Index: llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp +++ llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp @@ -25,7 +25,7 @@ void BPFSubtarget::anchor() {} -BPFSubtarget::BPFSubtarget(const std::string &TT, const std::string &CPU, +BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} Index: llvm/trunk/lib/Target/BPF/BPFTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/BPF/BPFTargetMachine.cpp +++ llvm/trunk/lib/Target/BPF/BPFTargetMachine.cpp @@ -43,7 +43,7 @@ : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(Triple(TT), CPU, FS, *this) { initAsmInfo(); } namespace { Index: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -46,8 +46,8 @@ return X; } -static MCSubtargetInfo *createBPFMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT, + StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitBPFMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h +++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h @@ -52,7 +52,7 @@ InstrItineraryData InstrItins; public: - HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, + HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM); /// getInstrItins - Return the instruction itineraries based on subtarget Index: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -70,8 +70,8 @@ return *this; } -HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, - const TargetMachine &TM) +HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, + StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() { Index: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -76,7 +76,7 @@ : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(Triple(TT), CPU, FS, *this) { initAsmInfo(); } Index: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -48,7 +48,7 @@ } static MCSubtargetInfo * -createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { +createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitHexagonMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -43,8 +43,8 @@ return X; } -static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitMSP430MCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h @@ -41,7 +41,7 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - MSP430Subtarget(const std::string &TT, const std::string &CPU, + MSP430Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM); MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); Index: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp @@ -31,7 +31,7 @@ return *this; } -MSP430Subtarget::MSP430Subtarget(const std::string &TT, const std::string &CPU, +MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), Index: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -34,7 +34,7 @@ Options, RM, CM, OL), TLOF(make_unique()), // FIXME: Check DataLayout string. - Subtarget(TT, CPU, FS, *this) { + Subtarget(Triple(TT), CPU, FS, *this) { initAsmInfo(); } Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h =================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -59,7 +59,7 @@ bool IsLittleEndian, bool Is64Bit); namespace MIPS_MC { -StringRef selectMipsCPU(StringRef TT, StringRef CPU); +StringRef selectMipsCPU(const Triple &TT, StringRef CPU); } } // End llvm namespace Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -43,11 +43,9 @@ /// Select the Mips CPU for the given triple and cpu name. /// FIXME: Merge with the copy in MipsSubtarget.cpp -StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) { +StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { if (CPU.empty() || CPU == "generic") { - Triple TheTriple(TT); - if (TheTriple.getArch() == Triple::mips || - TheTriple.getArch() == Triple::mipsel) + if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel) CPU = "mips32"; else CPU = "mips64"; @@ -67,8 +65,8 @@ return X; } -static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, + StringRef CPU, StringRef FS) { CPU = MIPS_MC::selectMipsCPU(TT, CPU); MCSubtargetInfo *X = new MCSubtargetInfo(); InitMipsMCSubtargetInfo(X, TT, CPU, FS); Index: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp @@ -694,9 +694,8 @@ // clean anyhow. // FIXME: For ifunc related functions we could iterate over and look // for a feature string that doesn't match the default one. - StringRef TT = TM.getTargetTriple(); - StringRef CPU = - MIPS_MC::selectMipsCPU(TM.getTargetTriple(), TM.getTargetCPU()); + const Triple TT(TM.getTargetTriple()); + StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU()); StringRef FS = TM.getTargetFeatureString(); const MipsTargetMachine &MTM = static_cast(TM); const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); Index: llvm/trunk/lib/Target/Mips/MipsSubtarget.h =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h @@ -161,9 +161,8 @@ /// This constructor initializes the data members to match that /// of the specified triple. - MipsSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool little, - const MipsTargetMachine &TM); + MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + bool little, const MipsTargetMachine &TM); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. Index: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp @@ -59,7 +59,7 @@ void MipsSubtarget::anchor() { } -MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, +MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, bool little, const MipsTargetMachine &TM) : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), @@ -141,7 +141,8 @@ MipsSubtarget & MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { - std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); + std::string CPUName = + MIPS_MC::selectMipsCPU(Triple(TM.getTargetTriple()), CPU); // Parse features string. ParseSubtargetFeatures(CPUName, FS); Index: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp @@ -92,11 +92,14 @@ CPU, FS, Options, RM, CM, OL), isLittle(isLittle), TLOF(make_unique()), ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)), - Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), - NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", + Subtarget(nullptr), + DefaultSubtarget(Triple(TT), CPU, FS, isLittle, *this), + NoMips16Subtarget(Triple(TT), CPU, + FS.empty() ? "-mips16" : FS.str() + ",-mips16", isLittle, *this), - Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", - isLittle, *this) { + Mips16Subtarget(Triple(TT), CPU, + FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle, + *this) { Subtarget = &DefaultSubtarget; initAsmInfo(); } @@ -157,7 +160,8 @@ // creation will depend on the TM and the code generation flags on the // function that reside in TargetOptions. resetTargetOptions(F); - I = llvm::make_unique(TargetTriple, CPU, FS, isLittle, *this); + I = llvm::make_unique(Triple(TargetTriple), CPU, FS, + isLittle, *this); } return I.get(); } Index: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -45,7 +45,7 @@ } static MCSubtargetInfo * -createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { +createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitNVPTXMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -808,7 +808,7 @@ // Construct a default subtarget off of the TargetMachine defaults. The // rest of NVPTX isn't friendly to change subtargets per function and // so the default TargetMachine will have all of the options. - StringRef TT = TM.getTargetTriple(); + const Triple TT(TM.getTargetTriple()); StringRef CPU = TM.getTargetCPU(); StringRef FS = TM.getTargetFeatureString(); const NVPTXTargetMachine &NTM = static_cast(TM); Index: llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h =================================================================== --- llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h +++ llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h @@ -52,7 +52,7 @@ /// This constructor initializes the data members to match that /// of the specified module. /// - NVPTXSubtarget(const std::string &TT, const std::string &CPU, + NVPTXSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const NVPTXTargetMachine &TM); const TargetFrameLowering *getFrameLowering() const override { Index: llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp +++ llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp @@ -43,7 +43,7 @@ return *this; } -NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, +NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const NVPTXTargetMachine &TM) : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), Index: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -91,7 +91,7 @@ : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, CM, OL), is64bit(is64bit), TLOF(make_unique()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(Triple(TT), CPU, FS, *this) { if (Triple(TT).getOS() == Triple::NVCL) drvInterface = NVPTX::NVCL; else Index: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -63,8 +63,8 @@ return X; } -static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT, + StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitPPCMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h @@ -135,8 +135,8 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - PPCSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, const PPCTargetMachine &TM); + PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + const PPCTargetMachine &TM); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. Index: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp @@ -47,7 +47,7 @@ return *this; } -PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, +PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM) : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), IsPPC64(TargetTriple.getArch() == Triple::ppc64 || Index: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -217,7 +217,7 @@ // function that reside in TargetOptions. resetTargetOptions(F); I = llvm::make_unique( - TargetTriple, CPU, + Triple(TargetTriple), CPU, // FIXME: It would be good to have the subtarget additions here // not necessary. Anything that turns them on/off (overrides) ends // up being put at the end of the feature string, but the defaults Index: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h =================================================================== --- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h +++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h @@ -85,9 +85,10 @@ Triple TargetTriple; public: - AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM); - AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU, - StringRef FS); + AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS, + TargetMachine &TM); + AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT, + StringRef GPU, StringRef FS); const AMDGPUFrameLowering *getFrameLowering() const override { return &FrameLowering; Index: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp +++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp @@ -32,8 +32,8 @@ #include "AMDGPUGenSubtargetInfo.inc" AMDGPUSubtarget & -AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU, - StringRef FS) { +AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT, + StringRef GPU, StringRef FS) { // Determine default and user-specified characteristics // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be // enabled, but some instructions do not respect them and they run at the @@ -46,7 +46,7 @@ SmallString<256> FullFS("+promote-alloca,+fp64-denormals,"); FullFS += FS; - if (GPU == "" && Triple(TT).getArch() == Triple::amdgcn) + if (GPU == "" && TT.getArch() == Triple::amdgcn) GPU = "SI"; ParseSubtargetFeatures(GPU, FullFS); @@ -61,7 +61,7 @@ return *this; } -AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, +AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, TargetMachine &TM) : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), DumpCode(false), R600ALUInst(false), HasVertexCache(false), @@ -70,9 +70,8 @@ CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0), - EnableVGPRSpilling(false), SGPRInitBug(false), - IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), - LDSBankCount(0), + EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false), + GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0), FrameLowering(TargetFrameLowering::StackGrowsUp, 64 * 16, // Maximum stack alignment (long16) 0), Index: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp +++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -73,8 +73,8 @@ CodeGenOpt::Level OptLevel) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, OptLevel), - TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this), - IntrinsicInfo() { + TLOF(new TargetLoweringObjectFileELF()), + Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() { setRequiresStructuredCFG(true); initAsmInfo(); } Index: llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -49,8 +49,8 @@ return X; } -static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo * X = new MCSubtargetInfo(); InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -76,7 +76,9 @@ bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc); bool parseDirectiveWord(unsigned Size, SMLoc L); - bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); } + bool is64Bit() const { + return STI.getTargetTriple().getArchName().startswith("sparcv9"); + } void expandSET(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); Index: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -63,12 +63,11 @@ return X; } -static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - Triple TheTriple(TT); if (CPU.empty()) - CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8"; + CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; InitSparcMCSubtargetInfo(X, TT, CPU, FS); return X; } Index: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h @@ -43,7 +43,7 @@ SparcFrameLowering FrameLowering; public: - SparcSubtarget(const std::string &TT, const std::string &CPU, + SparcSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64bit); const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } Index: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp @@ -49,7 +49,7 @@ return *this; } -SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, +SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64Bit) : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), Index: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp @@ -62,7 +62,7 @@ : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique()), - Subtarget(TT, CPU, FS, *this, is64bit) { + Subtarget(Triple(TT), CPU, FS, *this, is64bit) { initAsmInfo(); } Index: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -154,9 +154,8 @@ return X; } -static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitSystemZMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h @@ -56,7 +56,7 @@ SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); public: - SystemZSubtarget(const std::string &TT, const std::string &CPU, + SystemZSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM); const TargetFrameLowering *getFrameLowering() const override { Index: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -32,8 +32,7 @@ return *this; } -SystemZSubtarget::SystemZSubtarget(const std::string &TT, - const std::string &CPU, +SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), @@ -41,9 +40,9 @@ HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasTransactionalExecution(false), HasProcessorAssist(false), - HasVector(false), - TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), - TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} + HasVector(false), TargetTriple(TT), + InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), + TSInfo(*TM.getDataLayout()), FrameLowering() {} // Return true if GV binds locally under reloc model RM. static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) { Index: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -84,10 +84,10 @@ const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), - TT, CPU, FS, Options, RM, CM, OL), + : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, + RM, CM, OL), TLOF(make_unique()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(Triple(TT), CPU, FS, *this) { initAsmInfo(); } Index: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h =================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -52,16 +52,16 @@ } namespace X86_MC { - std::string ParseX86Triple(StringRef TT); +std::string ParseX86Triple(const Triple &TT); - unsigned getDwarfRegFlavour(Triple TT, bool isEH); +unsigned getDwarfRegFlavour(Triple TT, bool isEH); - void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); +void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); - /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. - /// do not need to go through TargetRegistry. - MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS); +/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. +/// do not need to go through TargetRegistry. +MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, + StringRef FS); } MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, Index: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -42,12 +42,11 @@ #define GET_SUBTARGETINFO_MC_DESC #include "X86GenSubtargetInfo.inc" -std::string X86_MC::ParseX86Triple(StringRef TT) { - Triple TheTriple(TT); +std::string X86_MC::ParseX86Triple(const Triple &TT) { std::string FS; - if (TheTriple.getArch() == Triple::x86_64) + if (TT.getArch() == Triple::x86_64) FS = "+64bit-mode,-32bit-mode,-16bit-mode"; - else if (TheTriple.getEnvironment() != Triple::CODE16) + else if (TT.getEnvironment() != Triple::CODE16) FS = "-64bit-mode,+32bit-mode,-16bit-mode"; else FS = "-64bit-mode,-32bit-mode,+16bit-mode"; @@ -75,8 +74,8 @@ } } -MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, + StringRef CPU, StringRef FS) { std::string ArchFS = X86_MC::ParseX86Triple(TT); if (!FS.empty()) { if (!ArchFS.empty()) Index: llvm/trunk/lib/Target/X86/X86Subtarget.h =================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h +++ llvm/trunk/lib/Target/X86/X86Subtarget.h @@ -253,9 +253,8 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - X86Subtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, const X86TargetMachine &TM, - unsigned StackAlignOverride); + X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + const X86TargetMachine &TM, unsigned StackAlignOverride); const X86TargetLowering *getTargetLowering() const override { return &TLInfo; Index: llvm/trunk/lib/Target/X86/X86Subtarget.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp @@ -287,7 +287,7 @@ return *this; } -X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, +X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const X86TargetMachine &TM, unsigned StackAlignOverride) : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others), Index: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp @@ -97,7 +97,7 @@ : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options, RM, CM, OL), TLOF(createTLOF(Triple(getTargetTriple()))), - Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) { + Subtarget(Triple(TT), CPU, FS, *this, Options.StackAlignmentOverride) { // Windows stack unwinder gets confused when execution flow "falls through" // after a call to 'noreturn' function. // To prevent that, we emit a trap for 'unreachable' IR instructions. @@ -148,7 +148,7 @@ // creation will depend on the TM and the code generation flags on the // function that reside in TargetOptions. resetTargetOptions(F); - I = llvm::make_unique(TargetTriple, CPU, FS, *this, + I = llvm::make_unique(Triple(TargetTriple), CPU, FS, *this, Options.StackAlignmentOverride); } return I.get(); Index: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -46,8 +46,8 @@ return X; } -static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitXCoreMCSubtargetInfo(X, TT, CPU, FS); return X; Index: llvm/trunk/lib/Target/XCore/XCoreSubtarget.h =================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.h +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.h @@ -40,9 +40,9 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - XCoreSubtarget(const std::string &TT, const std::string &CPU, + XCoreSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM); - + /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); Index: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp @@ -25,7 +25,7 @@ void XCoreSubtarget::anchor() { } -XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, +XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()) {} Index: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp =================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp @@ -31,7 +31,7 @@ T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(Triple(TT), CPU, FS, *this) { initAsmInfo(); } Index: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp @@ -1437,7 +1437,7 @@ // MCInstrInfo initialization routine. OS << "static inline void Init" << Target << "MCSubtargetInfo(MCSubtargetInfo *II, " - << "StringRef TT, StringRef CPU, StringRef FS) {\n"; + << "const Triple &TT, StringRef CPU, StringRef FS) {\n"; OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; if (NumFeatures) OS << Target << "FeatureKV, "; @@ -1482,10 +1482,11 @@ OS << "namespace llvm {\n"; OS << "class DFAPacketizer;\n"; OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" - << " explicit " << ClassName << "(StringRef TT, StringRef CPU, " + << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, " << "StringRef FS);\n" << "public:\n" - << " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI," + << " unsigned resolveSchedClass(unsigned SchedClass, " + << " const MachineInstr *DefMI," << " const TargetSchedModel *SchedModel) const override;\n" << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" << " const;\n" @@ -1515,7 +1516,7 @@ OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; } - OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " + OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, " << "StringRef FS)\n" << " : TargetSubtargetInfo() {\n" << " InitMCSubtargetInfo(TT, CPU, FS, ";