diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -963,6 +963,11 @@
 // FIXME: Several processors below are not using their own scheduler
 // model, but one of similar/previous processor. These should be fixed.
 
+def : ProcNoItin<"arm2",                                [ARMv2]>;
+def : ProcNoItin<"arm3",                                [ARMv2a]>;
+def : ProcNoItin<"arm6",                                [ARMv3]>;
+def : ProcNoItin<"arm7m",                               [ARMv3m]>;
+
 def : ProcNoItin<"arm8",                                [ARMv4]>;
 def : ProcNoItin<"arm810",                              [ARMv4]>;
 def : ProcNoItin<"strongarm",                           [ARMv4]>;
diff --git a/llvm/test/CodeGen/ARM/pr50454.ll b/llvm/test/CodeGen/ARM/pr50454.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/pr50454.ll
@@ -0,0 +1,9 @@
+;; At one point these CPUs were only know to Clang because
+;; they were defined in the Arm target parser but not in ARM.td.
+
+; RUN: llc < %s -mtriple=armv2-unknown-eabi -mcpu=arm2 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv2a-unknown-eabi -mcpu=arm3 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv3-unknown-eabi -mcpu=arm6 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv3m-unknown-eabi -mcpu=arm7m 2>&1 | FileCheck %s
+
+; CHECK-NOT: {{.*}} is not a recognized processor for this target (ignoring processor)