diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,6 +29,20 @@
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
    CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
+// Builtins for XL compatibility
+// Compare
+BUILTIN(__builtin_cmpeqb, "LLiLLiLLi", "")
+BUILTIN(__builtin_cmprb, "iCiii", "")
+BUILTIN(__builtin_setb, "LLiLLiLLi", "")
+// Multiply
+BUILTIN(__builtin_mulhd, "LLiLiLi", "")
+BUILTIN(__builtin_mulhdu, "ULLiULiULi", "")
+BUILTIN(__builtin_mulhw, "iii", "")
+BUILTIN(__builtin_mulhwu, "UiUiUi", "")
+BUILTIN(__builtin_maddhd, "LLiLLiLLiLLi", "")
+BUILTIN(__builtin_maddhdu, "ULLiULLiULLiULLi", "")
+BUILTIN(__builtin_maddld, "LLiLLiLLiLLi", "")
+
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3331,6 +3331,8 @@
      return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+  case PPC::BI__builtin_cmprb:
+    return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c b/clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+signed long long test_builtin_ppc_cmpeqb() {
+// CHECK-LABEL: @test_builtin_ppc_cmpeqb(
+// CHECK-NEXT:  entry:
+  signed long long a;
+  signed long long b;
+  return __builtin_cmpeqb(a, b);
+// CHECK:       %2 = call i64 @llvm.ppc.cmpeqb(i64 %0, i64 %1)
+}
+long long test_builtin_ppc_setb() {
+// CHECK-LABEL: @test_builtin_ppc_setb(
+// CHECK-NEXT:  entry:
+  signed long long a;
+  signed long long b;
+  return __builtin_setb(a, b);
+// CHECK:       %2 = call i64 @llvm.ppc.setb(i64 %0, i64 %1)
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-compare.c b/clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+int test_builtin_ppc_cmprb() {
+// CHECK-LABEL: @test_builtin_ppc_cmprb(
+// CHECK-NEXT:  entry:
+  unsigned int a;
+  unsigned int b;
+  unsigned int c;
+  unsigned int d;
+  return __builtin_cmprb(0, a, b) + __builtin_cmprb(1, c, d);
+// CHECK:       %2 = call i32 @llvm.ppc.cmprb(i32 0, i32 %0, i32 %1)
+// CHECK:       %5 = call i32 @llvm.ppc.cmprb(i32 1, i32 %3, i32 %4)
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
@@ -0,0 +1,62 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+long long test_builtin_ppc_mulhd() {
+// CHECK-LABEL: @test_builtin_ppc_mulhd(
+// CHECK-NEXT:  entry:
+  long int a;
+  long int b;
+  return __builtin_mulhd(a, b);
+// CHECK:       %2 = call i64 @llvm.ppc.mulhd(i64 %0, i64 %1)
+}
+
+unsigned long long test_builtin_ppc_mulhdu() {
+// CHECK-LABEL: @test_builtin_ppc_mulhdu(
+// CHECK-NEXT:  entry:
+  unsigned long int a;
+  unsigned long int b;
+  return __builtin_mulhdu(a, b);
+// CHECK:       %2 = call i64 @llvm.ppc.mulhdu(i64 %0, i64 %1)
+}
+
+signed long long test_builtin_ppc_maddhd() {
+// CHECK-LABEL: @test_builtin_ppc_maddhd(
+// CHECK-NEXT:  entry:
+  signed long long a;
+  signed long long b;
+  signed long long c;
+  return __builtin_maddhd(a, b, c);
+// CHECK:       %3 = call i64 @llvm.ppc.maddhd(i64 %0, i64 %1, i64 %2)
+}
+
+unsigned long long test_builtin_ppc_maddhdu() {
+// CHECK-LABEL: @test_builtin_ppc_maddhdu(
+// CHECK-NEXT:  entry:
+  unsigned long long a;
+  unsigned long long b;
+  unsigned long long c;
+  return __builtin_maddhdu(a, b, c);
+// CHECK:       %3 = call i64 @llvm.ppc.maddhdu(i64 %0, i64 %1, i64 %2)
+}
+
+signed long long test_builtin_ppc_maddld() {
+// CHECK-LABEL: @test_builtin_ppc_maddld(
+// CHECK-NEXT:  entry:
+  signed long long a;
+  signed long long b;
+  signed long long c;
+  return __builtin_maddld(a, b, c);
+// CHECK:       %3 = call i64 @llvm.ppc.maddld(i64 %0, i64 %1, i64 %2)
+}
+
+unsigned long long test_builtin_ppc_maddld_unsigned() {
+// CHECK-LABEL: @test_builtin_ppc_maddld_unsigned(
+// CHECK-NEXT:  entry:
+  unsigned long long a;
+  unsigned long long b;
+  unsigned long long c;
+  return __builtin_maddld(a, b, c);
+// CHECK:       %3 = call i64 @llvm.ppc.maddld(i64 %0, i64 %1, i64 %2)
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+
+int test_builtin_ppc_mulhw() {
+// CHECK-LABEL: @test_builtin_ppc_mulhw(
+// CHECK-NEXT:  entry:
+  int a;
+  int b;
+  return __builtin_mulhw(a, b);
+// CHECK:       %2 = call i32 @llvm.ppc.mulhw(i32 %0, i32 %1)
+}
+
+unsigned int test_builtin_ppc_mulhwu() {
+// CHECK-LABEL: @test_builtin_ppc_mulhwu(
+// CHECK-NEXT:  entry:
+  unsigned int a;
+  unsigned int b;
+  return __builtin_mulhwu(a, b);
+// CHECK:       %2 = call i32 @llvm.ppc.mulhwu(i32 %0, i32 %1)
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -132,6 +132,36 @@
       : GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
 
+  def int_ppc_cmpeqb
+      : GCCBuiltin<"__builtin_cmpeqb">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_cmprb
+      : GCCBuiltin<"__builtin_cmprb">,
+        Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_ppc_setb
+      : GCCBuiltin<"__builtin_setb">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_mulhd
+      : GCCBuiltin<"__builtin_mulhd">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_mulhdu
+      : GCCBuiltin<"__builtin_mulhdu">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_mulhw
+      : GCCBuiltin<"__builtin_mulhw">,
+        Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_ppc_mulhwu
+      : GCCBuiltin<"__builtin_mulhwu">,
+        Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_ppc_maddhd
+      : GCCBuiltin<"__builtin_maddhd">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_maddhdu
+      : GCCBuiltin<"__builtin_maddhdu">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_maddld
+      : GCCBuiltin<"__builtin_maddld">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
 }
 
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1645,6 +1645,26 @@
 def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD  g8rc:$val, memrix:$ptr)>;
 def : Pat<(atomic_store_64 XForm:$ptr,  i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
 
+let Predicates = [IsISA3_0, In64BitMode] in {
+def : Pat<(i64 (int_ppc_cmpeqb i64:$a, i64:$b)),
+          (i64 (SETB8 (CMPEQB $a, $b)))>;
+def : Pat<(i64 (int_ppc_setb i64:$a, i64:$b)),
+          (i64 (SETB8 (CMPD $a, $b)))>;
+def : Pat<(i64 (int_ppc_maddhd i64:$a, i64:$b, i64:$c)),
+          (i64 (MADDHD $a, $b, $c))>;
+def : Pat<(i64 (int_ppc_maddhdu i64:$a, i64:$b, i64:$c)),
+          (i64 (MADDHDU $a, $b, $c))>;
+def : Pat<(i64 (int_ppc_maddld i64:$a, i64:$b, i64:$c)),
+          (i64 (MADDLD8 $a, $b, $c))>;
+}
+
+let Predicates = [In64BitMode] in {
+def : Pat<(i64 (int_ppc_mulhd i64:$a, i64:$b)),
+          (i64 (MULHD $a, $b))>;
+def : Pat<(i64 (int_ppc_mulhdu i64:$a, i64:$b)),
+          (i64 (MULHDU $a, $b))>;
+}
+
 let Predicates = [IsISA3_0] in {
 // DARN (deliver random number)
 // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5243,6 +5243,15 @@
                        "setb $RT, $BFA", IIC_IntGeneral>;
 } // IsISA3_0
 
+let Predicates = [IsISA3_0] in {
+def : Pat<(i32 (int_ppc_cmprb i32:$a, i32:$b, i32:$c)),
+          (i32 (SETB (CMPRB imm:$a, $b, $c)))>;
+}
+def : Pat<(i32 (int_ppc_mulhw i32:$a, i32:$b)),
+          (i32 (MULHW $a, $b))>;
+def : Pat<(i32 (int_ppc_mulhwu i32:$a, i32:$b)),
+          (i32 (MULHWU $a, $b))>;
+
 // Fast 32-bit reverse bits algorithm:
 // Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
 // n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_cmpeqb(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_cmpeqb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpeqb cr0, r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.cmpeqb(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.cmpeqb(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_setb(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_setb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.setb(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.setb(i64, i64) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
+
+
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_cmprb(i32 %a, i32%b, i32 %c, i32%d) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_cmprb:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    cmprb cr0, 0, r3, r4
+; CHECK-32-NEXT:    setb r3, cr0
+; CHECK-32-NEXT:    cmprb cr0, 1, r5, r6
+; CHECK-32-NEXT:    setb r4, cr0
+; CHECK-32-NEXT:    add r3, r3, r4
+; CHECK-32-NEXT:    blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_cmprb:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    cmprb cr0, 0, r3, r4
+; CHECK-64-NEXT:    setb r3, cr0
+; CHECK-64-NEXT:    cmprb cr0, 1, r5, r6
+; CHECK-64-NEXT:    setb r4, cr0
+; CHECK-64-NEXT:    add r3, r3, r4
+; CHECK-64-NEXT:    extsw r3, r3
+; CHECK-64-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.cmprb(i32 0, i32 %a, i32 %b)
+  %1 = call i32 @llvm.ppc.cmprb(i32 1, i32 %c, i32 %d)
+  %add = add nsw i32 %0, %1
+  ret i32 %add
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.cmprb(i32, i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhd(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mulhd r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhd(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhd(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_mulhdu(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: test_builtin_ppc_mulhdu:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mulhdu r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mulhdu(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.mulhdu(i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_maddhd(i64 %a, i64 %b, i64 %c) #0 {
+; CHECK-LABEL: test_builtin_ppc_maddhd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    maddhd r3, r3, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhd(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.maddhd(i64, i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_maddhdu(i64 %a, i64 %b, i64 %c) #0 {
+; CHECK-LABEL: test_builtin_ppc_maddhdu:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    maddhdu r3, r3, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.maddhdu(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.maddhdu(i64, i64, i64) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i64 @test_builtin_ppc_maddld(i64 %a, i64 %b, i64 %c) #0 {
+; CHECK-LABEL: test_builtin_ppc_maddld:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    maddld r3, r3, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.maddld(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.maddld(i64, i64, i64) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }
+
+
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @test_builtin_ppc_mulhw(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhw:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    mulhw r3, r3, r4
+; CHECK-32-NEXT:    blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhw:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    mulhw r3, r3, r4
+; CHECK-64-NEXT:    extsw r3, r3
+; CHECK-64-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhw(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhw(i32, i32) #1
+
+; Function Attrs: noinline nounwind optnone
+define dso_local zeroext i32 @test_builtin_ppc_mulhwu(i32 %a, i32%b) #0 {
+; CHECK-32-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    mulhwu r3, r3, r4
+; CHECK-32-NEXT:    blr
+;
+; CHECK-64-LABEL: test_builtin_ppc_mulhwu:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    mulhwu r3, r3, r4
+; CHECK-64-NEXT:    clrldi r3, r3, 32
+; CHECK-64-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mulhwu(i32 %a, i32 %b)
+  ret i32 %0
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.mulhwu(i32, i32) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind readnone }