diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -332,7 +332,7 @@
   bits<4> elements    = 0;
   bits<1> has_sccb    = 1;
   bits<1> sccb_value  = 0;
-  bits<1> IsBufferInv = 0;
+  bits<1> IsCacheCtrl = 0;
 }
 
 class MUBUF_Real <MUBUF_Pseudo ps> :
@@ -364,9 +364,8 @@
   bits<1> acc = !if(ps.has_vdata, vdata{9}, 0);
 }
 
-
-// For cache invalidation instructions.
-class MUBUF_Invalidate <string opName, SDPatternOperator node = null_frag> :
+// For cache control instructions.
+class MUBUF_CacheControl <string opName, SDPatternOperator node = null_frag> :
   MUBUF_Pseudo<opName, (outs), (ins), "", [(node)]> {
 
   let AsmMatchConverter = "";
@@ -375,7 +374,7 @@
   let mayLoad = 0;
   let mayStore = 0;
 
-  let IsBufferInv = 1;
+  let IsCacheCtrl = 1;
   // Set everything else to 0.
   let offen       = 0;
   let idxen       = 0;
@@ -1033,7 +1032,7 @@
 defm BUFFER_ATOMIC_RSUB_X2     : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub_x2">;
 */
 
-def BUFFER_WBINVL1_SC : MUBUF_Invalidate <"buffer_wbinvl1_sc",
+def BUFFER_WBINVL1_SC : MUBUF_CacheControl <"buffer_wbinvl1_sc",
                                           int_amdgcn_buffer_wbinvl1_sc>;
 }
 
@@ -1103,7 +1102,7 @@
 
 } // End HasD16LoadStore
 
-def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1",
+def BUFFER_WBINVL1 : MUBUF_CacheControl <"buffer_wbinvl1",
                                        int_amdgcn_buffer_wbinvl1>;
 
 let SubtargetPredicate = HasAtomicFaddInsts in {
@@ -1165,15 +1164,15 @@
 // Instruction definitions for CI and newer.
 //===----------------------------------------------------------------------===//
 
-def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
+def BUFFER_WBINVL1_VOL : MUBUF_CacheControl <"buffer_wbinvl1_vol",
                                            int_amdgcn_buffer_wbinvl1_vol>;
 
 } // End let SubtargetPredicate = isGFX7Plus
 
 let SubtargetPredicate = isGFX90APlus in {
-  def BUFFER_WBL2  : MUBUF_Invalidate<"buffer_wbl2"> {
+  def BUFFER_WBL2  : MUBUF_CacheControl<"buffer_wbl2"> {
   }
-  def BUFFER_INVL2 : MUBUF_Invalidate<"buffer_invl2"> {
+  def BUFFER_INVL2 : MUBUF_CacheControl<"buffer_invl2"> {
   }
 
   defm BUFFER_ATOMIC_ADD_F64 : MUBUF_Pseudo_Atomics<"buffer_atomic_add_f64", VReg_64, f64, int_amdgcn_global_atomic_fadd>;
@@ -1182,8 +1181,8 @@
 } // End SubtargetPredicate = isGFX90APlus
 
 let SubtargetPredicate = isGFX10Plus in {
-  def BUFFER_GL0_INV : MUBUF_Invalidate<"buffer_gl0_inv">;
-  def BUFFER_GL1_INV : MUBUF_Invalidate<"buffer_gl1_inv">;
+  def BUFFER_GL0_INV : MUBUF_CacheControl<"buffer_gl0_inv">;
+  def BUFFER_GL1_INV : MUBUF_CacheControl<"buffer_gl1_inv">;
 } // End SubtargetPredicate = isGFX10Plus
 
 //===----------------------------------------------------------------------===//
@@ -2610,7 +2609,7 @@
   let CppTypeName = "MUBUFInfo";
   let Fields = [
     "Opcode", "BaseOpcode", "elements", "has_vaddr", "has_srsrc", "has_soffset",
-    "IsBufferInv"
+    "IsCacheCtrl"
   ];
 
   let PrimaryKey = ["Opcode"];
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1320,7 +1320,7 @@
     if (FlatASCount > 1)
       ScoreBrackets->setPendingFlat();
   } else if (SIInstrInfo::isVMEM(Inst) &&
-             !llvm::AMDGPU::getMUBUFIsBufferInv(Inst.getOpcode())) {
+             !llvm::AMDGPU::getMUBUFIsCacheCtrl(Inst.getOpcode())) {
     if (!ST->hasVscnt())
       ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst);
     else if ((Inst.mayLoad() && !SIInstrInfo::isAtomicNoRet(Inst)) ||
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -400,7 +400,7 @@
 bool getMUBUFHasSoffset(unsigned Opc);
 
 LLVM_READONLY
-bool getMUBUFIsBufferInv(unsigned Opc);
+bool getMUBUFIsCacheCtrl(unsigned Opc);
 
 LLVM_READONLY
 bool getSMEMIsBuffer(unsigned Opc);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -190,7 +190,7 @@
   bool has_vaddr;
   bool has_srsrc;
   bool has_soffset;
-  bool IsBufferInv;
+  bool IsCacheCtrl;
 };
 
 struct MTBUFInfo {
@@ -286,9 +286,9 @@
   return Info ? Info->has_soffset : false;
 }
 
-bool getMUBUFIsBufferInv(unsigned Opc) {
+bool getMUBUFIsCacheCtrl(unsigned Opc) {
   const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
-  return Info ? Info->IsBufferInv : false;
+  return Info ? Info->IsCacheCtrl : false;
 }
 
 bool getSMEMIsBuffer(unsigned Opc) {