Index: llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -994,8 +994,8 @@
     // If type is to be expanded, split the vector.
     //  <4 x i140> -> <2 x i140>
     if (LK.first == TypeExpandInteger) {
-      if (VT.getVectorElementCount() == ElementCount::getScalable(1))
-        report_fatal_error("Cannot legalize this scalable vector");
+      if (VT.getVectorElementCount().isScalable())
+        return LegalizeKind(TypeScalarizeScalableVector, EltVT);
       return LegalizeKind(TypeSplitVector,
                           VT.getHalfNumVectorElementsVT(Context));
     }
@@ -1058,7 +1058,7 @@
   }
 
   if (VT.getVectorElementCount() == ElementCount::getScalable(1))
-    report_fatal_error("Cannot legalize this vector");
+    return LegalizeKind(TypeScalarizeScalableVector, EltVT);
 
   // Vectors with illegal element types are expanded.
   EVT NVT = EVT::getVectorVT(Context, EltVT,
@@ -1823,6 +1823,9 @@
   while (true) {
     LegalizeKind LK = getTypeConversion(C, MTy);
 
+    if (LK.first == TypeScalarizeScalableVector)
+      return std::make_pair(InstructionCost::getInvalid(), MVT::getVT(Ty));
+
     if (LK.first == TypeLegal)
       return std::make_pair(Cost, MTy.getSimpleVT());
 
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1180,6 +1180,9 @@
     return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
                                         CostKind);
   auto LT = TLI->getTypeLegalizationCost(DL, Src);
+  if (!LT.first.isValid())
+    return LT.first;
+
   return LT.first * 2;
 }
 
@@ -1192,6 +1195,9 @@
                                          Alignment, CostKind, I);
   auto *VT = cast<VectorType>(DataTy);
   auto LT = TLI->getTypeLegalizationCost(DL, DataTy);
+  if (!LT.first.isValid())
+    return LT.first;
+
   ElementCount LegalVF = LT.second.getVectorElementCount();
   Optional<unsigned> MaxNumVScale = getMaxVScale();
   assert(MaxNumVScale && "Expected valid max vscale value");
@@ -1218,6 +1224,8 @@
                                   CostKind);
 
   auto LT = TLI->getTypeLegalizationCost(DL, Ty);
+  if (!LT.first.isValid())
+    return LT.first;
 
   // TODO: consider latency as well for TCK_SizeAndLatency.
   if (CostKind == TTI::TCK_CodeSize || CostKind == TTI::TCK_SizeAndLatency)
Index: llvm/test/Analysis/CostModel/AArch64/sve-illegal-types.ll
===================================================================
--- /dev/null
+++ llvm/test/Analysis/CostModel/AArch64/sve-illegal-types.ll
@@ -0,0 +1,49 @@
+; RUN: opt -cost-model -analyze -mtriple=aarch64--linux-gnu -mattr=+sve  < %s | FileCheck %s
+
+define <vscale x 2 x i128> @load_nxvi128(<vscale x 2 x i128>* %val) {
+; CHECK-LABEL: 'load_nxvi128'
+; CHECK-NEXT: Invalid cost for instruction: %load = load <vscale x 2 x i128>, <vscale x 2 x i128>* %val
+  %load = load <vscale x 2 x i128>, <vscale x 2 x i128>* %val
+  ret <vscale x 2 x i128> %load
+}
+
+define void @store_nxvi128(<vscale x 1 x i128>* %ptrs, <vscale x 1 x i128> %val) {
+; CHECK-LABEL: 'store_nxvi128'
+; CHECK-NEXT: Invalid cost for instruction: store <vscale x 1 x i128> %val, <vscale x 1 x i128>* %ptrs
+  store <vscale x 1 x i128> %val, <vscale x 1 x i128>* %ptrs
+  ret void
+}
+
+define <vscale x 4 x fp128> @masked_load_nxvfp128(<vscale x 4 x fp128>* %val, <vscale x 4 x i1> %mask, <vscale x 4 x fp128> %passthru) {
+; CHECK-LABEL: 'masked_load_nxvfp128'
+; CHECK-NEXT: Invalid cost for instruction: %mload = call <vscale x 4 x fp128> @llvm.masked.load.nxv4f128.p0nxv4f128(<vscale x 4 x fp128>* %val, i32 8, <vscale x 4 x i1> %mask, <vscale x 4 x fp128> %passthru)
+  %mload = call <vscale x 4 x fp128> @llvm.masked.load.nxv4f128(<vscale x 4 x fp128>* %val, i32 8, <vscale x 4 x i1> %mask, <vscale x 4 x fp128> %passthru)
+  ret <vscale x 4 x fp128> %mload
+}
+
+define void @masked_store_nxvfp128(<vscale x 4 x fp128> %val, <vscale x 4 x fp128>* %ptrs, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: 'masked_store_nxvfp128'
+; CHECK-NEXT: Invalid cost for instruction: call void @llvm.masked.store.nxv4f128.p0nxv4f128(<vscale x 4 x fp128> %val, <vscale x 4 x fp128>* %ptrs, i32 8, <vscale x 4 x i1> %mask)
+  call void @llvm.masked.store.nxv4f128(<vscale x 4 x fp128> %val, <vscale x 4 x fp128>* %ptrs, i32 8, <vscale x 4 x i1> %mask)
+  ret void
+}
+
+define <vscale x 2 x i128> @masked_gather_nxv2i128(<vscale x 2 x i128*> %ld, <vscale x 2 x i1> %masks, <vscale x 2 x i128> %passthru) {
+; CHECK-LABEL: 'masked_gather_nxv2i128'
+; CHECK-NEXT: Invalid cost for instruction: %mgather = call <vscale x 2 x i128> @llvm.masked.gather.nxv2i128.nxv2p0i128(<vscale x 2 x i128*> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x i128> %passthru)
+  %mgather = call <vscale x 2 x i128> @llvm.masked.gather.nxv2i128(<vscale x 2 x i128*> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x i128> %passthru)
+  ret <vscale x 2 x i128> %mgather
+}
+
+define void @masked_scatter_nxv4i128(<vscale x 4 x i128> %val, <vscale x 4 x i128*> %ptrs, <vscale x 4 x i1> %masks) {
+; CHECK-LABEL: 'masked_scatter_nxv4i128'
+; CHECK-NEXT: Invalid cost for instruction: call void @llvm.masked.scatter.nxv4i128.nxv4p0i128(<vscale x 4 x i128> %val, <vscale x 4 x i128*> %ptrs, i32 0, <vscale x 4 x i1> %masks)
+  call void @llvm.masked.scatter.nxv4i128(<vscale x 4 x i128> %val, <vscale x 4 x i128*> %ptrs, i32 0, <vscale x 4 x i1> %masks)
+  ret void
+}
+
+declare <vscale x 4 x fp128> @llvm.masked.load.nxv4f128(<vscale x 4 x fp128>*, i32, <vscale x 4 x i1>, <vscale x 4 x fp128>)
+declare <vscale x 2 x i128> @llvm.masked.gather.nxv2i128(<vscale x 2 x i128*>, i32, <vscale x 2 x i1>, <vscale x 2 x i128>)
+
+declare void @llvm.masked.store.nxv4f128(<vscale x 4 x fp128>, <vscale x 4 x fp128>*, i32, <vscale x 4 x i1>)
+declare void @llvm.masked.scatter.nxv4i128(<vscale x 4 x i128>, <vscale x 4 x i128*>, i32, <vscale x 4 x i1>)