Index: llvm/include/llvm/Analysis/TargetTransformInfo.h
===================================================================
--- llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1320,6 +1320,9 @@
   bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
                                     unsigned AddrSpace) const;
 
+  /// \returns True if it is legal to vectorize the given element type.
+  bool isElementTypeLegalForScalableVector(Type *Ty) const;
+
   /// \returns True if it is legal to vectorize the given reduction kind.
   bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc,
                                    ElementCount VF) const;
@@ -1704,6 +1707,7 @@
   virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
                                             Align Alignment,
                                             unsigned AddrSpace) const = 0;
+  virtual bool isElementTypeLegalForScalableVector(Type *Ty) const = 0;
   virtual bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc,
                                            ElementCount VF) const = 0;
   virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
@@ -2253,6 +2257,9 @@
     return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
                                              AddrSpace);
   }
+  bool isElementTypeLegalForScalableVector(Type *Ty) const override {
+    return Impl.isElementTypeLegalForScalableVector(Ty);
+  }
   bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc,
                                    ElementCount VF) const override {
     return Impl.isLegalToVectorizeReduction(RdxDesc, VF);
Index: llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
===================================================================
--- llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -720,6 +720,8 @@
     return true;
   }
 
+  bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
+
   unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
                                unsigned ChainSizeInBytes,
                                VectorType *VecTy) const {
Index: llvm/lib/Analysis/TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Analysis/TargetTransformInfo.cpp
+++ llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -997,6 +997,10 @@
                                                AddrSpace);
 }
 
+bool TargetTransformInfo::isElementTypeLegalForScalableVector(Type *Ty) const {
+  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
+}
+
 bool TargetTransformInfo::isLegalToVectorizeReduction(
     RecurrenceDescriptor RdxDesc, ElementCount VF) const {
   return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
Index: llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -995,7 +995,7 @@
     //  <4 x i140> -> <2 x i140>
     if (LK.first == TypeExpandInteger) {
       if (VT.getVectorElementCount() == ElementCount::getScalable(1))
-        report_fatal_error("Cannot legalize this scalable vector");
+        return LegalizeKind(TypeScalarizeScalableVector, EltVT);
       return LegalizeKind(TypeSplitVector,
                           VT.getHalfNumVectorElementsVT(Context));
     }
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -288,6 +288,8 @@
 
   bool supportsScalableVectors() const { return ST->hasSVE(); }
 
+  bool isElementTypeLegalForScalableVector(Type *Ty) const;
+
   bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc,
                                    ElementCount VF) const;
 
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1160,6 +1160,10 @@
   if (!isa<ScalableVectorType>(Src))
     return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
                                         CostKind);
+
+  if (!isElementTypeLegalForScalableVector(Src->getScalarType()))
+    return InstructionCost::getInvalid();
+
   auto LT = TLI->getTypeLegalizationCost(DL, Src);
   return LT.first * 2;
 }
@@ -1171,6 +1175,10 @@
   if (!isa<ScalableVectorType>(DataTy))
     return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
                                          Alignment, CostKind, I);
+
+  if (!isElementTypeLegalForScalableVector(DataTy->getScalarType()))
+    return InstructionCost::getInvalid();
+
   auto *VT = cast<VectorType>(DataTy);
   auto LT = TLI->getTypeLegalizationCost(DL, DataTy);
   ElementCount LegalVF = LT.second.getVectorElementCount();
@@ -1198,6 +1206,11 @@
     return BaseT::getMemoryOpCost(Opcode, Ty, Alignment, AddressSpace,
                                   CostKind);
 
+  // Return an invalid cost if Ty is unsupported
+  VectorType *VTy = dyn_cast<ScalableVectorType>(Ty);
+  if (VTy && !isElementTypeLegalForScalableVector(VTy->getScalarType()))
+    return InstructionCost::getInvalid();
+
   auto LT = TLI->getTypeLegalizationCost(DL, Ty);
 
   // TODO: consider latency as well for TCK_SizeAndLatency.
@@ -1501,6 +1514,10 @@
   return Considerable;
 }
 
+bool AArch64TTIImpl::isElementTypeLegalForScalableVector(Type *Ty) const {
+  return Ty->isIntegerTy(1) || isLegalElementTypeForSVE(Ty);
+}
+
 bool AArch64TTIImpl::isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc,
                                                  ElementCount VF) const {
   if (!VF.isScalable())
Index: llvm/test/Analysis/CostModel/AArch64/sve-illegal-types.ll
===================================================================
--- /dev/null
+++ llvm/test/Analysis/CostModel/AArch64/sve-illegal-types.ll
@@ -0,0 +1,49 @@
+; RUN: opt -cost-model -analyze -mtriple=aarch64--linux-gnu -mattr=+sve  < %s | FileCheck %s
+
+define <vscale x 2 x i128> @load_nxvi128(<vscale x 2 x i128>* %val) {
+; CHECK-LABEL: 'load_nxvi128'
+; CHECK-NEXT: Invalid cost for instruction: %load = load <vscale x 2 x i128>, <vscale x 2 x i128>* %val
+  %load = load <vscale x 2 x i128>, <vscale x 2 x i128>* %val
+  ret <vscale x 2 x i128> %load
+}
+
+define void @store_nxvi128(<vscale x 1 x i128>* %ptrs, <vscale x 1 x i128> %val) {
+; CHECK-LABEL: 'store_nxvi128'
+; CHECK-NEXT: Invalid cost for instruction: store <vscale x 1 x i128> %val, <vscale x 1 x i128>* %ptrs
+  store <vscale x 1 x i128> %val, <vscale x 1 x i128>* %ptrs
+  ret void
+}
+
+define <vscale x 4 x fp128> @masked_load_nxvfp128(<vscale x 4 x fp128>* %val, <vscale x 4 x i1> %mask, <vscale x 4 x fp128> %passthru) {
+; CHECK-LABEL: 'masked_load_nxvfp128'
+; CHECK-NEXT: Invalid cost for instruction: %mload = call <vscale x 4 x fp128> @llvm.masked.load.nxv4f128.p0nxv4f128(<vscale x 4 x fp128>* %val, i32 8, <vscale x 4 x i1> %mask, <vscale x 4 x fp128> %passthru)
+  %mload = call <vscale x 4 x fp128> @llvm.masked.load.nxv4f128(<vscale x 4 x fp128>* %val, i32 8, <vscale x 4 x i1> %mask, <vscale x 4 x fp128> %passthru)
+  ret <vscale x 4 x fp128> %mload
+}
+
+define void @masked_store_nxvfp128(<vscale x 4 x fp128> %val, <vscale x 4 x fp128>* %ptrs, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: 'masked_store_nxvfp128'
+; CHECK-NEXT: Invalid cost for instruction: call void @llvm.masked.store.nxv4f128.p0nxv4f128(<vscale x 4 x fp128> %val, <vscale x 4 x fp128>* %ptrs, i32 8, <vscale x 4 x i1> %mask)
+  call void @llvm.masked.store.nxv4f128(<vscale x 4 x fp128> %val, <vscale x 4 x fp128>* %ptrs, i32 8, <vscale x 4 x i1> %mask)
+  ret void
+}
+
+define <vscale x 2 x i128> @masked_gather_nxv2i128(<vscale x 2 x i128*> %ld, <vscale x 2 x i1> %masks, <vscale x 2 x i128> %passthru) {
+; CHECK-LABEL: 'masked_gather_nxv2i128'
+; CHECK-NEXT: Invalid cost for instruction: %mgather = call <vscale x 2 x i128> @llvm.masked.gather.nxv2i128.nxv2p0i128(<vscale x 2 x i128*> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x i128> %passthru)
+  %mgather = call <vscale x 2 x i128> @llvm.masked.gather.nxv2i128(<vscale x 2 x i128*> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x i128> %passthru)
+  ret <vscale x 2 x i128> %mgather
+}
+
+define void @masked_scatter_nxv4i128(<vscale x 4 x i128> %val, <vscale x 4 x i128*> %ptrs, <vscale x 4 x i1> %masks) {
+; CHECK-LABEL: 'masked_scatter_nxv4i128'
+; CHECK-NEXT: Invalid cost for instruction: call void @llvm.masked.scatter.nxv4i128.nxv4p0i128(<vscale x 4 x i128> %val, <vscale x 4 x i128*> %ptrs, i32 0, <vscale x 4 x i1> %masks)
+  call void @llvm.masked.scatter.nxv4i128(<vscale x 4 x i128> %val, <vscale x 4 x i128*> %ptrs, i32 0, <vscale x 4 x i1> %masks)
+  ret void
+}
+
+declare <vscale x 4 x fp128> @llvm.masked.load.nxv4f128(<vscale x 4 x fp128>*, i32, <vscale x 4 x i1>, <vscale x 4 x fp128>)
+declare <vscale x 2 x i128> @llvm.masked.gather.nxv2i128(<vscale x 2 x i128*>, i32, <vscale x 2 x i1>, <vscale x 2 x i128>)
+
+declare void @llvm.masked.store.nxv4f128(<vscale x 4 x fp128>, <vscale x 4 x fp128>*, i32, <vscale x 4 x i1>)
+declare void @llvm.masked.scatter.nxv4i128(<vscale x 4 x i128>, <vscale x 4 x i128*>, i32, <vscale x 4 x i1>)