diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -186,6 +186,7 @@ REV32, REV64, EXT, + SPLICE, // Vector shift by scalar VSHL, @@ -996,6 +997,8 @@ SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op, + SelectionDAG &DAG) const; SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl &Created) const override; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1447,6 +1447,7 @@ setOperationAction(ISD::BITCAST, VT, Custom); setOperationAction(ISD::BITREVERSE, VT, Custom); setOperationAction(ISD::BSWAP, VT, Custom); + setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); setOperationAction(ISD::CTLZ, VT, Custom); setOperationAction(ISD::CTPOP, VT, Custom); setOperationAction(ISD::CTTZ, VT, Custom); @@ -1893,6 +1894,7 @@ MAKE_CASE(AArch64ISD::REV32) MAKE_CASE(AArch64ISD::REV64) MAKE_CASE(AArch64ISD::EXT) + MAKE_CASE(AArch64ISD::SPLICE) MAKE_CASE(AArch64ISD::VSHL) MAKE_CASE(AArch64ISD::VLSHR) MAKE_CASE(AArch64ISD::VASHR) @@ -3806,6 +3808,9 @@ case Intrinsic::aarch64_sve_zip2: return DAG.getNode(AArch64ISD::ZIP2, dl, Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); + case Intrinsic::aarch64_sve_splice: + return DAG.getNode(AArch64ISD::SPLICE, dl, Op.getValueType(), + Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); case Intrinsic::aarch64_sve_ptrue: return DAG.getNode(AArch64ISD::PTRUE, dl, Op.getValueType(), Op.getOperand(1)); @@ -9960,6 +9965,9 @@ SDValue AArch64TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { + if (useSVEForFixedLengthVectorVT(Op.getValueType())) + return LowerFixedLengthConcatVectorsToSVE(Op, DAG); + assert(Op.getValueType().isScalableVector() && isTypeLegal(Op.getValueType()) && "Expected legal scalable vector type!"); @@ -17689,6 +17697,36 @@ return convertFromScalableVector(DAG, VT, Op); } +SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE( + SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + auto SrcOp1 = Op.getOperand(0); + auto SrcOp2 = Op.getOperand(1); + EVT VT = Op.getValueType(); + EVT SrcVT = SrcOp1.getValueType(); + + EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT); + EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT); + + // For now don't support concat of more than 2 vectors + if (Op->getNumOperands() != 2) + return SDValue(); + + SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT); + + SrcOp1 = convertToScalableVector(DAG, ContainerSrcVT, SrcOp1); + SrcOp2 = convertToScalableVector(DAG, ContainerSrcVT, SrcOp2); + + // Skip the splice for the trivial case of concat with undef + if (SrcOp2.isUndef()) + Op = SrcOp1; + else + Op = + DAG.getNode(AArch64ISD::SPLICE, DL, ContainerDstVT, Pg, SrcOp1, SrcOp2); + + return convertFromScalableVector(DAG, VT, Op); +} + SDValue AArch64TargetLowering::getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -259,6 +259,8 @@ def SDT_AArch64DUP_PRED : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 3>, SDTCisVec<1>, SDTCVecEltisVT<1,i1>]>; def AArch64dup_mt : SDNode<"AArch64ISD::DUP_MERGE_PASSTHRU", SDT_AArch64DUP_PRED>; +def AArch64splice : SDNode<"AArch64ISD::SPLICE", SDT_AArch64Arith>; + def step_vector_oneuse : PatFrag<(ops node:$idx), (step_vector node:$idx), [{ return N->hasOneUse(); @@ -611,7 +613,7 @@ // Select elements from either vector (predicated) defm SEL_ZPZZ : sve_int_sel_vvv<"sel", vselect>; - defm SPLICE_ZPZ : sve_int_perm_splice<"splice", int_aarch64_sve_splice>; + defm SPLICE_ZPZ : sve_int_perm_splice<"splice", AArch64splice>; defm COMPACT_ZPZ : sve_int_perm_compact<"compact", int_aarch64_sve_compact>; defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>; diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll @@ -0,0 +1,803 @@ +; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE +; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK +; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK +; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048 + +target triple = "aarch64-unknown-linux-gnu" + +; Don't use SVE when its registers are no bigger than NEON. +; NO_SVE-NOT: ptrue + +; +; i8 +; + +; Don't use SVE for 64-bit vectors. +define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2) #0 { +; CHECK-LABEL: concat_v8i8: +; CHECK: uzp1 v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %res = shufflevector <4 x i8> %op1, <4 x i8> %op2, <8 x i32> + ret <8 x i8> %res +} + +; Don't use SVE for 128-bit vectors. +define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) #0 { +; CHECK-LABEL: concat_v16i8: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <8 x i8> %op1, <8 x i8> %op2, <16 x i32> + ret <16 x i8> %res +} + +define void @concat_v32i8(<16 x i8>* %a, <16 x i8>* %b, <32 x i8>* %c) #0 { +; CHECK-LABEL: concat_v32i8: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].b, vl16 +; CHECK-NEXT: splice [[RES:z[0-9]+]].b, [[PG1]], z[[OP1]].b, z[[OP2]].b +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].b, vl32 +; CHECK-NEXT: st1b { [[RES]].b }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <16 x i8>, <16 x i8>* %a + %op2 = load <16 x i8>, <16 x i8>* %b + %res = shufflevector <16 x i8> %op1, <16 x i8> %op2, <32 x i32> + store <32 x i8> %res, <32 x i8>* %c + ret void +} + +define void @concat_v64i8(<32 x i8>* %a, <32 x i8>* %b, <64 x i8>* %c) #0 { +; CHECK-LABEL: concat_v64i8: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].b, vl32 +; VBITS_GE_512-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].b, [[PG1]], [[OP1]].b, [[OP2]].b +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].b, vl64 +; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b + %res = shufflevector <32 x i8> %op1, <32 x i8> %op2, <64 x i32> + store <64 x i8> %res, <64 x i8>* %c + ret void +} + +define void @concat_v128i8(<64 x i8>* %a, <64 x i8>* %b, <128 x i8>* %c) #0 { +; CHECK-LABEL: concat_v128i8: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].b, vl64 +; VBITS_GE_1024-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].b, [[PG1]], [[OP1]].b, [[OP2]].b +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].b, vl128 +; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <64 x i8>, <64 x i8>* %a + %op2 = load <64 x i8>, <64 x i8>* %b + %res = shufflevector <64 x i8> %op1, <64 x i8> %op2, <128 x i32> + store <128 x i8> %res, <128 x i8>* %c + ret void +} + +define void @concat_v256i8(<128 x i8>* %a, <128 x i8>* %b, <256 x i8>* %c) #0 { +; CHECK-LABEL: concat_v256i8: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].b, vl128 +; VBITS_GE_2048-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].b, [[PG1]], [[OP1]].b, [[OP2]].b +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].b, vl256 +; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <128 x i8>, <128 x i8>* %a + %op2 = load <128 x i8>, <128 x i8>* %b + %res = shufflevector <128 x i8> %op1, <128 x i8> %op2, <256 x i32> + store <256 x i8> %res, <256 x i8>* %c + ret void +} + +; +; i16 +; + +; Don't use SVE for 64-bit vectors. +define <4 x i16> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2) #0 { +; CHECK-LABEL: concat_v4i16: +; CHECK: uzp1 v0.4h, v0.4h, v1.4h +; CHECK-NEXT: ret + %res = shufflevector <2 x i16> %op1, <2 x i16> %op2, <4 x i32> + ret <4 x i16> %res +} + +; Don't use SVE for 128-bit vectors. +define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) #0 { +; CHECK-LABEL: concat_v8i16: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <4 x i16> %op1, <4 x i16> %op2, <8 x i32> + ret <8 x i16> %res +} + +define void @concat_v16i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) #0 { +; CHECK-LABEL: concat_v16i16: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].h, vl8 +; CHECK-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], z[[OP1]].h, z[[OP2]].h +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].h, vl16 +; CHECK-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <8 x i16>, <8 x i16>* %a + %op2 = load <8 x i16>, <8 x i16>* %b + %res = shufflevector <8 x i16> %op1, <8 x i16> %op2, <16 x i32> + store <16 x i16> %res, <16 x i16>* %c + ret void +} + +define void @concat_v32i16(<16 x i16>* %a, <16 x i16>* %b, <32 x i16>* %c) #0 { +; CHECK-LABEL: concat_v32i16: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].h, vl16 +; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], [[OP1]].h, [[OP2]].h +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].h, vl32 +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b + %res = shufflevector <16 x i16> %op1, <16 x i16> %op2, <32 x i32> + store <32 x i16> %res, <32 x i16>* %c + ret void +} + +define void @concat_v64i16(<32 x i16>* %a, <32 x i16>* %b, <64 x i16>* %c) #0 { +; CHECK-LABEL: concat_v64i16: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].h, vl32 +; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], [[OP1]].h, [[OP2]].h +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].h, vl64 +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <32 x i16>, <32 x i16>* %a + %op2 = load <32 x i16>, <32 x i16>* %b + %res = shufflevector <32 x i16> %op1, <32 x i16> %op2, <64 x i32> + store <64 x i16> %res, <64 x i16>* %c + ret void +} + +define void @concat_v128i16(<64 x i16>* %a, <64 x i16>* %b, <128 x i16>* %c) #0 { +; CHECK-LABEL: concat_v128i16: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].h, vl64 +; VBITS_GE_2048-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], [[OP1]].h, [[OP2]].h +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].h, vl128 +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <64 x i16>, <64 x i16>* %a + %op2 = load <64 x i16>, <64 x i16>* %b + %res = shufflevector <64 x i16> %op1, <64 x i16> %op2, <128 x i32> + store <128 x i16> %res, <128 x i16>* %c + ret void +} + +; +; i32 +; + +; Don't use SVE for 64-bit vectors. +define <2 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2) #0 { +; CHECK-LABEL: concat_v2i32: +; CHECK: zip1 v0.2s, v0.2s, v1.2s +; CHECK-NEXT: ret + %res = shufflevector <1 x i32> %op1, <1 x i32> %op2, <2 x i32> + ret <2 x i32> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) #0 { +; CHECK-LABEL: concat_v4i32: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <2 x i32> %op1, <2 x i32> %op2, <4 x i32> + ret <4 x i32> %res +} + +define void @concat_v8i32(<4 x i32>* %a, <4 x i32>* %b, <8 x i32>* %c) #0 { +; CHECK-LABEL: concat_v8i32: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].s, vl4 +; CHECK-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], z[[OP1]].s, z[[OP2]].s +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].s, vl8 +; CHECK-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <4 x i32>, <4 x i32>* %a + %op2 = load <4 x i32>, <4 x i32>* %b + %res = shufflevector <4 x i32> %op1, <4 x i32> %op2, <8 x i32> + store <8 x i32> %res, <8 x i32>* %c + ret void +} + +define void @concat_v16i32(<8 x i32>* %a, <8 x i32>* %b, <16 x i32>* %c) #0 { +; CHECK-LABEL: concat_v16i32: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].s, vl8 +; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], [[OP1]].s, [[OP2]].s +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].s, vl16 +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <8 x i32>, <8 x i32>* %a + %op2 = load <8 x i32>, <8 x i32>* %b + %res = shufflevector <8 x i32> %op1, <8 x i32> %op2, <16 x i32> + store <16 x i32> %res, <16 x i32>* %c + ret void +} + +define void @concat_v32i32(<16 x i32>* %a, <16 x i32>* %b, <32 x i32>* %c) #0 { +; CHECK-LABEL: concat_v32i32: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].s, vl16 +; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], [[OP1]].s, [[OP2]].s +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].s, vl32 +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <16 x i32>, <16 x i32>* %a + %op2 = load <16 x i32>, <16 x i32>* %b + %res = shufflevector <16 x i32> %op1, <16 x i32> %op2, <32 x i32> + store <32 x i32> %res, <32 x i32>* %c + ret void +} + +define void @concat_v64i32(<32 x i32>* %a, <32 x i32>* %b, <64 x i32>* %c) #0 { +; CHECK-LABEL: concat_v64i32: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].s, vl32 +; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], [[OP1]].s, [[OP2]].s +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].s, vl64 +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <32 x i32>, <32 x i32>* %a + %op2 = load <32 x i32>, <32 x i32>* %b + %res = shufflevector <32 x i32> %op1, <32 x i32> %op2, <64 x i32> + store <64 x i32> %res, <64 x i32>* %c + ret void +} + +; +; i64 +; + +; Don't use SVE for 128-bit vectors. +define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2) #0 { +; CHECK-LABEL: concat_v2i64: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <1 x i64> %op1, <1 x i64> %op2, <2 x i32> + ret <2 x i64> %res +} + +define void @concat_v4i64(<2 x i64>* %a, <2 x i64>* %b, <4 x i64>* %c) #0 { +; CHECK-LABEL: concat_v4i64: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].d, vl2 +; CHECK-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], z[[OP1]].d, z[[OP2]].d +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].d, vl4 +; CHECK-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <2 x i64>, <2 x i64>* %a + %op2 = load <2 x i64>, <2 x i64>* %b + %res = shufflevector <2 x i64> %op1, <2 x i64> %op2, <4 x i32> + store <4 x i64> %res, <4 x i64>* %c + ret void +} + +define void @concat_v8i64(<4 x i64>* %a, <4 x i64>* %b, <8 x i64>* %c) #0 { +; CHECK-LABEL: concat_v8i64: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].d, vl4 +; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], [[OP1]].d, [[OP2]].d +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].d, vl8 +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b + %res = shufflevector <4 x i64> %op1, <4 x i64> %op2, <8 x i32> + store <8 x i64> %res, <8 x i64>* %c + ret void +} + +define void @concat_v16i64(<8 x i64>* %a, <8 x i64>* %b, <16 x i64>* %c) #0 { +; CHECK-LABEL: concat_v16i64: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].d, vl8 +; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], [[OP1]].d, [[OP2]].d +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].d, vl16 +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <8 x i64>, <8 x i64>* %a + %op2 = load <8 x i64>, <8 x i64>* %b + %res = shufflevector <8 x i64> %op1, <8 x i64> %op2, <16 x i32> + store <16 x i64> %res, <16 x i64>* %c + ret void +} + +define void @concat_v32i64(<16 x i64>* %a, <16 x i64>* %b, <32 x i64>* %c) #0 { +; CHECK-LABEL: concat_v32i64: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].d, vl16 +; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], [[OP1]].d, [[OP2]].d +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].d, vl32 +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <16 x i64>, <16 x i64>* %a + %op2 = load <16 x i64>, <16 x i64>* %b + %res = shufflevector <16 x i64> %op1, <16 x i64> %op2, <32 x i32> + store <32 x i64> %res, <32 x i64>* %c + ret void +} + +; +; f16 +; + +; Don't use SVE for 64-bit vectors. +define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2) #0 { +; CHECK-LABEL: concat_v4f16: +; CHECK: ext v0.8b, v0.8b, v0.8b, #4 +; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 +; CHECK-NEXT: ret + %res = shufflevector <2 x half> %op1, <2 x half> %op2, <4 x i32> + ret <4 x half> %res +} + +; Don't use SVE for 128-bit vectors. +define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) #0 { +; CHECK-LABEL: concat_v8f16: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <4 x half> %op1, <4 x half> %op2, <8 x i32> + ret <8 x half> %res +} + +define void @concat_v16f16(<8 x half>* %a, <8 x half>* %b, <16 x half>* %c) #0 { +; CHECK-LABEL: concat_v16f16: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].h, vl8 +; CHECK-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], z[[OP1]].h, z[[OP2]].h +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].h, vl16 +; CHECK-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <8 x half>, <8 x half>* %a + %op2 = load <8 x half>, <8 x half>* %b + %res = shufflevector <8 x half> %op1, <8 x half> %op2, <16 x i32> + store <16 x half> %res, <16 x half>* %c + ret void +} + +define void @concat_v32f16(<16 x half>* %a, <16 x half>* %b, <32 x half>* %c) #0 { +; CHECK-LABEL: concat_v32f16: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].h, vl16 +; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], [[OP1]].h, [[OP2]].h +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].h, vl32 +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b + %res = shufflevector <16 x half> %op1, <16 x half> %op2, <32 x i32> + store <32 x half> %res, <32 x half>* %c + ret void +} + +define void @concat_v64f16(<32 x half>* %a, <32 x half>* %b, <64 x half>* %c) #0 { +; CHECK-LABEL: concat_v64f16: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].h, vl32 +; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], [[OP1]].h, [[OP2]].h +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].h, vl64 +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <32 x half>, <32 x half>* %a + %op2 = load <32 x half>, <32 x half>* %b + %res = shufflevector <32 x half> %op1, <32 x half> %op2, <64 x i32> + store <64 x half> %res, <64 x half>* %c + ret void +} + +define void @concat_v128f16(<64 x half>* %a, <64 x half>* %b, <128 x half>* %c) #0 { +; CHECK-LABEL: concat_v128f16: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].h, vl64 +; VBITS_GE_2048-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].h, [[PG1]], [[OP1]].h, [[OP2]].h +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].h, vl128 +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <64 x half>, <64 x half>* %a + %op2 = load <64 x half>, <64 x half>* %b + %res = shufflevector <64 x half> %op1, <64 x half> %op2, <128 x i32> + store <128 x half> %res, <128 x half>* %c + ret void +} + +; +; i32 +; + +; Don't use SVE for 64-bit vectors. +define <2 x float> @concat_v2f32(<1 x float> %op1, <1 x float> %op2) #0 { +; CHECK-LABEL: concat_v2f32: +; CHECK: zip1 v0.2s, v0.2s, v1.2s +; CHECK-NEXT: ret + %res = shufflevector <1 x float> %op1, <1 x float> %op2, <2 x i32> + ret <2 x float> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) #0 { +; CHECK-LABEL: concat_v4f32: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <2 x float> %op1, <2 x float> %op2, <4 x i32> + ret <4 x float> %res +} + +define void @concat_v8f32(<4 x float>* %a, <4 x float>* %b, <8 x float>* %c) #0 { +; CHECK-LABEL: concat_v8f32: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].s, vl4 +; CHECK-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], z[[OP1]].s, z[[OP2]].s +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].s, vl8 +; CHECK-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <4 x float>, <4 x float>* %a + %op2 = load <4 x float>, <4 x float>* %b + %res = shufflevector <4 x float> %op1, <4 x float> %op2, <8 x i32> + store <8 x float> %res, <8 x float>* %c + ret void +} + +define void @concat_v16f32(<8 x float>* %a, <8 x float>* %b, <16 x float>* %c) #0 { +; CHECK-LABEL: concat_v16f32: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].s, vl8 +; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], [[OP1]].s, [[OP2]].s +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].s, vl16 +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b + %res = shufflevector <8 x float> %op1, <8 x float> %op2, <16 x i32> + store <16 x float> %res, <16 x float>* %c + ret void +} + +define void @concat_v32f32(<16 x float>* %a, <16 x float>* %b, <32 x float>* %c) #0 { +; CHECK-LABEL: concat_v32f32: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].s, vl16 +; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], [[OP1]].s, [[OP2]].s +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].s, vl32 +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <16 x float>, <16 x float>* %a + %op2 = load <16 x float>, <16 x float>* %b + %res = shufflevector <16 x float> %op1, <16 x float> %op2, <32 x i32> + store <32 x float> %res, <32 x float>* %c + ret void +} + +define void @concat_v64f32(<32 x float>* %a, <32 x float>* %b, <64 x float>* %c) #0 { +; CHECK-LABEL: concat_v64f32: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].s, vl32 +; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].s, [[PG1]], [[OP1]].s, [[OP2]].s +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].s, vl64 +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <32 x float>, <32 x float>* %a + %op2 = load <32 x float>, <32 x float>* %b + %res = shufflevector <32 x float> %op1, <32 x float> %op2, <64 x i32> + store <64 x float> %res, <64 x float>* %c + ret void +} + +; +; f64 +; + +; Don't use SVE for 128-bit vectors. +define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2) #0 { +; CHECK-LABEL: concat_v2f64: +; CHECK: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %res = shufflevector <1 x double> %op1, <1 x double> %op2, <2 x i32> + ret <2 x double> %res +} + +define void @concat_v4f64(<2 x double>* %a, <2 x double>* %b, <4 x double>* %c) #0 { +; CHECK-LABEL: concat_v4f64: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ldr q[[OP2:[0-9]+]], [x1] +; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].d, vl2 +; CHECK-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], z[[OP1]].d, z[[OP2]].d +; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].d, vl4 +; CHECK-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; CHECK-NEXT: ret + %op1 = load <2 x double>, <2 x double>* %a + %op2 = load <2 x double>, <2 x double>* %b + %res = shufflevector <2 x double> %op1, <2 x double> %op2, <4 x i32> + store <4 x double> %res, <4 x double>* %c + ret void +} + +define void @concat_v8f64(<4 x double>* %a, <4 x double>* %b, <8 x double>* %c) #0 { +; CHECK-LABEL: concat_v8f64: +; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].d, vl4 +; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG1]]/z, [x0] +; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG1]]/z, [x1] +; VBITS_GE_512-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], [[OP1]].d, [[OP2]].d +; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].d, vl8 +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; VBITS_GE_512-NEXT: ret + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b + %res = shufflevector <4 x double> %op1, <4 x double> %op2, <8 x i32> + store <8 x double> %res, <8 x double>* %c + ret void +} + +define void @concat_v16f64(<8 x double>* %a, <8 x double>* %b, <16 x double>* %c) #0 { +; CHECK-LABEL: concat_v16f64: +; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].d, vl8 +; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG1]]/z, [x0] +; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG1]]/z, [x1] +; VBITS_GE_1024-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], [[OP1]].d, [[OP2]].d +; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].d, vl16 +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; VBITS_GE_1024-NEXT: ret + %op1 = load <8 x double>, <8 x double>* %a + %op2 = load <8 x double>, <8 x double>* %b + %res = shufflevector <8 x double> %op1, <8 x double> %op2, <16 x i32> + store <16 x double> %res, <16 x double>* %c + ret void +} + +define void @concat_v32f64(<16 x double>* %a, <16 x double>* %b, <32 x double>* %c) #0 { +; CHECK-LABEL: concat_v32f64: +; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].d, vl16 +; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG1]]/z, [x0] +; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG1]]/z, [x1] +; VBITS_GE_2048-NEXT: splice [[RES:z[0-9]+]].d, [[PG1]], [[OP1]].d, [[OP2]].d +; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].d, vl32 +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG2]], [x2] +; VBITS_GE_2048-NEXT: ret + %op1 = load <16 x double>, <16 x double>* %a + %op2 = load <16 x double>, <16 x double>* %b + %res = shufflevector <16 x double> %op1, <16 x double> %op2, <32 x i32> + store <32 x double> %res, <32 x double>* %c + ret void +} + +; +; undef +; + +define void @concat_v32i8_undef(<16 x i8>* %a, <32 x i8>* %b) #0 { +; CHECK-LABEL: concat_v32i8_undef: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ptrue [[PG:p[0-9]+]].b, vl32 +; CHECK-NEXT: st1b { z[[OP1]].b }, [[PG]], [x1] +; CHECK-NEXT: ret + %op1 = load <16 x i8>, <16 x i8>* %a + %res = shufflevector <16 x i8> %op1, <16 x i8> undef, <32 x i32> + store <32 x i8> %res, <32 x i8>* %b + ret void +} + +define void @concat_v16i16_undef(<8 x i16>* %a, <16 x i16>* %b) #0 { +; CHECK-LABEL: concat_v16i16_undef: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ptrue [[PG:p[0-9]+]].h, vl16 +; CHECK-NEXT: st1h { z[[OP1]].h }, [[PG]], [x1] +; CHECK-NEXT: ret + %op1 = load <8 x i16>, <8 x i16>* %a + %res = shufflevector <8 x i16> %op1, <8 x i16> undef, <16 x i32> + store <16 x i16> %res, <16 x i16>* %b + ret void +} + +define void @concat_v8i32_undef(<4 x i32>* %a, <8 x i32>* %b) #0 { +; CHECK-LABEL: concat_v8i32_undef: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ptrue [[PG:p[0-9]+]].s, vl8 +; CHECK-NEXT: st1w { z[[OP1]].s }, [[PG]], [x1] +; CHECK-NEXT: ret + %op1 = load <4 x i32>, <4 x i32>* %a + %res = shufflevector <4 x i32> %op1, <4 x i32> undef, <8 x i32> + store <8 x i32> %res, <8 x i32>* %b + ret void +} + +define void @concat_v4i64_undef(<2 x i64>* %a, <4 x i64>* %b) #0 { +; CHECK-LABEL: concat_v4i64_undef: +; CHECK: ldr q[[OP1:[0-9]+]], [x0] +; CHECK-NEXT: ptrue [[PG:p[0-9]+]].d, vl4 +; CHECK-NEXT: st1d { z[[OP1]].d }, [[PG]], [x1] +; CHECK-NEXT: ret + %op1 = load <2 x i64>, <2 x i64>* %a + %res = shufflevector <2 x i64> %op1, <2 x i64> undef, <4 x i32> + store <4 x i64> %res, <4 x i64>* %b + ret void +} + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll @@ -1,5 +1,4 @@ ; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 target triple = "aarch64-unknown-linux-gnu" @@ -15,36 +14,4 @@ ret void } -; NOTE: Currently all CONCAT_VECTORS get expanded so there's little point in -; validating all combinations of vector type. - -define void @concat_vectors_v4i64(<2 x i64> %a, <2 x i64> %b, <4 x i64> *%c.addr) #0 { -; CHECK-LABEL: concat_vectors_v4i64: -; CHECK: stp q0, q1, [sp] -; CHECK: ptrue [[OUT_PG:p[0-9]+]].d, vl4 -; CHECK: mov x[[LO_ADDR:[0-9]+]], sp -; CHECK: ld1d { z{{[0-9]+}}.d }, [[OUT_PG]]/z, [x[[LO_ADDR]]] - %concat = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> - store <4 x i64> %concat, <4 x i64>* %c.addr - ret void -} - -define void @concat_vectors_v8i64(<4 x i64> *%a.addr, <4 x i64> *%b.addr, <8 x i64> *%c.addr) #0 { -; VBITS_GE_512-LABEL: concat_vectors_v8i64: -; VBITS_GE_512: ptrue [[IN_PG:p[0-9]+]].d, vl4 -; VBITS_GE_512: ld1d { [[LO:z[0-9]+]].d }, [[IN_PG]]/z, [x0] -; VBITS_GE_512: ld1d { [[HI:z[0-9]+]].d }, [[IN_PG]]/z, [x1] -; VBITS_GE_512: mov x[[LO_ADDR:[0-9]+]], sp -; VBITS_GE_512: orr x[[HI_ADDR:[0-9]+]], x[[LO_ADDR]], #0x20 -; VBITS_GE_512: st1d { [[LO]].d }, [[IN_PG]], [x[[LO_ADDR]]] -; VBITS_GE_512: st1d { [[HI]].d }, [[IN_PG]], [x[[HI_ADDR]]] -; VBITS_GE_512: ptrue [[OUT_PG:p[0-9]+]].d, vl8 -; VBITS_GE_512: ld1d { z{{[0-9]+}}.d }, [[OUT_PG]]/z, [x8] - %a = load <4 x i64>, <4 x i64>* %a.addr - %b = load <4 x i64>, <4 x i64>* %b.addr - %concat = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> - store <8 x i64> %concat, <8 x i64>* %c.addr - ret void -} - attributes #0 = { nounwind "target-features"="+sve" }