diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -812,6 +812,8 @@
       for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
         setOperationAction(Opc, VT, Expand);
 
+      setOperationAction(ISD::ADD, VT, Legal);
+      setOperationAction(ISD::SUB, VT, Legal);
       setOperationAction(ISD::BITCAST, VT, Legal);
 
       // Promote load and store operations.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1225,3 +1225,21 @@
 
 let Predicates = [HasStdExtP] in
 def : RVPTernaryINSBPat<INSB, "insb">;
+
+//===----------------------------------------------------------------------===//
+// Codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtP] in {
+class PatALU8<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI8VT (OpNode GPR:$rs1, GPR:$rs2)),
+          (Inst GPR:$rs1, GPR:$rs2)>;
+class PatALU16<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI16VT (OpNode GPR:$rs1, GPR:$rs2)),
+          (Inst GPR:$rs1, GPR:$rs2)>;
+
+def : PatALU8<add, ADD8>;
+def : PatALU8<sub, SUB8>;
+def : PatALU16<add, ADD16>;
+def : PatALU16<sub, SUB16>;
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp/alu-rv32.ll b/llvm/test/CodeGen/RISCV/rvp/alu-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvp/alu-rv32.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define i32 @addv4i8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: addv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add8 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %add = add <4 x i8> %tmp1, %tmp2
+  %res = bitcast <4 x i8> %add to i32
+  ret i32 %res
+}
+
+define i32 @subv4i8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: subv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub8 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <4 x i8>
+  %tmp2 = bitcast i32 %b to <4 x i8>
+  %sub = sub <4 x i8> %tmp1, %tmp2
+  %res = bitcast <4 x i8> %sub to i32
+  ret i32 %res
+}
+
+define i32 @addv2i16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: addv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add16 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %add = add <2 x i16> %tmp1, %tmp2
+  %res = bitcast <2 x i16> %add to i32
+  ret i32 %res
+}
+
+define i32 @subv2i16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: subv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub16 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i32 %a to <2 x i16>
+  %tmp2 = bitcast i32 %b to <2 x i16>
+  %sub = sub <2 x i16> %tmp1, %tmp2
+  %res = bitcast <2 x i16> %sub to i32
+  ret i32 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp/alu-rv64.ll b/llvm/test/CodeGen/RISCV/rvp/alu-rv64.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvp/alu-rv64.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define i64 @addv8i8(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: addv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add8 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %add = add <8 x i8> %tmp1, %tmp2
+  %res = bitcast <8 x i8> %add to i64
+  ret i64 %res
+}
+
+define i64 @subv8i8(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: subv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub8 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <8 x i8>
+  %tmp2 = bitcast i64 %b to <8 x i8>
+  %sub = sub <8 x i8> %tmp1, %tmp2
+  %res = bitcast <8 x i8> %sub to i64
+  ret i64 %res
+}
+
+define i64 @addv4i16(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: addv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add16 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %add = add <4 x i16> %tmp1, %tmp2
+  %res = bitcast <4 x i16> %add to i64
+  ret i64 %res
+}
+
+define i64 @subv4i16(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: subv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub16 a0, a0, a1
+; CHECK-NEXT:    ret
+  %tmp1 = bitcast i64 %a to <4 x i16>
+  %tmp2 = bitcast i64 %b to <4 x i16>
+  %sub = sub <4 x i16> %tmp1, %tmp2
+  %res = bitcast <4 x i16> %sub to i64
+  ret i64 %res
+}