diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -318,6 +318,9 @@
   shouldExpandBuildVectorWithShuffles(EVT VT,
                                       unsigned DefinedValues) const override;
 
+  TargetLoweringBase::LegalizeTypeAction
+  getPreferredVectorAction(MVT VT) const override;
+
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -827,6 +827,11 @@
       for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
         setOperationAction(Opc, VT, Expand);
 
+      setOperationAction(ISD::ADD, VT, Legal);
+      setOperationAction(ISD::SUB, VT, Legal);
+      setOperationAction(ISD::AND, VT, Legal);
+      setOperationAction(ISD::OR, VT, Legal);
+      setOperationAction(ISD::XOR, VT, Legal);
       setOperationAction(ISD::BITCAST, VT, Legal);
 
       // Promote load and store operations.
@@ -8739,6 +8744,15 @@
   return SDValue();
 }
 
+TargetLoweringBase::LegalizeTypeAction
+RISCVTargetLowering::getPreferredVectorAction(MVT VT) const {
+  // For RV64P, v4i8 and v2i16 can be widened to v8i8 and v4i16 as legal types.
+  if (Subtarget.hasStdExtZpn() && (VT == MVT::v4i8 || VT == MVT::v2i16))
+    return TypeWidenVector;
+
+  return TargetLoweringBase::getPreferredVectorAction(VT);
+}
+
 #define GET_REGISTER_MATCHER
 #include "RISCVGenAsmMatcher.inc"
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1226,3 +1226,59 @@
 
 let Predicates = [HasStdExtZpn] in
 def : RVPTernaryINSBPat<INSB, "insb">;
+
+//===----------------------------------------------------------------------===//
+// Codegen patterns
+//===----------------------------------------------------------------------===//
+
+class PatALU8<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI8VT (OpNode GPR:$rs1, GPR:$rs2)),
+          (Inst GPR:$rs1, GPR:$rs2)>;
+class PatALU16<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI16VT (OpNode GPR:$rs1, GPR:$rs2)),
+          (Inst GPR:$rs1, GPR:$rs2)>;
+class PatALU32<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI32VT (OpNode GPR:$rs1, GPR:$rs2)),
+          (Inst GPR:$rs1, GPR:$rs2)>;
+class PatALU8I<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI8VT (OpNode GPR:$rs1, (bitconvert simm12:$imm))),
+          (Inst GPR:$rs1, simm12:$imm)>;
+class PatALU16I<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI16VT (OpNode GPR:$rs1, (bitconvert simm12:$imm))),
+          (Inst GPR:$rs1, simm12:$imm)>;
+class PatALU32I<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XVEI32VT (OpNode GPR:$rs1, (bitconvert simm12:$imm))),
+          (Inst GPR:$rs1, simm12:$imm)>;
+
+// ALU operations
+let Predicates = [HasStdExtZpn] in {
+def : PatALU8<add, ADD8>;
+def : PatALU8<sub, SUB8>;
+def : PatALU8<and, AND>;
+def : PatALU8<or, OR>;
+def : PatALU8<xor, XOR>;
+def : PatALU16<add, ADD16>;
+def : PatALU16<sub, SUB16>;
+def : PatALU16<and, AND>;
+def : PatALU16<or, OR>;
+def : PatALU16<xor, XOR>;
+
+def : PatALU8I<and, ANDI>;
+def : PatALU8I<or, ORI>;
+def : PatALU8I<xor, XORI>;
+def : PatALU16I<and, ANDI>;
+def : PatALU16I<or, ORI>;
+def : PatALU16I<xor, XORI>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZpn, IsRV64] in {
+def : PatALU32<add, ADD32>;
+def : PatALU32<sub, SUB32>;
+def : PatALU32<and, AND>;
+def : PatALU32<or, OR>;
+def : PatALU32<xor, XOR>;
+
+def : PatALU32I<and, ANDI>;
+def : PatALU32I<or, ORI>;
+def : PatALU32I<xor, XORI>;
+} // [HasStdExtZpn, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/rv32zpn-alu.ll b/llvm/test/CodeGen/RISCV/rv32zpn-alu.ll
--- a/llvm/test/CodeGen/RISCV/rv32zpn-alu.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zpn-alu.ll
@@ -7,52 +7,12 @@
 define i32 @addv4i8(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: addv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    lb a1, 7(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 10(sp)
-; RV32IP-NEXT:    lb a1, 6(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 9(sp)
-; RV32IP-NEXT:    lb a1, 5(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 8(sp)
-; RV32IP-NEXT:    lb a1, 4(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add8 a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: addv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    lb a1, 7(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 10(sp)
-; RV32IPN-NEXT:    lb a1, 6(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 9(sp)
-; RV32IPN-NEXT:    lb a1, 5(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 8(sp)
-; RV32IPN-NEXT:    lb a1, 4(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add8 a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -64,36 +24,12 @@
 define i32 @addv2i16(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: addv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lh a0, 10(sp)
-; RV32IP-NEXT:    lh a1, 6(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    lh a1, 4(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add16 a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: addv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lh a0, 10(sp)
-; RV32IPN-NEXT:    lh a1, 6(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    lh a1, 4(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add16 a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -105,90 +41,14 @@
 define i64 @addv8i8(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: addv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    lb a0, 19(sp)
-; RV32IP-NEXT:    lb a1, 11(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 27(sp)
-; RV32IP-NEXT:    lb a0, 18(sp)
-; RV32IP-NEXT:    lb a1, 10(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 26(sp)
-; RV32IP-NEXT:    lb a0, 17(sp)
-; RV32IP-NEXT:    lb a1, 9(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 25(sp)
-; RV32IP-NEXT:    lb a0, 16(sp)
-; RV32IP-NEXT:    lb a1, 8(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 24(sp)
-; RV32IP-NEXT:    lb a0, 23(sp)
-; RV32IP-NEXT:    lb a1, 15(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 31(sp)
-; RV32IP-NEXT:    lb a0, 22(sp)
-; RV32IP-NEXT:    lb a1, 14(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 30(sp)
-; RV32IP-NEXT:    lb a0, 21(sp)
-; RV32IP-NEXT:    lb a1, 13(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 29(sp)
-; RV32IP-NEXT:    lb a0, 20(sp)
-; RV32IP-NEXT:    lb a1, 12(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 24(sp)
-; RV32IP-NEXT:    lw a1, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    add8 a1, a1, a3
+; RV32IP-NEXT:    add8 a0, a0, a2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: addv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    lb a0, 19(sp)
-; RV32IPN-NEXT:    lb a1, 11(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 27(sp)
-; RV32IPN-NEXT:    lb a0, 18(sp)
-; RV32IPN-NEXT:    lb a1, 10(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 26(sp)
-; RV32IPN-NEXT:    lb a0, 17(sp)
-; RV32IPN-NEXT:    lb a1, 9(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 25(sp)
-; RV32IPN-NEXT:    lb a0, 16(sp)
-; RV32IPN-NEXT:    lb a1, 8(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 24(sp)
-; RV32IPN-NEXT:    lb a0, 23(sp)
-; RV32IPN-NEXT:    lb a1, 15(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 31(sp)
-; RV32IPN-NEXT:    lb a0, 22(sp)
-; RV32IPN-NEXT:    lb a1, 14(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 30(sp)
-; RV32IPN-NEXT:    lb a0, 21(sp)
-; RV32IPN-NEXT:    lb a1, 13(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 29(sp)
-; RV32IPN-NEXT:    lb a0, 20(sp)
-; RV32IPN-NEXT:    lb a1, 12(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 24(sp)
-; RV32IPN-NEXT:    lw a1, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    add8 a1, a1, a3
+; RV32IPN-NEXT:    add8 a0, a0, a2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -200,58 +60,14 @@
 define i64 @addv4i16(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: addv4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    lh a0, 18(sp)
-; RV32IP-NEXT:    lh a1, 10(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 26(sp)
-; RV32IP-NEXT:    lh a0, 16(sp)
-; RV32IP-NEXT:    lh a1, 8(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 24(sp)
-; RV32IP-NEXT:    lh a0, 22(sp)
-; RV32IP-NEXT:    lh a1, 14(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 30(sp)
-; RV32IP-NEXT:    lh a0, 20(sp)
-; RV32IP-NEXT:    lh a1, 12(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 24(sp)
-; RV32IP-NEXT:    lw a1, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    add16 a1, a1, a3
+; RV32IP-NEXT:    add16 a0, a0, a2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: addv4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    lh a0, 18(sp)
-; RV32IPN-NEXT:    lh a1, 10(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 26(sp)
-; RV32IPN-NEXT:    lh a0, 16(sp)
-; RV32IPN-NEXT:    lh a1, 8(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 24(sp)
-; RV32IPN-NEXT:    lh a0, 22(sp)
-; RV32IPN-NEXT:    lh a1, 14(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 30(sp)
-; RV32IPN-NEXT:    lh a0, 20(sp)
-; RV32IPN-NEXT:    lh a1, 12(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 24(sp)
-; RV32IPN-NEXT:    lw a1, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    add16 a1, a1, a3
+; RV32IPN-NEXT:    add16 a0, a0, a2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -282,52 +98,12 @@
 define i32 @subv4i8(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: subv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    lb a1, 7(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 10(sp)
-; RV32IP-NEXT:    lb a1, 6(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 9(sp)
-; RV32IP-NEXT:    lb a1, 5(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 8(sp)
-; RV32IP-NEXT:    lb a1, 4(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    sub8 a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: subv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    lb a1, 7(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 10(sp)
-; RV32IPN-NEXT:    lb a1, 6(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 9(sp)
-; RV32IPN-NEXT:    lb a1, 5(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 8(sp)
-; RV32IPN-NEXT:    lb a1, 4(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    sub8 a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -339,36 +115,12 @@
 define i32 @subv2i16(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: subv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lh a0, 10(sp)
-; RV32IP-NEXT:    lh a1, 6(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    lh a1, 4(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    sub16 a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: subv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lh a0, 10(sp)
-; RV32IPN-NEXT:    lh a1, 6(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    lh a1, 4(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    sub16 a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -380,90 +132,14 @@
 define i64 @subv8i8(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: subv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    lb a0, 19(sp)
-; RV32IP-NEXT:    lb a1, 11(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 27(sp)
-; RV32IP-NEXT:    lb a0, 18(sp)
-; RV32IP-NEXT:    lb a1, 10(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 26(sp)
-; RV32IP-NEXT:    lb a0, 17(sp)
-; RV32IP-NEXT:    lb a1, 9(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 25(sp)
-; RV32IP-NEXT:    lb a0, 16(sp)
-; RV32IP-NEXT:    lb a1, 8(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 24(sp)
-; RV32IP-NEXT:    lb a0, 23(sp)
-; RV32IP-NEXT:    lb a1, 15(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 31(sp)
-; RV32IP-NEXT:    lb a0, 22(sp)
-; RV32IP-NEXT:    lb a1, 14(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 30(sp)
-; RV32IP-NEXT:    lb a0, 21(sp)
-; RV32IP-NEXT:    lb a1, 13(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 29(sp)
-; RV32IP-NEXT:    lb a0, 20(sp)
-; RV32IP-NEXT:    lb a1, 12(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sb a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 24(sp)
-; RV32IP-NEXT:    lw a1, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    sub8 a1, a1, a3
+; RV32IP-NEXT:    sub8 a0, a0, a2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: subv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    lb a0, 19(sp)
-; RV32IPN-NEXT:    lb a1, 11(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 27(sp)
-; RV32IPN-NEXT:    lb a0, 18(sp)
-; RV32IPN-NEXT:    lb a1, 10(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 26(sp)
-; RV32IPN-NEXT:    lb a0, 17(sp)
-; RV32IPN-NEXT:    lb a1, 9(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 25(sp)
-; RV32IPN-NEXT:    lb a0, 16(sp)
-; RV32IPN-NEXT:    lb a1, 8(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 24(sp)
-; RV32IPN-NEXT:    lb a0, 23(sp)
-; RV32IPN-NEXT:    lb a1, 15(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 31(sp)
-; RV32IPN-NEXT:    lb a0, 22(sp)
-; RV32IPN-NEXT:    lb a1, 14(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 30(sp)
-; RV32IPN-NEXT:    lb a0, 21(sp)
-; RV32IPN-NEXT:    lb a1, 13(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 29(sp)
-; RV32IPN-NEXT:    lb a0, 20(sp)
-; RV32IPN-NEXT:    lb a1, 12(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 24(sp)
-; RV32IPN-NEXT:    lw a1, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    sub8 a1, a1, a3
+; RV32IPN-NEXT:    sub8 a0, a0, a2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -475,58 +151,14 @@
 define i64 @subv4i16(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: subv4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    lh a0, 18(sp)
-; RV32IP-NEXT:    lh a1, 10(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sh a0, 26(sp)
-; RV32IP-NEXT:    lh a0, 16(sp)
-; RV32IP-NEXT:    lh a1, 8(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sh a0, 24(sp)
-; RV32IP-NEXT:    lh a0, 22(sp)
-; RV32IP-NEXT:    lh a1, 14(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sh a0, 30(sp)
-; RV32IP-NEXT:    lh a0, 20(sp)
-; RV32IP-NEXT:    lh a1, 12(sp)
-; RV32IP-NEXT:    sub a0, a1, a0
-; RV32IP-NEXT:    sh a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 24(sp)
-; RV32IP-NEXT:    lw a1, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    sub16 a1, a1, a3
+; RV32IP-NEXT:    sub16 a0, a0, a2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: subv4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    lh a0, 18(sp)
-; RV32IPN-NEXT:    lh a1, 10(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 26(sp)
-; RV32IPN-NEXT:    lh a0, 16(sp)
-; RV32IPN-NEXT:    lh a1, 8(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 24(sp)
-; RV32IPN-NEXT:    lh a0, 22(sp)
-; RV32IPN-NEXT:    lh a1, 14(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 30(sp)
-; RV32IPN-NEXT:    lh a0, 20(sp)
-; RV32IPN-NEXT:    lh a1, 12(sp)
-; RV32IPN-NEXT:    sub a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 24(sp)
-; RV32IPN-NEXT:    lw a1, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    sub16 a1, a1, a3
+; RV32IPN-NEXT:    sub16 a0, a0, a2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -557,42 +189,16 @@
 define i32 @andv4i8(i32 %a) nounwind {
 ; RV32IP-LABEL: andv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lbu a0, 11(sp)
-; RV32IP-NEXT:    andi a0, a0, 4
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lbu a0, 10(sp)
-; RV32IP-NEXT:    andi a0, a0, 3
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lbu a0, 9(sp)
-; RV32IP-NEXT:    andi a0, a0, 2
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lbu a0, 8(sp)
-; RV32IP-NEXT:    andi a0, a0, 1
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
+; RV32IP-NEXT:    and a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lbu a0, 11(sp)
-; RV32IPN-NEXT:    andi a0, a0, 4
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lbu a0, 10(sp)
-; RV32IPN-NEXT:    andi a0, a0, 3
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lbu a0, 9(sp)
-; RV32IPN-NEXT:    andi a0, a0, 2
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lbu a0, 8(sp)
-; RV32IPN-NEXT:    andi a0, a0, 1
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
+; RV32IPN-NEXT:    and a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <4 x i8>
   %and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
@@ -603,30 +209,16 @@
 define i32 @andv2i16(i32 %a) nounwind {
 ; RV32IP-LABEL: andv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lhu a0, 10(sp)
-; RV32IP-NEXT:    andi a0, a0, 2
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lhu a0, 8(sp)
-; RV32IP-NEXT:    andi a0, a0, 1
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI11_0)(a1)
+; RV32IP-NEXT:    and a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lhu a0, 10(sp)
-; RV32IPN-NEXT:    andi a0, a0, 2
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lhu a0, 8(sp)
-; RV32IPN-NEXT:    andi a0, a0, 1
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI11_0)(a1)
+; RV32IPN-NEXT:    and a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <2 x i16>
   %and = and <2 x i16> %tmp, <i16 1, i16 2>
@@ -637,70 +229,22 @@
 define i64 @andv8i8(i64 %a) nounwind {
 ; RV32IP-LABEL: andv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 0(sp)
-; RV32IP-NEXT:    sw a1, 4(sp)
-; RV32IP-NEXT:    lbu a0, 3(sp)
-; RV32IP-NEXT:    andi a0, a0, 4
-; RV32IP-NEXT:    sb a0, 11(sp)
-; RV32IP-NEXT:    lbu a0, 2(sp)
-; RV32IP-NEXT:    andi a0, a0, 3
-; RV32IP-NEXT:    sb a0, 10(sp)
-; RV32IP-NEXT:    lbu a0, 1(sp)
-; RV32IP-NEXT:    andi a0, a0, 2
-; RV32IP-NEXT:    sb a0, 9(sp)
-; RV32IP-NEXT:    lbu a0, 0(sp)
-; RV32IP-NEXT:    andi a0, a0, 1
-; RV32IP-NEXT:    sb a0, 8(sp)
-; RV32IP-NEXT:    lbu a0, 7(sp)
-; RV32IP-NEXT:    andi a0, a0, 8
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lbu a0, 6(sp)
-; RV32IP-NEXT:    andi a0, a0, 7
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lbu a0, 5(sp)
-; RV32IP-NEXT:    andi a0, a0, 6
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lbu a0, 4(sp)
-; RV32IP-NEXT:    andi a0, a0, 5
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 8(sp)
-; RV32IP-NEXT:    lw a1, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IP-NEXT:    lw a2, %lo(.LCPI12_0)(a2)
+; RV32IP-NEXT:    lui a3, %hi(.LCPI12_1)
+; RV32IP-NEXT:    lw a3, %lo(.LCPI12_1)(a3)
+; RV32IP-NEXT:    and a1, a1, a2
+; RV32IP-NEXT:    and a0, a0, a3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 0(sp)
-; RV32IPN-NEXT:    sw a1, 4(sp)
-; RV32IPN-NEXT:    lbu a0, 3(sp)
-; RV32IPN-NEXT:    andi a0, a0, 4
-; RV32IPN-NEXT:    sb a0, 11(sp)
-; RV32IPN-NEXT:    lbu a0, 2(sp)
-; RV32IPN-NEXT:    andi a0, a0, 3
-; RV32IPN-NEXT:    sb a0, 10(sp)
-; RV32IPN-NEXT:    lbu a0, 1(sp)
-; RV32IPN-NEXT:    andi a0, a0, 2
-; RV32IPN-NEXT:    sb a0, 9(sp)
-; RV32IPN-NEXT:    lbu a0, 0(sp)
-; RV32IPN-NEXT:    andi a0, a0, 1
-; RV32IPN-NEXT:    sb a0, 8(sp)
-; RV32IPN-NEXT:    lbu a0, 7(sp)
-; RV32IPN-NEXT:    andi a0, a0, 8
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lbu a0, 6(sp)
-; RV32IPN-NEXT:    andi a0, a0, 7
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lbu a0, 5(sp)
-; RV32IPN-NEXT:    andi a0, a0, 6
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lbu a0, 4(sp)
-; RV32IPN-NEXT:    andi a0, a0, 5
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 8(sp)
-; RV32IPN-NEXT:    lw a1, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IPN-NEXT:    lw a2, %lo(.LCPI12_0)(a2)
+; RV32IPN-NEXT:    lui a3, %hi(.LCPI12_1)
+; RV32IPN-NEXT:    lw a3, %lo(.LCPI12_1)(a3)
+; RV32IPN-NEXT:    and a1, a1, a2
+; RV32IPN-NEXT:    and a0, a0, a3
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <8 x i8>
   %and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
@@ -711,46 +255,22 @@
 define i64 @andv4i16(i64 %a) nounwind {
 ; RV32IP-LABEL: andv4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 0(sp)
-; RV32IP-NEXT:    sw a1, 4(sp)
-; RV32IP-NEXT:    lhu a0, 2(sp)
-; RV32IP-NEXT:    andi a0, a0, 2
-; RV32IP-NEXT:    sh a0, 10(sp)
-; RV32IP-NEXT:    lhu a0, 0(sp)
-; RV32IP-NEXT:    andi a0, a0, 1
-; RV32IP-NEXT:    sh a0, 8(sp)
-; RV32IP-NEXT:    lhu a0, 6(sp)
-; RV32IP-NEXT:    andi a0, a0, 4
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lhu a0, 4(sp)
-; RV32IP-NEXT:    andi a0, a0, 3
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 8(sp)
-; RV32IP-NEXT:    lw a1, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a2, %hi(.LCPI13_0)
+; RV32IP-NEXT:    lw a2, %lo(.LCPI13_0)(a2)
+; RV32IP-NEXT:    lui a3, %hi(.LCPI13_1)
+; RV32IP-NEXT:    lw a3, %lo(.LCPI13_1)(a3)
+; RV32IP-NEXT:    and a1, a1, a2
+; RV32IP-NEXT:    and a0, a0, a3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andv4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 0(sp)
-; RV32IPN-NEXT:    sw a1, 4(sp)
-; RV32IPN-NEXT:    lhu a0, 2(sp)
-; RV32IPN-NEXT:    andi a0, a0, 2
-; RV32IPN-NEXT:    sh a0, 10(sp)
-; RV32IPN-NEXT:    lhu a0, 0(sp)
-; RV32IPN-NEXT:    andi a0, a0, 1
-; RV32IPN-NEXT:    sh a0, 8(sp)
-; RV32IPN-NEXT:    lhu a0, 6(sp)
-; RV32IPN-NEXT:    andi a0, a0, 4
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lhu a0, 4(sp)
-; RV32IPN-NEXT:    andi a0, a0, 3
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 8(sp)
-; RV32IPN-NEXT:    lw a1, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a2, %hi(.LCPI13_0)
+; RV32IPN-NEXT:    lw a2, %lo(.LCPI13_0)(a2)
+; RV32IPN-NEXT:    lui a3, %hi(.LCPI13_1)
+; RV32IPN-NEXT:    lw a3, %lo(.LCPI13_1)(a3)
+; RV32IPN-NEXT:    and a1, a1, a2
+; RV32IPN-NEXT:    and a0, a0, a3
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <4 x i16>
   %and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
@@ -779,42 +299,16 @@
 define i32 @orv4i8(i32 %a) nounwind {
 ; RV32IP-LABEL: orv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    ori a0, a0, 4
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 10(sp)
-; RV32IP-NEXT:    ori a0, a0, 3
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 9(sp)
-; RV32IP-NEXT:    ori a0, a0, 2
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 8(sp)
-; RV32IP-NEXT:    ori a0, a0, 1
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI15_0)(a1)
+; RV32IP-NEXT:    or a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: orv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    ori a0, a0, 4
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 10(sp)
-; RV32IPN-NEXT:    ori a0, a0, 3
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 9(sp)
-; RV32IPN-NEXT:    ori a0, a0, 2
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 8(sp)
-; RV32IPN-NEXT:    ori a0, a0, 1
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI15_0)(a1)
+; RV32IPN-NEXT:    or a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <4 x i8>
   %or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
@@ -825,30 +319,16 @@
 define i32 @orv2i16(i32 %a) nounwind {
 ; RV32IP-LABEL: orv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lh a0, 10(sp)
-; RV32IP-NEXT:    ori a0, a0, 2
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    ori a0, a0, 1
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI16_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI16_0)(a1)
+; RV32IP-NEXT:    or a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: orv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lh a0, 10(sp)
-; RV32IPN-NEXT:    ori a0, a0, 2
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    ori a0, a0, 1
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI16_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI16_0)(a1)
+; RV32IPN-NEXT:    or a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <2 x i16>
   %or = or <2 x i16> %tmp, <i16 1, i16 2>
@@ -859,70 +339,22 @@
 define i64 @orv8i8(i64 %a) nounwind {
 ; RV32IP-LABEL: orv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 0(sp)
-; RV32IP-NEXT:    sw a1, 4(sp)
-; RV32IP-NEXT:    lb a0, 3(sp)
-; RV32IP-NEXT:    ori a0, a0, 4
-; RV32IP-NEXT:    sb a0, 11(sp)
-; RV32IP-NEXT:    lb a0, 2(sp)
-; RV32IP-NEXT:    ori a0, a0, 3
-; RV32IP-NEXT:    sb a0, 10(sp)
-; RV32IP-NEXT:    lb a0, 1(sp)
-; RV32IP-NEXT:    ori a0, a0, 2
-; RV32IP-NEXT:    sb a0, 9(sp)
-; RV32IP-NEXT:    lb a0, 0(sp)
-; RV32IP-NEXT:    ori a0, a0, 1
-; RV32IP-NEXT:    sb a0, 8(sp)
-; RV32IP-NEXT:    lb a0, 7(sp)
-; RV32IP-NEXT:    ori a0, a0, 8
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 6(sp)
-; RV32IP-NEXT:    ori a0, a0, 7
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 5(sp)
-; RV32IP-NEXT:    ori a0, a0, 6
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 4(sp)
-; RV32IP-NEXT:    ori a0, a0, 5
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 8(sp)
-; RV32IP-NEXT:    lw a1, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a2, %hi(.LCPI17_0)
+; RV32IP-NEXT:    lw a2, %lo(.LCPI17_0)(a2)
+; RV32IP-NEXT:    lui a3, %hi(.LCPI17_1)
+; RV32IP-NEXT:    lw a3, %lo(.LCPI17_1)(a3)
+; RV32IP-NEXT:    or a1, a1, a2
+; RV32IP-NEXT:    or a0, a0, a3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: orv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 0(sp)
-; RV32IPN-NEXT:    sw a1, 4(sp)
-; RV32IPN-NEXT:    lb a0, 3(sp)
-; RV32IPN-NEXT:    ori a0, a0, 4
-; RV32IPN-NEXT:    sb a0, 11(sp)
-; RV32IPN-NEXT:    lb a0, 2(sp)
-; RV32IPN-NEXT:    ori a0, a0, 3
-; RV32IPN-NEXT:    sb a0, 10(sp)
-; RV32IPN-NEXT:    lb a0, 1(sp)
-; RV32IPN-NEXT:    ori a0, a0, 2
-; RV32IPN-NEXT:    sb a0, 9(sp)
-; RV32IPN-NEXT:    lb a0, 0(sp)
-; RV32IPN-NEXT:    ori a0, a0, 1
-; RV32IPN-NEXT:    sb a0, 8(sp)
-; RV32IPN-NEXT:    lb a0, 7(sp)
-; RV32IPN-NEXT:    ori a0, a0, 8
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 6(sp)
-; RV32IPN-NEXT:    ori a0, a0, 7
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 5(sp)
-; RV32IPN-NEXT:    ori a0, a0, 6
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 4(sp)
-; RV32IPN-NEXT:    ori a0, a0, 5
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 8(sp)
-; RV32IPN-NEXT:    lw a1, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a2, %hi(.LCPI17_0)
+; RV32IPN-NEXT:    lw a2, %lo(.LCPI17_0)(a2)
+; RV32IPN-NEXT:    lui a3, %hi(.LCPI17_1)
+; RV32IPN-NEXT:    lw a3, %lo(.LCPI17_1)(a3)
+; RV32IPN-NEXT:    or a1, a1, a2
+; RV32IPN-NEXT:    or a0, a0, a3
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <8 x i8>
   %or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
@@ -933,46 +365,22 @@
 define i64 @orv4i16(i64 %a) nounwind {
 ; RV32IP-LABEL: orv4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 0(sp)
-; RV32IP-NEXT:    sw a1, 4(sp)
-; RV32IP-NEXT:    lh a0, 2(sp)
-; RV32IP-NEXT:    ori a0, a0, 2
-; RV32IP-NEXT:    sh a0, 10(sp)
-; RV32IP-NEXT:    lh a0, 0(sp)
-; RV32IP-NEXT:    ori a0, a0, 1
-; RV32IP-NEXT:    sh a0, 8(sp)
-; RV32IP-NEXT:    lh a0, 6(sp)
-; RV32IP-NEXT:    ori a0, a0, 4
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lh a0, 4(sp)
-; RV32IP-NEXT:    ori a0, a0, 3
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 8(sp)
-; RV32IP-NEXT:    lw a1, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a2, %hi(.LCPI18_0)
+; RV32IP-NEXT:    lw a2, %lo(.LCPI18_0)(a2)
+; RV32IP-NEXT:    lui a3, %hi(.LCPI18_1)
+; RV32IP-NEXT:    lw a3, %lo(.LCPI18_1)(a3)
+; RV32IP-NEXT:    or a1, a1, a2
+; RV32IP-NEXT:    or a0, a0, a3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: orv4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 0(sp)
-; RV32IPN-NEXT:    sw a1, 4(sp)
-; RV32IPN-NEXT:    lh a0, 2(sp)
-; RV32IPN-NEXT:    ori a0, a0, 2
-; RV32IPN-NEXT:    sh a0, 10(sp)
-; RV32IPN-NEXT:    lh a0, 0(sp)
-; RV32IPN-NEXT:    ori a0, a0, 1
-; RV32IPN-NEXT:    sh a0, 8(sp)
-; RV32IPN-NEXT:    lh a0, 6(sp)
-; RV32IPN-NEXT:    ori a0, a0, 4
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lh a0, 4(sp)
-; RV32IPN-NEXT:    ori a0, a0, 3
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 8(sp)
-; RV32IPN-NEXT:    lw a1, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a2, %hi(.LCPI18_0)
+; RV32IPN-NEXT:    lw a2, %lo(.LCPI18_0)(a2)
+; RV32IPN-NEXT:    lui a3, %hi(.LCPI18_1)
+; RV32IPN-NEXT:    lw a3, %lo(.LCPI18_1)(a3)
+; RV32IPN-NEXT:    or a1, a1, a2
+; RV32IPN-NEXT:    or a0, a0, a3
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <4 x i16>
   %or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
@@ -1001,42 +409,16 @@
 define i32 @xorv4i8(i32 %a) nounwind {
 ; RV32IP-LABEL: xorv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    xori a0, a0, 4
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 10(sp)
-; RV32IP-NEXT:    xori a0, a0, 3
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 9(sp)
-; RV32IP-NEXT:    xori a0, a0, 2
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 8(sp)
-; RV32IP-NEXT:    xori a0, a0, 1
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI20_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI20_0)(a1)
+; RV32IP-NEXT:    xor a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xorv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    xori a0, a0, 4
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 10(sp)
-; RV32IPN-NEXT:    xori a0, a0, 3
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 9(sp)
-; RV32IPN-NEXT:    xori a0, a0, 2
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 8(sp)
-; RV32IPN-NEXT:    xori a0, a0, 1
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI20_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI20_0)(a1)
+; RV32IPN-NEXT:    xor a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <4 x i8>
   %xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
@@ -1047,30 +429,16 @@
 define i32 @xorv2i16(i32 %a) nounwind {
 ; RV32IP-LABEL: xorv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lh a0, 10(sp)
-; RV32IP-NEXT:    xori a0, a0, 2
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    xori a0, a0, 1
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI21_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI21_0)(a1)
+; RV32IP-NEXT:    xor a0, a0, a1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xorv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lh a0, 10(sp)
-; RV32IPN-NEXT:    xori a0, a0, 2
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    xori a0, a0, 1
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI21_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI21_0)(a1)
+; RV32IPN-NEXT:    xor a0, a0, a1
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <2 x i16>
   %xor = xor <2 x i16> %tmp, <i16 1, i16 2>
@@ -1081,70 +449,22 @@
 define i64 @xorv8i8(i64 %a) nounwind {
 ; RV32IP-LABEL: xorv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 0(sp)
-; RV32IP-NEXT:    sw a1, 4(sp)
-; RV32IP-NEXT:    lb a0, 3(sp)
-; RV32IP-NEXT:    xori a0, a0, 4
-; RV32IP-NEXT:    sb a0, 11(sp)
-; RV32IP-NEXT:    lb a0, 2(sp)
-; RV32IP-NEXT:    xori a0, a0, 3
-; RV32IP-NEXT:    sb a0, 10(sp)
-; RV32IP-NEXT:    lb a0, 1(sp)
-; RV32IP-NEXT:    xori a0, a0, 2
-; RV32IP-NEXT:    sb a0, 9(sp)
-; RV32IP-NEXT:    lb a0, 0(sp)
-; RV32IP-NEXT:    xori a0, a0, 1
-; RV32IP-NEXT:    sb a0, 8(sp)
-; RV32IP-NEXT:    lb a0, 7(sp)
-; RV32IP-NEXT:    xori a0, a0, 8
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 6(sp)
-; RV32IP-NEXT:    xori a0, a0, 7
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 5(sp)
-; RV32IP-NEXT:    xori a0, a0, 6
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 4(sp)
-; RV32IP-NEXT:    xori a0, a0, 5
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 8(sp)
-; RV32IP-NEXT:    lw a1, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a2, %hi(.LCPI22_0)
+; RV32IP-NEXT:    lw a2, %lo(.LCPI22_0)(a2)
+; RV32IP-NEXT:    lui a3, %hi(.LCPI22_1)
+; RV32IP-NEXT:    lw a3, %lo(.LCPI22_1)(a3)
+; RV32IP-NEXT:    xor a1, a1, a2
+; RV32IP-NEXT:    xor a0, a0, a3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xorv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 0(sp)
-; RV32IPN-NEXT:    sw a1, 4(sp)
-; RV32IPN-NEXT:    lb a0, 3(sp)
-; RV32IPN-NEXT:    xori a0, a0, 4
-; RV32IPN-NEXT:    sb a0, 11(sp)
-; RV32IPN-NEXT:    lb a0, 2(sp)
-; RV32IPN-NEXT:    xori a0, a0, 3
-; RV32IPN-NEXT:    sb a0, 10(sp)
-; RV32IPN-NEXT:    lb a0, 1(sp)
-; RV32IPN-NEXT:    xori a0, a0, 2
-; RV32IPN-NEXT:    sb a0, 9(sp)
-; RV32IPN-NEXT:    lb a0, 0(sp)
-; RV32IPN-NEXT:    xori a0, a0, 1
-; RV32IPN-NEXT:    sb a0, 8(sp)
-; RV32IPN-NEXT:    lb a0, 7(sp)
-; RV32IPN-NEXT:    xori a0, a0, 8
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 6(sp)
-; RV32IPN-NEXT:    xori a0, a0, 7
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 5(sp)
-; RV32IPN-NEXT:    xori a0, a0, 6
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 4(sp)
-; RV32IPN-NEXT:    xori a0, a0, 5
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 8(sp)
-; RV32IPN-NEXT:    lw a1, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a2, %hi(.LCPI22_0)
+; RV32IPN-NEXT:    lw a2, %lo(.LCPI22_0)(a2)
+; RV32IPN-NEXT:    lui a3, %hi(.LCPI22_1)
+; RV32IPN-NEXT:    lw a3, %lo(.LCPI22_1)(a3)
+; RV32IPN-NEXT:    xor a1, a1, a2
+; RV32IPN-NEXT:    xor a0, a0, a3
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <8 x i8>
   %xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
@@ -1155,46 +475,22 @@
 define i64 @xorv4i16(i64 %a) nounwind {
 ; RV32IP-LABEL: xorv4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a0, 0(sp)
-; RV32IP-NEXT:    sw a1, 4(sp)
-; RV32IP-NEXT:    lh a0, 2(sp)
-; RV32IP-NEXT:    xori a0, a0, 2
-; RV32IP-NEXT:    sh a0, 10(sp)
-; RV32IP-NEXT:    lh a0, 0(sp)
-; RV32IP-NEXT:    xori a0, a0, 1
-; RV32IP-NEXT:    sh a0, 8(sp)
-; RV32IP-NEXT:    lh a0, 6(sp)
-; RV32IP-NEXT:    xori a0, a0, 4
-; RV32IP-NEXT:    sh a0, 14(sp)
-; RV32IP-NEXT:    lh a0, 4(sp)
-; RV32IP-NEXT:    xori a0, a0, 3
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 8(sp)
-; RV32IP-NEXT:    lw a1, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a2, %hi(.LCPI23_0)
+; RV32IP-NEXT:    lw a2, %lo(.LCPI23_0)(a2)
+; RV32IP-NEXT:    lui a3, %hi(.LCPI23_1)
+; RV32IP-NEXT:    lw a3, %lo(.LCPI23_1)(a3)
+; RV32IP-NEXT:    xor a1, a1, a2
+; RV32IP-NEXT:    xor a0, a0, a3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xorv4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a0, 0(sp)
-; RV32IPN-NEXT:    sw a1, 4(sp)
-; RV32IPN-NEXT:    lh a0, 2(sp)
-; RV32IPN-NEXT:    xori a0, a0, 2
-; RV32IPN-NEXT:    sh a0, 10(sp)
-; RV32IPN-NEXT:    lh a0, 0(sp)
-; RV32IPN-NEXT:    xori a0, a0, 1
-; RV32IPN-NEXT:    sh a0, 8(sp)
-; RV32IPN-NEXT:    lh a0, 6(sp)
-; RV32IPN-NEXT:    xori a0, a0, 4
-; RV32IPN-NEXT:    sh a0, 14(sp)
-; RV32IPN-NEXT:    lh a0, 4(sp)
-; RV32IPN-NEXT:    xori a0, a0, 3
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 8(sp)
-; RV32IPN-NEXT:    lw a1, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a2, %hi(.LCPI23_0)
+; RV32IPN-NEXT:    lw a2, %lo(.LCPI23_0)(a2)
+; RV32IPN-NEXT:    lui a3, %hi(.LCPI23_1)
+; RV32IPN-NEXT:    lw a3, %lo(.LCPI23_1)(a3)
+; RV32IPN-NEXT:    xor a1, a1, a2
+; RV32IPN-NEXT:    xor a0, a0, a3
 ; RV32IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <4 x i16>
   %xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
@@ -1228,72 +524,14 @@
 define i32 @andiv4i8(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: andiv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lb a6, 8(sp)
-; RV32IP-NEXT:    lb a7, 4(sp)
-; RV32IP-NEXT:    lb t0, 9(sp)
-; RV32IP-NEXT:    lb a3, 5(sp)
-; RV32IP-NEXT:    lb a4, 10(sp)
-; RV32IP-NEXT:    lb a5, 6(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    lb a1, 7(sp)
-; RV32IP-NEXT:    addi a2, zero, 1
-; RV32IP-NEXT:    sw a2, 0(sp)
-; RV32IP-NEXT:    lb a2, 3(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 2(sp)
-; RV32IP-NEXT:    add a1, a5, a4
-; RV32IP-NEXT:    and a0, a1, a0
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 1(sp)
-; RV32IP-NEXT:    add a1, a3, t0
-; RV32IP-NEXT:    and a0, a1, a0
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 0(sp)
-; RV32IP-NEXT:    add a1, a7, a6
-; RV32IP-NEXT:    and a0, a1, a0
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add8 a0, a0, a1
+; RV32IP-NEXT:    andi a0, a0, 1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andiv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lb a6, 8(sp)
-; RV32IPN-NEXT:    lb a7, 4(sp)
-; RV32IPN-NEXT:    lb t0, 9(sp)
-; RV32IPN-NEXT:    lb a3, 5(sp)
-; RV32IPN-NEXT:    lb a4, 10(sp)
-; RV32IPN-NEXT:    lb a5, 6(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    lb a1, 7(sp)
-; RV32IPN-NEXT:    addi a2, zero, 1
-; RV32IPN-NEXT:    sw a2, 0(sp)
-; RV32IPN-NEXT:    lb a2, 3(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 2(sp)
-; RV32IPN-NEXT:    add a1, a5, a4
-; RV32IPN-NEXT:    and a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 1(sp)
-; RV32IPN-NEXT:    add a1, a3, t0
-; RV32IPN-NEXT:    and a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 0(sp)
-; RV32IPN-NEXT:    add a1, a7, a6
-; RV32IPN-NEXT:    and a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add8 a0, a0, a1
+; RV32IPN-NEXT:    andi a0, a0, 1
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -1307,48 +545,14 @@
 define i32 @andiv2i16(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: andiv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    lh a1, 4(sp)
-; RV32IP-NEXT:    lh a2, 10(sp)
-; RV32IP-NEXT:    lh a3, 6(sp)
-; RV32IP-NEXT:    addi a4, zero, -2
-; RV32IP-NEXT:    sw a4, 0(sp)
-; RV32IP-NEXT:    lh a4, 2(sp)
-; RV32IP-NEXT:    add a2, a3, a2
-; RV32IP-NEXT:    and a2, a2, a4
-; RV32IP-NEXT:    sh a2, 14(sp)
-; RV32IP-NEXT:    lh a2, 0(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add16 a0, a0, a1
+; RV32IP-NEXT:    andi a0, a0, -2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andiv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    lh a1, 4(sp)
-; RV32IPN-NEXT:    lh a2, 10(sp)
-; RV32IPN-NEXT:    lh a3, 6(sp)
-; RV32IPN-NEXT:    addi a4, zero, -2
-; RV32IPN-NEXT:    sw a4, 0(sp)
-; RV32IPN-NEXT:    lh a4, 2(sp)
-; RV32IPN-NEXT:    add a2, a3, a2
-; RV32IPN-NEXT:    and a2, a2, a4
-; RV32IPN-NEXT:    sh a2, 14(sp)
-; RV32IPN-NEXT:    lh a2, 0(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add16 a0, a0, a1
+; RV32IPN-NEXT:    andi a0, a0, -2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -1362,110 +566,16 @@
 define i64 @andiv8i8(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: andiv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lb a0, 23(sp)
-; RV32IP-NEXT:    lb a1, 15(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 27(sp)
-; RV32IP-NEXT:    lb a0, 22(sp)
-; RV32IP-NEXT:    lb a1, 14(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 26(sp)
-; RV32IP-NEXT:    lb a0, 21(sp)
-; RV32IP-NEXT:    lb a1, 13(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 25(sp)
-; RV32IP-NEXT:    lb a0, 20(sp)
-; RV32IP-NEXT:    lb a1, 12(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sb a0, 24(sp)
-; RV32IP-NEXT:    lb a6, 16(sp)
-; RV32IP-NEXT:    lb a7, 8(sp)
-; RV32IP-NEXT:    lb t0, 17(sp)
-; RV32IP-NEXT:    lb t1, 9(sp)
-; RV32IP-NEXT:    lb a5, 18(sp)
-; RV32IP-NEXT:    lb a0, 10(sp)
-; RV32IP-NEXT:    lb a2, 19(sp)
-; RV32IP-NEXT:    lb a3, 11(sp)
-; RV32IP-NEXT:    lw a1, 24(sp)
-; RV32IP-NEXT:    addi a4, zero, -3
-; RV32IP-NEXT:    sw a4, 4(sp)
-; RV32IP-NEXT:    lb a4, 7(sp)
-; RV32IP-NEXT:    add a2, a3, a2
-; RV32IP-NEXT:    and a2, a2, a4
-; RV32IP-NEXT:    sb a2, 31(sp)
-; RV32IP-NEXT:    lb a2, 6(sp)
-; RV32IP-NEXT:    add a0, a0, a5
-; RV32IP-NEXT:    and a0, a0, a2
-; RV32IP-NEXT:    sb a0, 30(sp)
-; RV32IP-NEXT:    lb a0, 5(sp)
-; RV32IP-NEXT:    add a2, t1, t0
-; RV32IP-NEXT:    and a0, a2, a0
-; RV32IP-NEXT:    sb a0, 29(sp)
-; RV32IP-NEXT:    lb a0, 4(sp)
-; RV32IP-NEXT:    add a2, a7, a6
-; RV32IP-NEXT:    and a0, a2, a0
-; RV32IP-NEXT:    sb a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    add8 a1, a1, a3
+; RV32IP-NEXT:    add8 a0, a0, a2
+; RV32IP-NEXT:    andi a0, a0, -3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andiv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lb a0, 23(sp)
-; RV32IPN-NEXT:    lb a1, 15(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 27(sp)
-; RV32IPN-NEXT:    lb a0, 22(sp)
-; RV32IPN-NEXT:    lb a1, 14(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 26(sp)
-; RV32IPN-NEXT:    lb a0, 21(sp)
-; RV32IPN-NEXT:    lb a1, 13(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 25(sp)
-; RV32IPN-NEXT:    lb a0, 20(sp)
-; RV32IPN-NEXT:    lb a1, 12(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 24(sp)
-; RV32IPN-NEXT:    lb a6, 16(sp)
-; RV32IPN-NEXT:    lb a7, 8(sp)
-; RV32IPN-NEXT:    lb t0, 17(sp)
-; RV32IPN-NEXT:    lb t1, 9(sp)
-; RV32IPN-NEXT:    lb a5, 18(sp)
-; RV32IPN-NEXT:    lb a0, 10(sp)
-; RV32IPN-NEXT:    lb a2, 19(sp)
-; RV32IPN-NEXT:    lb a3, 11(sp)
-; RV32IPN-NEXT:    lw a1, 24(sp)
-; RV32IPN-NEXT:    addi a4, zero, -3
-; RV32IPN-NEXT:    sw a4, 4(sp)
-; RV32IPN-NEXT:    lb a4, 7(sp)
-; RV32IPN-NEXT:    add a2, a3, a2
-; RV32IPN-NEXT:    and a2, a2, a4
-; RV32IPN-NEXT:    sb a2, 31(sp)
-; RV32IPN-NEXT:    lb a2, 6(sp)
-; RV32IPN-NEXT:    add a0, a0, a5
-; RV32IPN-NEXT:    and a0, a0, a2
-; RV32IPN-NEXT:    sb a0, 30(sp)
-; RV32IPN-NEXT:    lb a0, 5(sp)
-; RV32IPN-NEXT:    add a2, t1, t0
-; RV32IPN-NEXT:    and a0, a2, a0
-; RV32IPN-NEXT:    sb a0, 29(sp)
-; RV32IPN-NEXT:    lb a0, 4(sp)
-; RV32IPN-NEXT:    add a2, a7, a6
-; RV32IPN-NEXT:    and a0, a2, a0
-; RV32IPN-NEXT:    sb a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    add8 a1, a1, a3
+; RV32IPN-NEXT:    add8 a0, a0, a2
+; RV32IPN-NEXT:    andi a0, a0, -3
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -1479,70 +589,16 @@
 define i64 @andvi4i16(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: andvi4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lh a0, 22(sp)
-; RV32IP-NEXT:    lh a1, 14(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 26(sp)
-; RV32IP-NEXT:    lh a0, 20(sp)
-; RV32IP-NEXT:    lh a1, 12(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    sh a0, 24(sp)
-; RV32IP-NEXT:    lh a0, 16(sp)
-; RV32IP-NEXT:    lh a2, 8(sp)
-; RV32IP-NEXT:    lh a3, 18(sp)
-; RV32IP-NEXT:    lh a4, 10(sp)
-; RV32IP-NEXT:    lw a1, 24(sp)
-; RV32IP-NEXT:    addi a5, zero, -4
-; RV32IP-NEXT:    sw a5, 4(sp)
-; RV32IP-NEXT:    lh a5, 6(sp)
-; RV32IP-NEXT:    add a3, a4, a3
-; RV32IP-NEXT:    and a3, a3, a5
-; RV32IP-NEXT:    sh a3, 30(sp)
-; RV32IP-NEXT:    lh a3, 4(sp)
-; RV32IP-NEXT:    add a0, a2, a0
-; RV32IP-NEXT:    and a0, a0, a3
-; RV32IP-NEXT:    sh a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    add16 a1, a1, a3
+; RV32IP-NEXT:    add16 a0, a0, a2
+; RV32IP-NEXT:    andi a0, a0, -4
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: andvi4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lh a0, 22(sp)
-; RV32IPN-NEXT:    lh a1, 14(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 26(sp)
-; RV32IPN-NEXT:    lh a0, 20(sp)
-; RV32IPN-NEXT:    lh a1, 12(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 24(sp)
-; RV32IPN-NEXT:    lh a0, 16(sp)
-; RV32IPN-NEXT:    lh a2, 8(sp)
-; RV32IPN-NEXT:    lh a3, 18(sp)
-; RV32IPN-NEXT:    lh a4, 10(sp)
-; RV32IPN-NEXT:    lw a1, 24(sp)
-; RV32IPN-NEXT:    addi a5, zero, -4
-; RV32IPN-NEXT:    sw a5, 4(sp)
-; RV32IPN-NEXT:    lh a5, 6(sp)
-; RV32IPN-NEXT:    add a3, a4, a3
-; RV32IPN-NEXT:    and a3, a3, a5
-; RV32IPN-NEXT:    sh a3, 30(sp)
-; RV32IPN-NEXT:    lh a3, 4(sp)
-; RV32IPN-NEXT:    add a0, a2, a0
-; RV32IPN-NEXT:    and a0, a0, a3
-; RV32IPN-NEXT:    sh a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    add16 a1, a1, a3
+; RV32IPN-NEXT:    add16 a0, a0, a2
+; RV32IPN-NEXT:    andi a0, a0, -4
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -1579,72 +635,14 @@
 define i32 @oriv4i8(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: oriv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lb a6, 8(sp)
-; RV32IP-NEXT:    lb a7, 4(sp)
-; RV32IP-NEXT:    lb t0, 9(sp)
-; RV32IP-NEXT:    lb a3, 5(sp)
-; RV32IP-NEXT:    lb a4, 10(sp)
-; RV32IP-NEXT:    lb a5, 6(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    lb a1, 7(sp)
-; RV32IP-NEXT:    addi a2, zero, 1
-; RV32IP-NEXT:    sw a2, 0(sp)
-; RV32IP-NEXT:    lb a2, 3(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    or a0, a0, a2
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 2(sp)
-; RV32IP-NEXT:    add a1, a5, a4
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 1(sp)
-; RV32IP-NEXT:    add a1, a3, t0
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 0(sp)
-; RV32IP-NEXT:    add a1, a7, a6
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add8 a0, a0, a1
+; RV32IP-NEXT:    ori a0, a0, 1
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: oriv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lb a6, 8(sp)
-; RV32IPN-NEXT:    lb a7, 4(sp)
-; RV32IPN-NEXT:    lb t0, 9(sp)
-; RV32IPN-NEXT:    lb a3, 5(sp)
-; RV32IPN-NEXT:    lb a4, 10(sp)
-; RV32IPN-NEXT:    lb a5, 6(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    lb a1, 7(sp)
-; RV32IPN-NEXT:    addi a2, zero, 1
-; RV32IPN-NEXT:    sw a2, 0(sp)
-; RV32IPN-NEXT:    lb a2, 3(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    or a0, a0, a2
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 2(sp)
-; RV32IPN-NEXT:    add a1, a5, a4
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 1(sp)
-; RV32IPN-NEXT:    add a1, a3, t0
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 0(sp)
-; RV32IPN-NEXT:    add a1, a7, a6
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add8 a0, a0, a1
+; RV32IPN-NEXT:    ori a0, a0, 1
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -1658,48 +656,14 @@
 define i32 @oriv2i16(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: oriv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    lh a1, 4(sp)
-; RV32IP-NEXT:    lh a2, 10(sp)
-; RV32IP-NEXT:    lh a3, 6(sp)
-; RV32IP-NEXT:    addi a4, zero, -2
-; RV32IP-NEXT:    sw a4, 0(sp)
-; RV32IP-NEXT:    lh a4, 2(sp)
-; RV32IP-NEXT:    add a2, a3, a2
-; RV32IP-NEXT:    or a2, a2, a4
-; RV32IP-NEXT:    sh a2, 14(sp)
-; RV32IP-NEXT:    lh a2, 0(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    or a0, a0, a2
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add16 a0, a0, a1
+; RV32IP-NEXT:    ori a0, a0, -2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: oriv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    lh a1, 4(sp)
-; RV32IPN-NEXT:    lh a2, 10(sp)
-; RV32IPN-NEXT:    lh a3, 6(sp)
-; RV32IPN-NEXT:    addi a4, zero, -2
-; RV32IPN-NEXT:    sw a4, 0(sp)
-; RV32IPN-NEXT:    lh a4, 2(sp)
-; RV32IPN-NEXT:    add a2, a3, a2
-; RV32IPN-NEXT:    or a2, a2, a4
-; RV32IPN-NEXT:    sh a2, 14(sp)
-; RV32IPN-NEXT:    lh a2, 0(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    or a0, a0, a2
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add16 a0, a0, a1
+; RV32IPN-NEXT:    ori a0, a0, -2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -1713,76 +677,18 @@
 define i64 @oriv8i8(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: oriv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a2, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lb a6, 8(sp)
-; RV32IP-NEXT:    lb a7, 4(sp)
-; RV32IP-NEXT:    lb t0, 9(sp)
-; RV32IP-NEXT:    lb a3, 5(sp)
-; RV32IP-NEXT:    lb a4, 10(sp)
-; RV32IP-NEXT:    lb a5, 6(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    lb a1, 7(sp)
-; RV32IP-NEXT:    addi a2, zero, -3
-; RV32IP-NEXT:    sw a2, 0(sp)
-; RV32IP-NEXT:    lb a2, 3(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    or a0, a0, a2
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 2(sp)
-; RV32IP-NEXT:    add a1, a5, a4
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 1(sp)
-; RV32IP-NEXT:    add a1, a3, t0
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 0(sp)
-; RV32IP-NEXT:    add a1, a7, a6
-; RV32IP-NEXT:    or a0, a1, a0
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lui a0, %hi(.LCPI32_0)
-; RV32IP-NEXT:    lw a1, %lo(.LCPI32_0)(a0)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI32_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI32_0)(a1)
+; RV32IP-NEXT:    add8 a0, a0, a2
+; RV32IP-NEXT:    ori a0, a0, -3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: oriv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a2, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lb a6, 8(sp)
-; RV32IPN-NEXT:    lb a7, 4(sp)
-; RV32IPN-NEXT:    lb t0, 9(sp)
-; RV32IPN-NEXT:    lb a3, 5(sp)
-; RV32IPN-NEXT:    lb a4, 10(sp)
-; RV32IPN-NEXT:    lb a5, 6(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    lb a1, 7(sp)
-; RV32IPN-NEXT:    addi a2, zero, -3
-; RV32IPN-NEXT:    sw a2, 0(sp)
-; RV32IPN-NEXT:    lb a2, 3(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    or a0, a0, a2
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 2(sp)
-; RV32IPN-NEXT:    add a1, a5, a4
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 1(sp)
-; RV32IPN-NEXT:    add a1, a3, t0
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 0(sp)
-; RV32IPN-NEXT:    add a1, a7, a6
-; RV32IPN-NEXT:    or a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lui a0, %hi(.LCPI32_0)
-; RV32IPN-NEXT:    lw a1, %lo(.LCPI32_0)(a0)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI32_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI32_0)(a1)
+; RV32IPN-NEXT:    add8 a0, a0, a2
+; RV32IPN-NEXT:    ori a0, a0, -3
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -1796,52 +702,18 @@
 define i64 @orvi4i16(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: orvi4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a2, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    lh a1, 4(sp)
-; RV32IP-NEXT:    lh a2, 10(sp)
-; RV32IP-NEXT:    lh a3, 6(sp)
-; RV32IP-NEXT:    addi a4, zero, -4
-; RV32IP-NEXT:    sw a4, 0(sp)
-; RV32IP-NEXT:    lh a4, 2(sp)
-; RV32IP-NEXT:    add a2, a3, a2
-; RV32IP-NEXT:    or a2, a2, a4
-; RV32IP-NEXT:    sh a2, 14(sp)
-; RV32IP-NEXT:    lh a2, 0(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    or a0, a0, a2
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lui a0, %hi(.LCPI33_0)
-; RV32IP-NEXT:    lw a1, %lo(.LCPI33_0)(a0)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    lui a1, %hi(.LCPI33_0)
+; RV32IP-NEXT:    lw a1, %lo(.LCPI33_0)(a1)
+; RV32IP-NEXT:    add16 a0, a0, a2
+; RV32IP-NEXT:    ori a0, a0, -4
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: orvi4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a2, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    lh a1, 4(sp)
-; RV32IPN-NEXT:    lh a2, 10(sp)
-; RV32IPN-NEXT:    lh a3, 6(sp)
-; RV32IPN-NEXT:    addi a4, zero, -4
-; RV32IPN-NEXT:    sw a4, 0(sp)
-; RV32IPN-NEXT:    lh a4, 2(sp)
-; RV32IPN-NEXT:    add a2, a3, a2
-; RV32IPN-NEXT:    or a2, a2, a4
-; RV32IPN-NEXT:    sh a2, 14(sp)
-; RV32IPN-NEXT:    lh a2, 0(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    or a0, a0, a2
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lui a0, %hi(.LCPI33_0)
-; RV32IPN-NEXT:    lw a1, %lo(.LCPI33_0)(a0)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    lui a1, %hi(.LCPI33_0)
+; RV32IPN-NEXT:    lw a1, %lo(.LCPI33_0)(a1)
+; RV32IPN-NEXT:    add16 a0, a0, a2
+; RV32IPN-NEXT:    ori a0, a0, -4
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -1878,72 +750,14 @@
 define i32 @xoriv4i8(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: xoriv4i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lb a6, 8(sp)
-; RV32IP-NEXT:    lb a7, 4(sp)
-; RV32IP-NEXT:    lb t0, 9(sp)
-; RV32IP-NEXT:    lb a3, 5(sp)
-; RV32IP-NEXT:    lb a4, 10(sp)
-; RV32IP-NEXT:    lb a5, 6(sp)
-; RV32IP-NEXT:    lb a0, 11(sp)
-; RV32IP-NEXT:    lb a1, 7(sp)
-; RV32IP-NEXT:    addi a2, zero, -1
-; RV32IP-NEXT:    sw a2, 0(sp)
-; RV32IP-NEXT:    lb a2, 3(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    xor a0, a0, a2
-; RV32IP-NEXT:    sb a0, 15(sp)
-; RV32IP-NEXT:    lb a0, 2(sp)
-; RV32IP-NEXT:    add a1, a5, a4
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 14(sp)
-; RV32IP-NEXT:    lb a0, 1(sp)
-; RV32IP-NEXT:    add a1, a3, t0
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 13(sp)
-; RV32IP-NEXT:    lb a0, 0(sp)
-; RV32IP-NEXT:    add a1, a7, a6
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add8 a0, a0, a1
+; RV32IP-NEXT:    not a0, a0
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xoriv4i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lb a6, 8(sp)
-; RV32IPN-NEXT:    lb a7, 4(sp)
-; RV32IPN-NEXT:    lb t0, 9(sp)
-; RV32IPN-NEXT:    lb a3, 5(sp)
-; RV32IPN-NEXT:    lb a4, 10(sp)
-; RV32IPN-NEXT:    lb a5, 6(sp)
-; RV32IPN-NEXT:    lb a0, 11(sp)
-; RV32IPN-NEXT:    lb a1, 7(sp)
-; RV32IPN-NEXT:    addi a2, zero, -1
-; RV32IPN-NEXT:    sw a2, 0(sp)
-; RV32IPN-NEXT:    lb a2, 3(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    xor a0, a0, a2
-; RV32IPN-NEXT:    sb a0, 15(sp)
-; RV32IPN-NEXT:    lb a0, 2(sp)
-; RV32IPN-NEXT:    add a1, a5, a4
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 14(sp)
-; RV32IPN-NEXT:    lb a0, 1(sp)
-; RV32IPN-NEXT:    add a1, a3, t0
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 13(sp)
-; RV32IPN-NEXT:    lb a0, 0(sp)
-; RV32IPN-NEXT:    add a1, a7, a6
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add8 a0, a0, a1
+; RV32IPN-NEXT:    not a0, a0
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -1957,48 +771,14 @@
 define i32 @xoriv2i16(i32 %a, i32 %b) nounwind {
 ; RV32IP-LABEL: xoriv2i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -16
-; RV32IP-NEXT:    sw a1, 8(sp)
-; RV32IP-NEXT:    sw a0, 4(sp)
-; RV32IP-NEXT:    lh a0, 8(sp)
-; RV32IP-NEXT:    lh a1, 4(sp)
-; RV32IP-NEXT:    lh a2, 10(sp)
-; RV32IP-NEXT:    lh a3, 6(sp)
-; RV32IP-NEXT:    addi a4, zero, -2
-; RV32IP-NEXT:    sw a4, 0(sp)
-; RV32IP-NEXT:    lh a4, 2(sp)
-; RV32IP-NEXT:    add a2, a3, a2
-; RV32IP-NEXT:    xor a2, a2, a4
-; RV32IP-NEXT:    sh a2, 14(sp)
-; RV32IP-NEXT:    lh a2, 0(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    xor a0, a0, a2
-; RV32IP-NEXT:    sh a0, 12(sp)
-; RV32IP-NEXT:    lw a0, 12(sp)
-; RV32IP-NEXT:    addi sp, sp, 16
+; RV32IP-NEXT:    add16 a0, a0, a1
+; RV32IP-NEXT:    xori a0, a0, -2
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xoriv2i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -16
-; RV32IPN-NEXT:    sw a1, 8(sp)
-; RV32IPN-NEXT:    sw a0, 4(sp)
-; RV32IPN-NEXT:    lh a0, 8(sp)
-; RV32IPN-NEXT:    lh a1, 4(sp)
-; RV32IPN-NEXT:    lh a2, 10(sp)
-; RV32IPN-NEXT:    lh a3, 6(sp)
-; RV32IPN-NEXT:    addi a4, zero, -2
-; RV32IPN-NEXT:    sw a4, 0(sp)
-; RV32IPN-NEXT:    lh a4, 2(sp)
-; RV32IPN-NEXT:    add a2, a3, a2
-; RV32IPN-NEXT:    xor a2, a2, a4
-; RV32IPN-NEXT:    sh a2, 14(sp)
-; RV32IPN-NEXT:    lh a2, 0(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    xor a0, a0, a2
-; RV32IPN-NEXT:    sh a0, 12(sp)
-; RV32IPN-NEXT:    lw a0, 12(sp)
-; RV32IPN-NEXT:    addi sp, sp, 16
+; RV32IPN-NEXT:    add16 a0, a0, a1
+; RV32IPN-NEXT:    xori a0, a0, -2
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -2012,138 +792,18 @@
 define i64 @xoriv8i8(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: xoriv8i8:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -48
-; RV32IP-NEXT:    sw s0, 44(sp) # 4-byte Folded Spill
-; RV32IP-NEXT:    sw s1, 40(sp) # 4-byte Folded Spill
-; RV32IP-NEXT:    sw a3, 28(sp)
-; RV32IP-NEXT:    sw a1, 20(sp)
-; RV32IP-NEXT:    sw a2, 24(sp)
-; RV32IP-NEXT:    sw a0, 16(sp)
-; RV32IP-NEXT:    lb a6, 28(sp)
-; RV32IP-NEXT:    lb a7, 20(sp)
-; RV32IP-NEXT:    lb t0, 29(sp)
-; RV32IP-NEXT:    lb t1, 21(sp)
-; RV32IP-NEXT:    lb t2, 30(sp)
-; RV32IP-NEXT:    lb t3, 22(sp)
-; RV32IP-NEXT:    lb t4, 31(sp)
-; RV32IP-NEXT:    lb t5, 23(sp)
-; RV32IP-NEXT:    lb t6, 24(sp)
-; RV32IP-NEXT:    lb a3, 16(sp)
-; RV32IP-NEXT:    lb a4, 25(sp)
-; RV32IP-NEXT:    lb a5, 17(sp)
-; RV32IP-NEXT:    lb a0, 26(sp)
-; RV32IP-NEXT:    lb a1, 18(sp)
-; RV32IP-NEXT:    lb a2, 27(sp)
-; RV32IP-NEXT:    lb s0, 19(sp)
-; RV32IP-NEXT:    addi s1, zero, -3
-; RV32IP-NEXT:    sw s1, 8(sp)
-; RV32IP-NEXT:    addi s1, zero, -1
-; RV32IP-NEXT:    sw s1, 12(sp)
-; RV32IP-NEXT:    lb s1, 11(sp)
-; RV32IP-NEXT:    add a2, s0, a2
-; RV32IP-NEXT:    xor a2, a2, s1
-; RV32IP-NEXT:    sb a2, 35(sp)
-; RV32IP-NEXT:    lb a2, 10(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    xor a0, a0, a2
-; RV32IP-NEXT:    sb a0, 34(sp)
-; RV32IP-NEXT:    lb a0, 9(sp)
-; RV32IP-NEXT:    add a1, a5, a4
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 33(sp)
-; RV32IP-NEXT:    lb a0, 8(sp)
-; RV32IP-NEXT:    add a1, a3, t6
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 32(sp)
-; RV32IP-NEXT:    lb a0, 15(sp)
-; RV32IP-NEXT:    add a1, t5, t4
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 39(sp)
-; RV32IP-NEXT:    lb a0, 14(sp)
-; RV32IP-NEXT:    add a1, t3, t2
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 38(sp)
-; RV32IP-NEXT:    lb a0, 13(sp)
-; RV32IP-NEXT:    add a1, t1, t0
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 37(sp)
-; RV32IP-NEXT:    lb a0, 12(sp)
-; RV32IP-NEXT:    add a1, a7, a6
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sb a0, 36(sp)
-; RV32IP-NEXT:    lw a0, 32(sp)
-; RV32IP-NEXT:    lw a1, 36(sp)
-; RV32IP-NEXT:    lw s1, 40(sp) # 4-byte Folded Reload
-; RV32IP-NEXT:    lw s0, 44(sp) # 4-byte Folded Reload
-; RV32IP-NEXT:    addi sp, sp, 48
+; RV32IP-NEXT:    add8 a0, a0, a2
+; RV32IP-NEXT:    add8 a1, a1, a3
+; RV32IP-NEXT:    not a1, a1
+; RV32IP-NEXT:    xori a0, a0, -3
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xoriv8i8:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -48
-; RV32IPN-NEXT:    sw s0, 44(sp) # 4-byte Folded Spill
-; RV32IPN-NEXT:    sw s1, 40(sp) # 4-byte Folded Spill
-; RV32IPN-NEXT:    sw a3, 28(sp)
-; RV32IPN-NEXT:    sw a1, 20(sp)
-; RV32IPN-NEXT:    sw a2, 24(sp)
-; RV32IPN-NEXT:    sw a0, 16(sp)
-; RV32IPN-NEXT:    lb a6, 28(sp)
-; RV32IPN-NEXT:    lb a7, 20(sp)
-; RV32IPN-NEXT:    lb t0, 29(sp)
-; RV32IPN-NEXT:    lb t1, 21(sp)
-; RV32IPN-NEXT:    lb t2, 30(sp)
-; RV32IPN-NEXT:    lb t3, 22(sp)
-; RV32IPN-NEXT:    lb t4, 31(sp)
-; RV32IPN-NEXT:    lb t5, 23(sp)
-; RV32IPN-NEXT:    lb t6, 24(sp)
-; RV32IPN-NEXT:    lb a3, 16(sp)
-; RV32IPN-NEXT:    lb a4, 25(sp)
-; RV32IPN-NEXT:    lb a5, 17(sp)
-; RV32IPN-NEXT:    lb a0, 26(sp)
-; RV32IPN-NEXT:    lb a1, 18(sp)
-; RV32IPN-NEXT:    lb a2, 27(sp)
-; RV32IPN-NEXT:    lb s0, 19(sp)
-; RV32IPN-NEXT:    addi s1, zero, -3
-; RV32IPN-NEXT:    sw s1, 8(sp)
-; RV32IPN-NEXT:    addi s1, zero, -1
-; RV32IPN-NEXT:    sw s1, 12(sp)
-; RV32IPN-NEXT:    lb s1, 11(sp)
-; RV32IPN-NEXT:    add a2, s0, a2
-; RV32IPN-NEXT:    xor a2, a2, s1
-; RV32IPN-NEXT:    sb a2, 35(sp)
-; RV32IPN-NEXT:    lb a2, 10(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    xor a0, a0, a2
-; RV32IPN-NEXT:    sb a0, 34(sp)
-; RV32IPN-NEXT:    lb a0, 9(sp)
-; RV32IPN-NEXT:    add a1, a5, a4
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 33(sp)
-; RV32IPN-NEXT:    lb a0, 8(sp)
-; RV32IPN-NEXT:    add a1, a3, t6
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 32(sp)
-; RV32IPN-NEXT:    lb a0, 15(sp)
-; RV32IPN-NEXT:    add a1, t5, t4
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 39(sp)
-; RV32IPN-NEXT:    lb a0, 14(sp)
-; RV32IPN-NEXT:    add a1, t3, t2
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 38(sp)
-; RV32IPN-NEXT:    lb a0, 13(sp)
-; RV32IPN-NEXT:    add a1, t1, t0
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 37(sp)
-; RV32IPN-NEXT:    lb a0, 12(sp)
-; RV32IPN-NEXT:    add a1, a7, a6
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sb a0, 36(sp)
-; RV32IPN-NEXT:    lw a0, 32(sp)
-; RV32IPN-NEXT:    lw a1, 36(sp)
-; RV32IPN-NEXT:    lw s1, 40(sp) # 4-byte Folded Reload
-; RV32IPN-NEXT:    lw s0, 44(sp) # 4-byte Folded Reload
-; RV32IPN-NEXT:    addi sp, sp, 48
+; RV32IPN-NEXT:    add8 a0, a0, a2
+; RV32IPN-NEXT:    add8 a1, a1, a3
+; RV32IPN-NEXT:    not a1, a1
+; RV32IPN-NEXT:    xori a0, a0, -3
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -2157,82 +817,18 @@
 define i64 @xorvi4i16(i64 %a, i64 %b) nounwind {
 ; RV32IP-LABEL: xorvi4i16:
 ; RV32IP:       # %bb.0:
-; RV32IP-NEXT:    addi sp, sp, -32
-; RV32IP-NEXT:    sw a3, 20(sp)
-; RV32IP-NEXT:    sw a1, 12(sp)
-; RV32IP-NEXT:    sw a2, 16(sp)
-; RV32IP-NEXT:    sw a0, 8(sp)
-; RV32IP-NEXT:    lh a6, 20(sp)
-; RV32IP-NEXT:    lh a7, 12(sp)
-; RV32IP-NEXT:    lh t0, 22(sp)
-; RV32IP-NEXT:    lh a3, 14(sp)
-; RV32IP-NEXT:    lh a4, 16(sp)
-; RV32IP-NEXT:    lh a5, 8(sp)
-; RV32IP-NEXT:    lh a0, 18(sp)
-; RV32IP-NEXT:    lh a1, 10(sp)
-; RV32IP-NEXT:    addi a2, zero, -4
-; RV32IP-NEXT:    sw a2, 0(sp)
-; RV32IP-NEXT:    addi a2, zero, -1
-; RV32IP-NEXT:    sw a2, 4(sp)
-; RV32IP-NEXT:    lh a2, 2(sp)
-; RV32IP-NEXT:    add a0, a1, a0
-; RV32IP-NEXT:    xor a0, a0, a2
-; RV32IP-NEXT:    sh a0, 26(sp)
-; RV32IP-NEXT:    lh a0, 0(sp)
-; RV32IP-NEXT:    add a1, a5, a4
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sh a0, 24(sp)
-; RV32IP-NEXT:    lh a0, 6(sp)
-; RV32IP-NEXT:    add a1, a3, t0
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sh a0, 30(sp)
-; RV32IP-NEXT:    lh a0, 4(sp)
-; RV32IP-NEXT:    add a1, a7, a6
-; RV32IP-NEXT:    xor a0, a1, a0
-; RV32IP-NEXT:    sh a0, 28(sp)
-; RV32IP-NEXT:    lw a0, 24(sp)
-; RV32IP-NEXT:    lw a1, 28(sp)
-; RV32IP-NEXT:    addi sp, sp, 32
+; RV32IP-NEXT:    add16 a0, a0, a2
+; RV32IP-NEXT:    add16 a1, a1, a3
+; RV32IP-NEXT:    not a1, a1
+; RV32IP-NEXT:    xori a0, a0, -4
 ; RV32IP-NEXT:    ret
 ;
 ; RV32IPN-LABEL: xorvi4i16:
 ; RV32IPN:       # %bb.0:
-; RV32IPN-NEXT:    addi sp, sp, -32
-; RV32IPN-NEXT:    sw a3, 20(sp)
-; RV32IPN-NEXT:    sw a1, 12(sp)
-; RV32IPN-NEXT:    sw a2, 16(sp)
-; RV32IPN-NEXT:    sw a0, 8(sp)
-; RV32IPN-NEXT:    lh a6, 20(sp)
-; RV32IPN-NEXT:    lh a7, 12(sp)
-; RV32IPN-NEXT:    lh t0, 22(sp)
-; RV32IPN-NEXT:    lh a3, 14(sp)
-; RV32IPN-NEXT:    lh a4, 16(sp)
-; RV32IPN-NEXT:    lh a5, 8(sp)
-; RV32IPN-NEXT:    lh a0, 18(sp)
-; RV32IPN-NEXT:    lh a1, 10(sp)
-; RV32IPN-NEXT:    addi a2, zero, -4
-; RV32IPN-NEXT:    sw a2, 0(sp)
-; RV32IPN-NEXT:    addi a2, zero, -1
-; RV32IPN-NEXT:    sw a2, 4(sp)
-; RV32IPN-NEXT:    lh a2, 2(sp)
-; RV32IPN-NEXT:    add a0, a1, a0
-; RV32IPN-NEXT:    xor a0, a0, a2
-; RV32IPN-NEXT:    sh a0, 26(sp)
-; RV32IPN-NEXT:    lh a0, 0(sp)
-; RV32IPN-NEXT:    add a1, a5, a4
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 24(sp)
-; RV32IPN-NEXT:    lh a0, 6(sp)
-; RV32IPN-NEXT:    add a1, a3, t0
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 30(sp)
-; RV32IPN-NEXT:    lh a0, 4(sp)
-; RV32IPN-NEXT:    add a1, a7, a6
-; RV32IPN-NEXT:    xor a0, a1, a0
-; RV32IPN-NEXT:    sh a0, 28(sp)
-; RV32IPN-NEXT:    lw a0, 24(sp)
-; RV32IPN-NEXT:    lw a1, 28(sp)
-; RV32IPN-NEXT:    addi sp, sp, 32
+; RV32IPN-NEXT:    add16 a0, a0, a2
+; RV32IPN-NEXT:    add16 a1, a1, a3
+; RV32IPN-NEXT:    not a1, a1
+; RV32IPN-NEXT:    xori a0, a0, -4
 ; RV32IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
diff --git a/llvm/test/CodeGen/RISCV/rv64zpn-alu.ll b/llvm/test/CodeGen/RISCV/rv64zpn-alu.ll
--- a/llvm/test/CodeGen/RISCV/rv64zpn-alu.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zpn-alu.ll
@@ -7,52 +7,14 @@
 define signext i32 @addv4i8(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: addv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 8(sp)
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lb a6, 8(sp)
-; RV64IP-NEXT:    lb a7, 12(sp)
-; RV64IP-NEXT:    lb a2, 9(sp)
-; RV64IP-NEXT:    lb a3, 11(sp)
-; RV64IP-NEXT:    lb a4, 15(sp)
-; RV64IP-NEXT:    lb a5, 10(sp)
-; RV64IP-NEXT:    lb a0, 14(sp)
-; RV64IP-NEXT:    lb a1, 13(sp)
-; RV64IP-NEXT:    add a3, a4, a3
-; RV64IP-NEXT:    sb a3, 7(sp)
-; RV64IP-NEXT:    add a0, a0, a5
-; RV64IP-NEXT:    sb a0, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a2
-; RV64IP-NEXT:    sb a0, 5(sp)
-; RV64IP-NEXT:    add a0, a7, a6
-; RV64IP-NEXT:    sb a0, 4(sp)
-; RV64IP-NEXT:    lw a0, 4(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: addv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 8(sp)
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lb a6, 8(sp)
-; RV64IPN-NEXT:    lb a7, 12(sp)
-; RV64IPN-NEXT:    lb a2, 9(sp)
-; RV64IPN-NEXT:    lb a3, 11(sp)
-; RV64IPN-NEXT:    lb a4, 15(sp)
-; RV64IPN-NEXT:    lb a5, 10(sp)
-; RV64IPN-NEXT:    lb a0, 14(sp)
-; RV64IPN-NEXT:    lb a1, 13(sp)
-; RV64IPN-NEXT:    add a3, a4, a3
-; RV64IPN-NEXT:    sb a3, 7(sp)
-; RV64IPN-NEXT:    add a0, a0, a5
-; RV64IPN-NEXT:    sb a0, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a2
-; RV64IPN-NEXT:    sb a0, 5(sp)
-; RV64IPN-NEXT:    add a0, a7, a6
-; RV64IPN-NEXT:    sb a0, 4(sp)
-; RV64IPN-NEXT:    lw a0, 4(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -64,36 +26,14 @@
 define signext i32 @addv2i16(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: addv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 8(sp)
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lh a0, 10(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    lh a2, 8(sp)
-; RV64IP-NEXT:    lh a3, 12(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sh a0, 6(sp)
-; RV64IP-NEXT:    add a0, a3, a2
-; RV64IP-NEXT:    sh a0, 4(sp)
-; RV64IP-NEXT:    lw a0, 4(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: addv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 8(sp)
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lh a0, 10(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    lh a2, 8(sp)
-; RV64IPN-NEXT:    lh a3, 12(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 6(sp)
-; RV64IPN-NEXT:    add a0, a3, a2
-; RV64IPN-NEXT:    sh a0, 4(sp)
-; RV64IPN-NEXT:    lw a0, 4(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -105,84 +45,12 @@
 define i64 @addv8i8(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: addv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lb a0, 23(sp)
-; RV64IP-NEXT:    lb a1, 15(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 31(sp)
-; RV64IP-NEXT:    lb a0, 22(sp)
-; RV64IP-NEXT:    lb a1, 14(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 30(sp)
-; RV64IP-NEXT:    lb a0, 21(sp)
-; RV64IP-NEXT:    lb a1, 13(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 29(sp)
-; RV64IP-NEXT:    lb a0, 20(sp)
-; RV64IP-NEXT:    lb a1, 12(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 28(sp)
-; RV64IP-NEXT:    lb a0, 19(sp)
-; RV64IP-NEXT:    lb a1, 11(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 27(sp)
-; RV64IP-NEXT:    lb a0, 18(sp)
-; RV64IP-NEXT:    lb a1, 10(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 26(sp)
-; RV64IP-NEXT:    lb a0, 17(sp)
-; RV64IP-NEXT:    lb a1, 9(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 25(sp)
-; RV64IP-NEXT:    lb a0, 16(sp)
-; RV64IP-NEXT:    lb a1, 8(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sb a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add8 a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: addv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lb a0, 23(sp)
-; RV64IPN-NEXT:    lb a1, 15(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 31(sp)
-; RV64IPN-NEXT:    lb a0, 22(sp)
-; RV64IPN-NEXT:    lb a1, 14(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 30(sp)
-; RV64IPN-NEXT:    lb a0, 21(sp)
-; RV64IPN-NEXT:    lb a1, 13(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 29(sp)
-; RV64IPN-NEXT:    lb a0, 20(sp)
-; RV64IPN-NEXT:    lb a1, 12(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 28(sp)
-; RV64IPN-NEXT:    lb a0, 19(sp)
-; RV64IPN-NEXT:    lb a1, 11(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 27(sp)
-; RV64IPN-NEXT:    lb a0, 18(sp)
-; RV64IPN-NEXT:    lb a1, 10(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 26(sp)
-; RV64IPN-NEXT:    lb a0, 17(sp)
-; RV64IPN-NEXT:    lb a1, 9(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 25(sp)
-; RV64IPN-NEXT:    lb a0, 16(sp)
-; RV64IPN-NEXT:    lb a1, 8(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add8 a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -194,52 +62,12 @@
 define i64 @addv4i16(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: addv4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lh a0, 22(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sh a0, 30(sp)
-; RV64IP-NEXT:    lh a0, 20(sp)
-; RV64IP-NEXT:    lh a1, 12(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sh a0, 28(sp)
-; RV64IP-NEXT:    lh a0, 18(sp)
-; RV64IP-NEXT:    lh a1, 10(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sh a0, 26(sp)
-; RV64IP-NEXT:    lh a0, 16(sp)
-; RV64IP-NEXT:    lh a1, 8(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sh a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add16 a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: addv4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lh a0, 22(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 30(sp)
-; RV64IPN-NEXT:    lh a0, 20(sp)
-; RV64IPN-NEXT:    lh a1, 12(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 28(sp)
-; RV64IPN-NEXT:    lh a0, 18(sp)
-; RV64IPN-NEXT:    lh a1, 10(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 26(sp)
-; RV64IPN-NEXT:    lh a0, 16(sp)
-; RV64IPN-NEXT:    lh a1, 8(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add16 a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -251,36 +79,12 @@
 define i64 @addv2i32(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: addv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 20(sp)
-; RV64IP-NEXT:    lw a1, 12(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sw a0, 28(sp)
-; RV64IP-NEXT:    lw a0, 16(sp)
-; RV64IP-NEXT:    lw a1, 8(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    sw a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add32 a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: addv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 20(sp)
-; RV64IPN-NEXT:    lw a1, 12(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sw a0, 28(sp)
-; RV64IPN-NEXT:    lw a0, 16(sp)
-; RV64IPN-NEXT:    lw a1, 8(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    sw a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add32 a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <2 x i32>
   %tmp2 = bitcast i64 %b to <2 x i32>
@@ -292,52 +96,14 @@
 define signext i32 @subv4i8(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: subv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 8(sp)
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lb a6, 8(sp)
-; RV64IP-NEXT:    lb a7, 12(sp)
-; RV64IP-NEXT:    lb a2, 9(sp)
-; RV64IP-NEXT:    lb a3, 11(sp)
-; RV64IP-NEXT:    lb a4, 15(sp)
-; RV64IP-NEXT:    lb a5, 10(sp)
-; RV64IP-NEXT:    lb a0, 14(sp)
-; RV64IP-NEXT:    lb a1, 13(sp)
-; RV64IP-NEXT:    sub a3, a4, a3
-; RV64IP-NEXT:    sb a3, 7(sp)
-; RV64IP-NEXT:    sub a0, a0, a5
-; RV64IP-NEXT:    sb a0, 6(sp)
-; RV64IP-NEXT:    sub a0, a1, a2
-; RV64IP-NEXT:    sb a0, 5(sp)
-; RV64IP-NEXT:    sub a0, a7, a6
-; RV64IP-NEXT:    sb a0, 4(sp)
-; RV64IP-NEXT:    lw a0, 4(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    sub8 a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: subv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 8(sp)
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lb a6, 8(sp)
-; RV64IPN-NEXT:    lb a7, 12(sp)
-; RV64IPN-NEXT:    lb a2, 9(sp)
-; RV64IPN-NEXT:    lb a3, 11(sp)
-; RV64IPN-NEXT:    lb a4, 15(sp)
-; RV64IPN-NEXT:    lb a5, 10(sp)
-; RV64IPN-NEXT:    lb a0, 14(sp)
-; RV64IPN-NEXT:    lb a1, 13(sp)
-; RV64IPN-NEXT:    sub a3, a4, a3
-; RV64IPN-NEXT:    sb a3, 7(sp)
-; RV64IPN-NEXT:    sub a0, a0, a5
-; RV64IPN-NEXT:    sb a0, 6(sp)
-; RV64IPN-NEXT:    sub a0, a1, a2
-; RV64IPN-NEXT:    sb a0, 5(sp)
-; RV64IPN-NEXT:    sub a0, a7, a6
-; RV64IPN-NEXT:    sb a0, 4(sp)
-; RV64IPN-NEXT:    lw a0, 4(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    sub8 a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -349,36 +115,14 @@
 define signext i32 @subv2i16(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: subv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 8(sp)
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lh a0, 10(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    lh a2, 8(sp)
-; RV64IP-NEXT:    lh a3, 12(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sh a0, 6(sp)
-; RV64IP-NEXT:    sub a0, a3, a2
-; RV64IP-NEXT:    sh a0, 4(sp)
-; RV64IP-NEXT:    lw a0, 4(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    sub16 a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: subv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 8(sp)
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lh a0, 10(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    lh a2, 8(sp)
-; RV64IPN-NEXT:    lh a3, 12(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 6(sp)
-; RV64IPN-NEXT:    sub a0, a3, a2
-; RV64IPN-NEXT:    sh a0, 4(sp)
-; RV64IPN-NEXT:    lw a0, 4(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    sub16 a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -390,84 +134,12 @@
 define i64 @subv8i8(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: subv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lb a0, 23(sp)
-; RV64IP-NEXT:    lb a1, 15(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 31(sp)
-; RV64IP-NEXT:    lb a0, 22(sp)
-; RV64IP-NEXT:    lb a1, 14(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 30(sp)
-; RV64IP-NEXT:    lb a0, 21(sp)
-; RV64IP-NEXT:    lb a1, 13(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 29(sp)
-; RV64IP-NEXT:    lb a0, 20(sp)
-; RV64IP-NEXT:    lb a1, 12(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 28(sp)
-; RV64IP-NEXT:    lb a0, 19(sp)
-; RV64IP-NEXT:    lb a1, 11(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 27(sp)
-; RV64IP-NEXT:    lb a0, 18(sp)
-; RV64IP-NEXT:    lb a1, 10(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 26(sp)
-; RV64IP-NEXT:    lb a0, 17(sp)
-; RV64IP-NEXT:    lb a1, 9(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 25(sp)
-; RV64IP-NEXT:    lb a0, 16(sp)
-; RV64IP-NEXT:    lb a1, 8(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sb a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    sub8 a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: subv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lb a0, 23(sp)
-; RV64IPN-NEXT:    lb a1, 15(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 31(sp)
-; RV64IPN-NEXT:    lb a0, 22(sp)
-; RV64IPN-NEXT:    lb a1, 14(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 30(sp)
-; RV64IPN-NEXT:    lb a0, 21(sp)
-; RV64IPN-NEXT:    lb a1, 13(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 29(sp)
-; RV64IPN-NEXT:    lb a0, 20(sp)
-; RV64IPN-NEXT:    lb a1, 12(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 28(sp)
-; RV64IPN-NEXT:    lb a0, 19(sp)
-; RV64IPN-NEXT:    lb a1, 11(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 27(sp)
-; RV64IPN-NEXT:    lb a0, 18(sp)
-; RV64IPN-NEXT:    lb a1, 10(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 26(sp)
-; RV64IPN-NEXT:    lb a0, 17(sp)
-; RV64IPN-NEXT:    lb a1, 9(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 25(sp)
-; RV64IPN-NEXT:    lb a0, 16(sp)
-; RV64IPN-NEXT:    lb a1, 8(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    sub8 a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -479,52 +151,12 @@
 define i64 @subv4i16(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: subv4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lh a0, 22(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sh a0, 30(sp)
-; RV64IP-NEXT:    lh a0, 20(sp)
-; RV64IP-NEXT:    lh a1, 12(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sh a0, 28(sp)
-; RV64IP-NEXT:    lh a0, 18(sp)
-; RV64IP-NEXT:    lh a1, 10(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sh a0, 26(sp)
-; RV64IP-NEXT:    lh a0, 16(sp)
-; RV64IP-NEXT:    lh a1, 8(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sh a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    sub16 a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: subv4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lh a0, 22(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 30(sp)
-; RV64IPN-NEXT:    lh a0, 20(sp)
-; RV64IPN-NEXT:    lh a1, 12(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 28(sp)
-; RV64IPN-NEXT:    lh a0, 18(sp)
-; RV64IPN-NEXT:    lh a1, 10(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 26(sp)
-; RV64IPN-NEXT:    lh a0, 16(sp)
-; RV64IPN-NEXT:    lh a1, 8(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    sub16 a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -536,36 +168,12 @@
 define i64 @subv2i32(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: subv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 20(sp)
-; RV64IP-NEXT:    lw a1, 12(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sw a0, 28(sp)
-; RV64IP-NEXT:    lw a0, 16(sp)
-; RV64IP-NEXT:    lw a1, 8(sp)
-; RV64IP-NEXT:    sub a0, a1, a0
-; RV64IP-NEXT:    sw a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    sub32 a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: subv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 20(sp)
-; RV64IPN-NEXT:    lw a1, 12(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sw a0, 28(sp)
-; RV64IPN-NEXT:    lw a0, 16(sp)
-; RV64IPN-NEXT:    lw a1, 8(sp)
-; RV64IPN-NEXT:    sub a0, a1, a0
-; RV64IPN-NEXT:    sw a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    sub32 a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <2 x i32>
   %tmp2 = bitcast i64 %b to <2 x i32>
@@ -577,42 +185,22 @@
 define signext i32 @andv4i8(i32 signext %a) nounwind {
 ; RV64IP-LABEL: andv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lbu a0, 15(sp)
-; RV64IP-NEXT:    lbu a1, 12(sp)
-; RV64IP-NEXT:    lbu a2, 14(sp)
-; RV64IP-NEXT:    lbu a3, 13(sp)
-; RV64IP-NEXT:    andi a0, a0, 4
-; RV64IP-NEXT:    sb a0, 11(sp)
-; RV64IP-NEXT:    andi a0, a2, 3
-; RV64IP-NEXT:    sb a0, 10(sp)
-; RV64IP-NEXT:    andi a0, a3, 2
-; RV64IP-NEXT:    sb a0, 9(sp)
-; RV64IP-NEXT:    andi a0, a1, 1
-; RV64IP-NEXT:    sb a0, 8(sp)
-; RV64IP-NEXT:    lwu a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI10_0)(a1)
+; RV64IP-NEXT:    and a0, a0, a1
+; RV64IP-NEXT:    lui a1, 16432
+; RV64IP-NEXT:    addiw a1, a1, 513
+; RV64IP-NEXT:    and a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lbu a0, 15(sp)
-; RV64IPN-NEXT:    lbu a1, 12(sp)
-; RV64IPN-NEXT:    lbu a2, 14(sp)
-; RV64IPN-NEXT:    lbu a3, 13(sp)
-; RV64IPN-NEXT:    andi a0, a0, 4
-; RV64IPN-NEXT:    sb a0, 11(sp)
-; RV64IPN-NEXT:    andi a0, a2, 3
-; RV64IPN-NEXT:    sb a0, 10(sp)
-; RV64IPN-NEXT:    andi a0, a3, 2
-; RV64IPN-NEXT:    sb a0, 9(sp)
-; RV64IPN-NEXT:    andi a0, a1, 1
-; RV64IPN-NEXT:    sb a0, 8(sp)
-; RV64IPN-NEXT:    lwu a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI10_0)(a1)
+; RV64IPN-NEXT:    and a0, a0, a1
+; RV64IPN-NEXT:    lui a1, 16432
+; RV64IPN-NEXT:    addiw a1, a1, 513
+; RV64IPN-NEXT:    and a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <4 x i8>
   %and = and <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
@@ -623,30 +211,22 @@
 define signext i32 @andv2i16(i32 signext %a) nounwind {
 ; RV64IP-LABEL: andv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lhu a0, 14(sp)
-; RV64IP-NEXT:    lhu a1, 12(sp)
-; RV64IP-NEXT:    andi a0, a0, 2
-; RV64IP-NEXT:    sh a0, 10(sp)
-; RV64IP-NEXT:    andi a0, a1, 1
-; RV64IP-NEXT:    sh a0, 8(sp)
-; RV64IP-NEXT:    lwu a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI11_0)(a1)
+; RV64IP-NEXT:    and a0, a0, a1
+; RV64IP-NEXT:    lui a1, 32
+; RV64IP-NEXT:    addiw a1, a1, 1
+; RV64IP-NEXT:    and a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lhu a0, 14(sp)
-; RV64IPN-NEXT:    lhu a1, 12(sp)
-; RV64IPN-NEXT:    andi a0, a0, 2
-; RV64IPN-NEXT:    sh a0, 10(sp)
-; RV64IPN-NEXT:    andi a0, a1, 1
-; RV64IPN-NEXT:    sh a0, 8(sp)
-; RV64IPN-NEXT:    lwu a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI11_0)(a1)
+; RV64IPN-NEXT:    and a0, a0, a1
+; RV64IPN-NEXT:    lui a1, 32
+; RV64IPN-NEXT:    addiw a1, a1, 1
+; RV64IPN-NEXT:    and a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <2 x i16>
   %and = and <2 x i16> %tmp, <i16 1, i16 2>
@@ -657,66 +237,16 @@
 define i64 @andv8i8(i64 %a) nounwind {
 ; RV64IP-LABEL: andv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lbu a0, 7(sp)
-; RV64IP-NEXT:    andi a0, a0, 8
-; RV64IP-NEXT:    sb a0, 15(sp)
-; RV64IP-NEXT:    lbu a0, 6(sp)
-; RV64IP-NEXT:    andi a0, a0, 7
-; RV64IP-NEXT:    sb a0, 14(sp)
-; RV64IP-NEXT:    lbu a0, 5(sp)
-; RV64IP-NEXT:    andi a0, a0, 6
-; RV64IP-NEXT:    sb a0, 13(sp)
-; RV64IP-NEXT:    lbu a0, 4(sp)
-; RV64IP-NEXT:    andi a0, a0, 5
-; RV64IP-NEXT:    sb a0, 12(sp)
-; RV64IP-NEXT:    lbu a0, 3(sp)
-; RV64IP-NEXT:    andi a0, a0, 4
-; RV64IP-NEXT:    sb a0, 11(sp)
-; RV64IP-NEXT:    lbu a0, 2(sp)
-; RV64IP-NEXT:    andi a0, a0, 3
-; RV64IP-NEXT:    sb a0, 10(sp)
-; RV64IP-NEXT:    lbu a0, 1(sp)
-; RV64IP-NEXT:    andi a0, a0, 2
-; RV64IP-NEXT:    sb a0, 9(sp)
-; RV64IP-NEXT:    lbu a0, 0(sp)
-; RV64IP-NEXT:    andi a0, a0, 1
-; RV64IP-NEXT:    sb a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI12_0)(a1)
+; RV64IP-NEXT:    and a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lbu a0, 7(sp)
-; RV64IPN-NEXT:    andi a0, a0, 8
-; RV64IPN-NEXT:    sb a0, 15(sp)
-; RV64IPN-NEXT:    lbu a0, 6(sp)
-; RV64IPN-NEXT:    andi a0, a0, 7
-; RV64IPN-NEXT:    sb a0, 14(sp)
-; RV64IPN-NEXT:    lbu a0, 5(sp)
-; RV64IPN-NEXT:    andi a0, a0, 6
-; RV64IPN-NEXT:    sb a0, 13(sp)
-; RV64IPN-NEXT:    lbu a0, 4(sp)
-; RV64IPN-NEXT:    andi a0, a0, 5
-; RV64IPN-NEXT:    sb a0, 12(sp)
-; RV64IPN-NEXT:    lbu a0, 3(sp)
-; RV64IPN-NEXT:    andi a0, a0, 4
-; RV64IPN-NEXT:    sb a0, 11(sp)
-; RV64IPN-NEXT:    lbu a0, 2(sp)
-; RV64IPN-NEXT:    andi a0, a0, 3
-; RV64IPN-NEXT:    sb a0, 10(sp)
-; RV64IPN-NEXT:    lbu a0, 1(sp)
-; RV64IPN-NEXT:    andi a0, a0, 2
-; RV64IPN-NEXT:    sb a0, 9(sp)
-; RV64IPN-NEXT:    lbu a0, 0(sp)
-; RV64IPN-NEXT:    andi a0, a0, 1
-; RV64IPN-NEXT:    sb a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI12_0)(a1)
+; RV64IPN-NEXT:    and a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <8 x i8>
   %and = and <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
@@ -727,42 +257,16 @@
 define i64 @andv4i16(i64 %a) nounwind {
 ; RV64IP-LABEL: andv4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lhu a0, 6(sp)
-; RV64IP-NEXT:    andi a0, a0, 4
-; RV64IP-NEXT:    sh a0, 14(sp)
-; RV64IP-NEXT:    lhu a0, 4(sp)
-; RV64IP-NEXT:    andi a0, a0, 3
-; RV64IP-NEXT:    sh a0, 12(sp)
-; RV64IP-NEXT:    lhu a0, 2(sp)
-; RV64IP-NEXT:    andi a0, a0, 2
-; RV64IP-NEXT:    sh a0, 10(sp)
-; RV64IP-NEXT:    lhu a0, 0(sp)
-; RV64IP-NEXT:    andi a0, a0, 1
-; RV64IP-NEXT:    sh a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI13_0)(a1)
+; RV64IP-NEXT:    and a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andv4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lhu a0, 6(sp)
-; RV64IPN-NEXT:    andi a0, a0, 4
-; RV64IPN-NEXT:    sh a0, 14(sp)
-; RV64IPN-NEXT:    lhu a0, 4(sp)
-; RV64IPN-NEXT:    andi a0, a0, 3
-; RV64IPN-NEXT:    sh a0, 12(sp)
-; RV64IPN-NEXT:    lhu a0, 2(sp)
-; RV64IPN-NEXT:    andi a0, a0, 2
-; RV64IPN-NEXT:    sh a0, 10(sp)
-; RV64IPN-NEXT:    lhu a0, 0(sp)
-; RV64IPN-NEXT:    andi a0, a0, 1
-; RV64IPN-NEXT:    sh a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI13_0)(a1)
+; RV64IPN-NEXT:    and a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <4 x i16>
   %and = and <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
@@ -773,30 +277,16 @@
 define i64 @andv2i32(i64 %a) nounwind {
 ; RV64IP-LABEL: andv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lwu a0, 4(sp)
-; RV64IP-NEXT:    andi a0, a0, 2
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lwu a0, 0(sp)
-; RV64IP-NEXT:    andi a0, a0, 1
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI14_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI14_0)(a1)
+; RV64IP-NEXT:    and a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lwu a0, 4(sp)
-; RV64IPN-NEXT:    andi a0, a0, 2
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lwu a0, 0(sp)
-; RV64IPN-NEXT:    andi a0, a0, 1
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI14_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI14_0)(a1)
+; RV64IPN-NEXT:    and a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <2 x i32>
   %and = and <2 x i32> %tmp, <i32 1, i32 2>
@@ -807,42 +297,18 @@
 define signext i32 @orv4i8(i32 signext %a) nounwind {
 ; RV64IP-LABEL: orv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lb a0, 15(sp)
-; RV64IP-NEXT:    lb a1, 12(sp)
-; RV64IP-NEXT:    lb a2, 14(sp)
-; RV64IP-NEXT:    lb a3, 13(sp)
-; RV64IP-NEXT:    ori a0, a0, 4
-; RV64IP-NEXT:    sb a0, 11(sp)
-; RV64IP-NEXT:    ori a0, a2, 3
-; RV64IP-NEXT:    sb a0, 10(sp)
-; RV64IP-NEXT:    ori a0, a3, 2
-; RV64IP-NEXT:    sb a0, 9(sp)
-; RV64IP-NEXT:    ori a0, a1, 1
-; RV64IP-NEXT:    sb a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI15_0)(a1)
+; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: orv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lb a0, 15(sp)
-; RV64IPN-NEXT:    lb a1, 12(sp)
-; RV64IPN-NEXT:    lb a2, 14(sp)
-; RV64IPN-NEXT:    lb a3, 13(sp)
-; RV64IPN-NEXT:    ori a0, a0, 4
-; RV64IPN-NEXT:    sb a0, 11(sp)
-; RV64IPN-NEXT:    ori a0, a2, 3
-; RV64IPN-NEXT:    sb a0, 10(sp)
-; RV64IPN-NEXT:    ori a0, a3, 2
-; RV64IPN-NEXT:    sb a0, 9(sp)
-; RV64IPN-NEXT:    ori a0, a1, 1
-; RV64IPN-NEXT:    sb a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI15_0)(a1)
+; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <4 x i8>
   %or = or <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
@@ -853,30 +319,18 @@
 define signext i32 @orv2i16(i32 signext %a) nounwind {
 ; RV64IP-LABEL: orv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lh a0, 14(sp)
-; RV64IP-NEXT:    lh a1, 12(sp)
-; RV64IP-NEXT:    ori a0, a0, 2
-; RV64IP-NEXT:    sh a0, 10(sp)
-; RV64IP-NEXT:    ori a0, a1, 1
-; RV64IP-NEXT:    sh a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI16_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI16_0)(a1)
+; RV64IP-NEXT:    or a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: orv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lh a0, 14(sp)
-; RV64IPN-NEXT:    lh a1, 12(sp)
-; RV64IPN-NEXT:    ori a0, a0, 2
-; RV64IPN-NEXT:    sh a0, 10(sp)
-; RV64IPN-NEXT:    ori a0, a1, 1
-; RV64IPN-NEXT:    sh a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI16_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI16_0)(a1)
+; RV64IPN-NEXT:    or a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <2 x i16>
   %or = or <2 x i16> %tmp, <i16 1, i16 2>
@@ -887,66 +341,16 @@
 define i64 @orv8i8(i64 %a) nounwind {
 ; RV64IP-LABEL: orv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lb a0, 7(sp)
-; RV64IP-NEXT:    ori a0, a0, 8
-; RV64IP-NEXT:    sb a0, 15(sp)
-; RV64IP-NEXT:    lb a0, 6(sp)
-; RV64IP-NEXT:    ori a0, a0, 7
-; RV64IP-NEXT:    sb a0, 14(sp)
-; RV64IP-NEXT:    lb a0, 5(sp)
-; RV64IP-NEXT:    ori a0, a0, 6
-; RV64IP-NEXT:    sb a0, 13(sp)
-; RV64IP-NEXT:    lb a0, 4(sp)
-; RV64IP-NEXT:    ori a0, a0, 5
-; RV64IP-NEXT:    sb a0, 12(sp)
-; RV64IP-NEXT:    lb a0, 3(sp)
-; RV64IP-NEXT:    ori a0, a0, 4
-; RV64IP-NEXT:    sb a0, 11(sp)
-; RV64IP-NEXT:    lb a0, 2(sp)
-; RV64IP-NEXT:    ori a0, a0, 3
-; RV64IP-NEXT:    sb a0, 10(sp)
-; RV64IP-NEXT:    lb a0, 1(sp)
-; RV64IP-NEXT:    ori a0, a0, 2
-; RV64IP-NEXT:    sb a0, 9(sp)
-; RV64IP-NEXT:    lb a0, 0(sp)
-; RV64IP-NEXT:    ori a0, a0, 1
-; RV64IP-NEXT:    sb a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI17_0)(a1)
+; RV64IP-NEXT:    or a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: orv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lb a0, 7(sp)
-; RV64IPN-NEXT:    ori a0, a0, 8
-; RV64IPN-NEXT:    sb a0, 15(sp)
-; RV64IPN-NEXT:    lb a0, 6(sp)
-; RV64IPN-NEXT:    ori a0, a0, 7
-; RV64IPN-NEXT:    sb a0, 14(sp)
-; RV64IPN-NEXT:    lb a0, 5(sp)
-; RV64IPN-NEXT:    ori a0, a0, 6
-; RV64IPN-NEXT:    sb a0, 13(sp)
-; RV64IPN-NEXT:    lb a0, 4(sp)
-; RV64IPN-NEXT:    ori a0, a0, 5
-; RV64IPN-NEXT:    sb a0, 12(sp)
-; RV64IPN-NEXT:    lb a0, 3(sp)
-; RV64IPN-NEXT:    ori a0, a0, 4
-; RV64IPN-NEXT:    sb a0, 11(sp)
-; RV64IPN-NEXT:    lb a0, 2(sp)
-; RV64IPN-NEXT:    ori a0, a0, 3
-; RV64IPN-NEXT:    sb a0, 10(sp)
-; RV64IPN-NEXT:    lb a0, 1(sp)
-; RV64IPN-NEXT:    ori a0, a0, 2
-; RV64IPN-NEXT:    sb a0, 9(sp)
-; RV64IPN-NEXT:    lb a0, 0(sp)
-; RV64IPN-NEXT:    ori a0, a0, 1
-; RV64IPN-NEXT:    sb a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI17_0)(a1)
+; RV64IPN-NEXT:    or a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <8 x i8>
   %or = or <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
@@ -957,42 +361,16 @@
 define i64 @orv4i16(i64 %a) nounwind {
 ; RV64IP-LABEL: orv4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lh a0, 6(sp)
-; RV64IP-NEXT:    ori a0, a0, 4
-; RV64IP-NEXT:    sh a0, 14(sp)
-; RV64IP-NEXT:    lh a0, 4(sp)
-; RV64IP-NEXT:    ori a0, a0, 3
-; RV64IP-NEXT:    sh a0, 12(sp)
-; RV64IP-NEXT:    lh a0, 2(sp)
-; RV64IP-NEXT:    ori a0, a0, 2
-; RV64IP-NEXT:    sh a0, 10(sp)
-; RV64IP-NEXT:    lh a0, 0(sp)
-; RV64IP-NEXT:    ori a0, a0, 1
-; RV64IP-NEXT:    sh a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI18_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI18_0)(a1)
+; RV64IP-NEXT:    or a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: orv4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lh a0, 6(sp)
-; RV64IPN-NEXT:    ori a0, a0, 4
-; RV64IPN-NEXT:    sh a0, 14(sp)
-; RV64IPN-NEXT:    lh a0, 4(sp)
-; RV64IPN-NEXT:    ori a0, a0, 3
-; RV64IPN-NEXT:    sh a0, 12(sp)
-; RV64IPN-NEXT:    lh a0, 2(sp)
-; RV64IPN-NEXT:    ori a0, a0, 2
-; RV64IPN-NEXT:    sh a0, 10(sp)
-; RV64IPN-NEXT:    lh a0, 0(sp)
-; RV64IPN-NEXT:    ori a0, a0, 1
-; RV64IPN-NEXT:    sh a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI18_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI18_0)(a1)
+; RV64IPN-NEXT:    or a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <4 x i16>
   %or = or <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
@@ -1003,30 +381,16 @@
 define i64 @orv2i32(i64 %a) nounwind {
 ; RV64IP-LABEL: orv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 4(sp)
-; RV64IP-NEXT:    ori a0, a0, 2
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    ori a0, a0, 1
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI19_0)(a1)
+; RV64IP-NEXT:    or a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: orv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 4(sp)
-; RV64IPN-NEXT:    ori a0, a0, 2
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    ori a0, a0, 1
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI19_0)(a1)
+; RV64IPN-NEXT:    or a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <2 x i32>
   %or = or <2 x i32> %tmp, <i32 1, i32 2>
@@ -1037,42 +401,18 @@
 define signext i32 @xorv4i8(i32 signext %a) nounwind {
 ; RV64IP-LABEL: xorv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lb a0, 15(sp)
-; RV64IP-NEXT:    lb a1, 12(sp)
-; RV64IP-NEXT:    lb a2, 14(sp)
-; RV64IP-NEXT:    lb a3, 13(sp)
-; RV64IP-NEXT:    xori a0, a0, 4
-; RV64IP-NEXT:    sb a0, 11(sp)
-; RV64IP-NEXT:    xori a0, a2, 3
-; RV64IP-NEXT:    sb a0, 10(sp)
-; RV64IP-NEXT:    xori a0, a3, 2
-; RV64IP-NEXT:    sb a0, 9(sp)
-; RV64IP-NEXT:    xori a0, a1, 1
-; RV64IP-NEXT:    sb a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI20_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI20_0)(a1)
+; RV64IP-NEXT:    xor a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xorv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lb a0, 15(sp)
-; RV64IPN-NEXT:    lb a1, 12(sp)
-; RV64IPN-NEXT:    lb a2, 14(sp)
-; RV64IPN-NEXT:    lb a3, 13(sp)
-; RV64IPN-NEXT:    xori a0, a0, 4
-; RV64IPN-NEXT:    sb a0, 11(sp)
-; RV64IPN-NEXT:    xori a0, a2, 3
-; RV64IPN-NEXT:    sb a0, 10(sp)
-; RV64IPN-NEXT:    xori a0, a3, 2
-; RV64IPN-NEXT:    sb a0, 9(sp)
-; RV64IPN-NEXT:    xori a0, a1, 1
-; RV64IPN-NEXT:    sb a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI20_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI20_0)(a1)
+; RV64IPN-NEXT:    xor a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <4 x i8>
   %xor = xor <4 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4>
@@ -1083,30 +423,18 @@
 define signext i32 @xorv2i16(i32 signext %a) nounwind {
 ; RV64IP-LABEL: xorv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lh a0, 14(sp)
-; RV64IP-NEXT:    lh a1, 12(sp)
-; RV64IP-NEXT:    xori a0, a0, 2
-; RV64IP-NEXT:    sh a0, 10(sp)
-; RV64IP-NEXT:    xori a0, a1, 1
-; RV64IP-NEXT:    sh a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI21_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI21_0)(a1)
+; RV64IP-NEXT:    xor a0, a0, a1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xorv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lh a0, 14(sp)
-; RV64IPN-NEXT:    lh a1, 12(sp)
-; RV64IPN-NEXT:    xori a0, a0, 2
-; RV64IPN-NEXT:    sh a0, 10(sp)
-; RV64IPN-NEXT:    xori a0, a1, 1
-; RV64IPN-NEXT:    sh a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI21_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI21_0)(a1)
+; RV64IPN-NEXT:    xor a0, a0, a1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i32 %a to <2 x i16>
   %xor = xor <2 x i16> %tmp, <i16 1, i16 2>
@@ -1117,66 +445,16 @@
 define i64 @xorv8i8(i64 %a) nounwind {
 ; RV64IP-LABEL: xorv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lb a0, 7(sp)
-; RV64IP-NEXT:    xori a0, a0, 8
-; RV64IP-NEXT:    sb a0, 15(sp)
-; RV64IP-NEXT:    lb a0, 6(sp)
-; RV64IP-NEXT:    xori a0, a0, 7
-; RV64IP-NEXT:    sb a0, 14(sp)
-; RV64IP-NEXT:    lb a0, 5(sp)
-; RV64IP-NEXT:    xori a0, a0, 6
-; RV64IP-NEXT:    sb a0, 13(sp)
-; RV64IP-NEXT:    lb a0, 4(sp)
-; RV64IP-NEXT:    xori a0, a0, 5
-; RV64IP-NEXT:    sb a0, 12(sp)
-; RV64IP-NEXT:    lb a0, 3(sp)
-; RV64IP-NEXT:    xori a0, a0, 4
-; RV64IP-NEXT:    sb a0, 11(sp)
-; RV64IP-NEXT:    lb a0, 2(sp)
-; RV64IP-NEXT:    xori a0, a0, 3
-; RV64IP-NEXT:    sb a0, 10(sp)
-; RV64IP-NEXT:    lb a0, 1(sp)
-; RV64IP-NEXT:    xori a0, a0, 2
-; RV64IP-NEXT:    sb a0, 9(sp)
-; RV64IP-NEXT:    lb a0, 0(sp)
-; RV64IP-NEXT:    xori a0, a0, 1
-; RV64IP-NEXT:    sb a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI22_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI22_0)(a1)
+; RV64IP-NEXT:    xor a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xorv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lb a0, 7(sp)
-; RV64IPN-NEXT:    xori a0, a0, 8
-; RV64IPN-NEXT:    sb a0, 15(sp)
-; RV64IPN-NEXT:    lb a0, 6(sp)
-; RV64IPN-NEXT:    xori a0, a0, 7
-; RV64IPN-NEXT:    sb a0, 14(sp)
-; RV64IPN-NEXT:    lb a0, 5(sp)
-; RV64IPN-NEXT:    xori a0, a0, 6
-; RV64IPN-NEXT:    sb a0, 13(sp)
-; RV64IPN-NEXT:    lb a0, 4(sp)
-; RV64IPN-NEXT:    xori a0, a0, 5
-; RV64IPN-NEXT:    sb a0, 12(sp)
-; RV64IPN-NEXT:    lb a0, 3(sp)
-; RV64IPN-NEXT:    xori a0, a0, 4
-; RV64IPN-NEXT:    sb a0, 11(sp)
-; RV64IPN-NEXT:    lb a0, 2(sp)
-; RV64IPN-NEXT:    xori a0, a0, 3
-; RV64IPN-NEXT:    sb a0, 10(sp)
-; RV64IPN-NEXT:    lb a0, 1(sp)
-; RV64IPN-NEXT:    xori a0, a0, 2
-; RV64IPN-NEXT:    sb a0, 9(sp)
-; RV64IPN-NEXT:    lb a0, 0(sp)
-; RV64IPN-NEXT:    xori a0, a0, 1
-; RV64IPN-NEXT:    sb a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI22_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI22_0)(a1)
+; RV64IPN-NEXT:    xor a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <8 x i8>
   %xor = xor <8 x i8> %tmp, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
@@ -1187,42 +465,16 @@
 define i64 @xorv4i16(i64 %a) nounwind {
 ; RV64IP-LABEL: xorv4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lh a0, 6(sp)
-; RV64IP-NEXT:    xori a0, a0, 4
-; RV64IP-NEXT:    sh a0, 14(sp)
-; RV64IP-NEXT:    lh a0, 4(sp)
-; RV64IP-NEXT:    xori a0, a0, 3
-; RV64IP-NEXT:    sh a0, 12(sp)
-; RV64IP-NEXT:    lh a0, 2(sp)
-; RV64IP-NEXT:    xori a0, a0, 2
-; RV64IP-NEXT:    sh a0, 10(sp)
-; RV64IP-NEXT:    lh a0, 0(sp)
-; RV64IP-NEXT:    xori a0, a0, 1
-; RV64IP-NEXT:    sh a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI23_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI23_0)(a1)
+; RV64IP-NEXT:    xor a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xorv4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lh a0, 6(sp)
-; RV64IPN-NEXT:    xori a0, a0, 4
-; RV64IPN-NEXT:    sh a0, 14(sp)
-; RV64IPN-NEXT:    lh a0, 4(sp)
-; RV64IPN-NEXT:    xori a0, a0, 3
-; RV64IPN-NEXT:    sh a0, 12(sp)
-; RV64IPN-NEXT:    lh a0, 2(sp)
-; RV64IPN-NEXT:    xori a0, a0, 2
-; RV64IPN-NEXT:    sh a0, 10(sp)
-; RV64IPN-NEXT:    lh a0, 0(sp)
-; RV64IPN-NEXT:    xori a0, a0, 1
-; RV64IPN-NEXT:    sh a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI23_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI23_0)(a1)
+; RV64IPN-NEXT:    xor a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <4 x i16>
   %xor = xor <4 x i16> %tmp, <i16 1, i16 2, i16 3, i16 4>
@@ -1233,30 +485,16 @@
 define i64 @xorv2i32(i64 %a) nounwind {
 ; RV64IP-LABEL: xorv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sd a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 4(sp)
-; RV64IP-NEXT:    xori a0, a0, 2
-; RV64IP-NEXT:    sw a0, 12(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    xori a0, a0, 1
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    ld a0, 8(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    lui a1, %hi(.LCPI24_0)
+; RV64IP-NEXT:    ld a1, %lo(.LCPI24_0)(a1)
+; RV64IP-NEXT:    xor a0, a0, a1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xorv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sd a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 4(sp)
-; RV64IPN-NEXT:    xori a0, a0, 2
-; RV64IPN-NEXT:    sw a0, 12(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    xori a0, a0, 1
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    ld a0, 8(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    lui a1, %hi(.LCPI24_0)
+; RV64IPN-NEXT:    ld a1, %lo(.LCPI24_0)(a1)
+; RV64IPN-NEXT:    xor a0, a0, a1
 ; RV64IPN-NEXT:    ret
   %tmp = bitcast i64 %a to <2 x i32>
   %xor = xor <2 x i32> %tmp, <i32 1, i32 2>
@@ -1272,72 +510,14 @@
 define signext i32 @andiv4i8(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: andiv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 4(sp)
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    lb a0, 7(sp)
-; RV64IP-NEXT:    lb a1, 11(sp)
-; RV64IP-NEXT:    lb a2, 6(sp)
-; RV64IP-NEXT:    lb a3, 10(sp)
-; RV64IP-NEXT:    lb t0, 5(sp)
-; RV64IP-NEXT:    lb a5, 9(sp)
-; RV64IP-NEXT:    lb a6, 4(sp)
-; RV64IP-NEXT:    lb a7, 8(sp)
-; RV64IP-NEXT:    addi a4, zero, 1
-; RV64IP-NEXT:    sw a4, 12(sp)
-; RV64IP-NEXT:    lb a4, 15(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    and a0, a0, a4
-; RV64IP-NEXT:    sb a0, 3(sp)
-; RV64IP-NEXT:    lb a0, 14(sp)
-; RV64IP-NEXT:    add a1, a3, a2
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 2(sp)
-; RV64IP-NEXT:    lb a0, 13(sp)
-; RV64IP-NEXT:    add a1, a5, t0
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 1(sp)
-; RV64IP-NEXT:    lb a0, 12(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 0(sp)
-; RV64IP-NEXT:    lwu a0, 0(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    andi a0, a0, 1
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andiv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 4(sp)
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    lb a0, 7(sp)
-; RV64IPN-NEXT:    lb a1, 11(sp)
-; RV64IPN-NEXT:    lb a2, 6(sp)
-; RV64IPN-NEXT:    lb a3, 10(sp)
-; RV64IPN-NEXT:    lb t0, 5(sp)
-; RV64IPN-NEXT:    lb a5, 9(sp)
-; RV64IPN-NEXT:    lb a6, 4(sp)
-; RV64IPN-NEXT:    lb a7, 8(sp)
-; RV64IPN-NEXT:    addi a4, zero, 1
-; RV64IPN-NEXT:    sw a4, 12(sp)
-; RV64IPN-NEXT:    lb a4, 15(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    and a0, a0, a4
-; RV64IPN-NEXT:    sb a0, 3(sp)
-; RV64IPN-NEXT:    lb a0, 14(sp)
-; RV64IPN-NEXT:    add a1, a3, a2
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 2(sp)
-; RV64IPN-NEXT:    lb a0, 13(sp)
-; RV64IPN-NEXT:    add a1, a5, t0
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 1(sp)
-; RV64IPN-NEXT:    lb a0, 12(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 0(sp)
-; RV64IPN-NEXT:    lwu a0, 0(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    andi a0, a0, 1
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -1351,52 +531,16 @@
 define signext i32 @andiv2i16(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: andiv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 4(sp)
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    lh a0, 6(sp)
-; RV64IP-NEXT:    lh a1, 10(sp)
-; RV64IP-NEXT:    lh a2, 4(sp)
-; RV64IP-NEXT:    lh a3, 8(sp)
-; RV64IP-NEXT:    addi a4, zero, 1
-; RV64IP-NEXT:    slli a4, a4, 32
-; RV64IP-NEXT:    addi a4, a4, -2
-; RV64IP-NEXT:    sw a4, 12(sp)
-; RV64IP-NEXT:    lh a4, 14(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    and a0, a0, a4
-; RV64IP-NEXT:    sh a0, 2(sp)
-; RV64IP-NEXT:    lh a0, 12(sp)
-; RV64IP-NEXT:    add a1, a3, a2
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sh a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    andi a0, a0, -2
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andiv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 4(sp)
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    lh a0, 6(sp)
-; RV64IPN-NEXT:    lh a1, 10(sp)
-; RV64IPN-NEXT:    lh a2, 4(sp)
-; RV64IPN-NEXT:    lh a3, 8(sp)
-; RV64IPN-NEXT:    addi a4, zero, 1
-; RV64IPN-NEXT:    slli a4, a4, 32
-; RV64IPN-NEXT:    addi a4, a4, -2
-; RV64IPN-NEXT:    sw a4, 12(sp)
-; RV64IPN-NEXT:    lh a4, 14(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    and a0, a0, a4
-; RV64IPN-NEXT:    sh a0, 2(sp)
-; RV64IPN-NEXT:    lh a0, 12(sp)
-; RV64IPN-NEXT:    add a1, a3, a2
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    andi a0, a0, -2
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -1410,128 +554,14 @@
 define i64 @andiv8i8(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: andiv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -48
-; RV64IP-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
-; RV64IP-NEXT:    sd s1, 32(sp) # 8-byte Folded Spill
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lb a6, 16(sp)
-; RV64IP-NEXT:    lb a7, 8(sp)
-; RV64IP-NEXT:    lb t0, 17(sp)
-; RV64IP-NEXT:    lb t1, 9(sp)
-; RV64IP-NEXT:    lb t2, 18(sp)
-; RV64IP-NEXT:    lb t3, 10(sp)
-; RV64IP-NEXT:    lb t4, 19(sp)
-; RV64IP-NEXT:    lb t5, 11(sp)
-; RV64IP-NEXT:    lb t6, 20(sp)
-; RV64IP-NEXT:    lb a3, 12(sp)
-; RV64IP-NEXT:    lb a4, 21(sp)
-; RV64IP-NEXT:    lb a5, 13(sp)
-; RV64IP-NEXT:    lb a0, 22(sp)
-; RV64IP-NEXT:    lb a1, 14(sp)
-; RV64IP-NEXT:    lb a2, 23(sp)
-; RV64IP-NEXT:    lb s0, 15(sp)
-; RV64IP-NEXT:    addi s1, zero, -3
-; RV64IP-NEXT:    sd s1, 0(sp)
-; RV64IP-NEXT:    lb s1, 7(sp)
-; RV64IP-NEXT:    add a2, s0, a2
-; RV64IP-NEXT:    and a2, a2, s1
-; RV64IP-NEXT:    sb a2, 31(sp)
-; RV64IP-NEXT:    lb a2, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    sb a0, 30(sp)
-; RV64IP-NEXT:    lb a0, 5(sp)
-; RV64IP-NEXT:    add a1, a5, a4
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 29(sp)
-; RV64IP-NEXT:    lb a0, 4(sp)
-; RV64IP-NEXT:    add a1, a3, t6
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 28(sp)
-; RV64IP-NEXT:    lb a0, 3(sp)
-; RV64IP-NEXT:    add a1, t5, t4
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 27(sp)
-; RV64IP-NEXT:    lb a0, 2(sp)
-; RV64IP-NEXT:    add a1, t3, t2
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 26(sp)
-; RV64IP-NEXT:    lb a0, 1(sp)
-; RV64IP-NEXT:    add a1, t1, t0
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 25(sp)
-; RV64IP-NEXT:    lb a0, 0(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sb a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    ld s1, 32(sp) # 8-byte Folded Reload
-; RV64IP-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
-; RV64IP-NEXT:    addi sp, sp, 48
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    andi a0, a0, -3
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andiv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -48
-; RV64IPN-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
-; RV64IPN-NEXT:    sd s1, 32(sp) # 8-byte Folded Spill
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lb a6, 16(sp)
-; RV64IPN-NEXT:    lb a7, 8(sp)
-; RV64IPN-NEXT:    lb t0, 17(sp)
-; RV64IPN-NEXT:    lb t1, 9(sp)
-; RV64IPN-NEXT:    lb t2, 18(sp)
-; RV64IPN-NEXT:    lb t3, 10(sp)
-; RV64IPN-NEXT:    lb t4, 19(sp)
-; RV64IPN-NEXT:    lb t5, 11(sp)
-; RV64IPN-NEXT:    lb t6, 20(sp)
-; RV64IPN-NEXT:    lb a3, 12(sp)
-; RV64IPN-NEXT:    lb a4, 21(sp)
-; RV64IPN-NEXT:    lb a5, 13(sp)
-; RV64IPN-NEXT:    lb a0, 22(sp)
-; RV64IPN-NEXT:    lb a1, 14(sp)
-; RV64IPN-NEXT:    lb a2, 23(sp)
-; RV64IPN-NEXT:    lb s0, 15(sp)
-; RV64IPN-NEXT:    addi s1, zero, -3
-; RV64IPN-NEXT:    sd s1, 0(sp)
-; RV64IPN-NEXT:    lb s1, 7(sp)
-; RV64IPN-NEXT:    add a2, s0, a2
-; RV64IPN-NEXT:    and a2, a2, s1
-; RV64IPN-NEXT:    sb a2, 31(sp)
-; RV64IPN-NEXT:    lb a2, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    sb a0, 30(sp)
-; RV64IPN-NEXT:    lb a0, 5(sp)
-; RV64IPN-NEXT:    add a1, a5, a4
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 29(sp)
-; RV64IPN-NEXT:    lb a0, 4(sp)
-; RV64IPN-NEXT:    add a1, a3, t6
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 28(sp)
-; RV64IPN-NEXT:    lb a0, 3(sp)
-; RV64IPN-NEXT:    add a1, t5, t4
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 27(sp)
-; RV64IPN-NEXT:    lb a0, 2(sp)
-; RV64IPN-NEXT:    add a1, t3, t2
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 26(sp)
-; RV64IPN-NEXT:    lb a0, 1(sp)
-; RV64IPN-NEXT:    add a1, t1, t0
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 25(sp)
-; RV64IPN-NEXT:    lb a0, 0(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    ld s1, 32(sp) # 8-byte Folded Reload
-; RV64IPN-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
-; RV64IPN-NEXT:    addi sp, sp, 48
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    andi a0, a0, -3
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -1545,72 +575,14 @@
 define i64 @andvi4i16(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: andvi4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lh a6, 16(sp)
-; RV64IP-NEXT:    lh a7, 8(sp)
-; RV64IP-NEXT:    lh t0, 18(sp)
-; RV64IP-NEXT:    lh a3, 10(sp)
-; RV64IP-NEXT:    lh a4, 20(sp)
-; RV64IP-NEXT:    lh a5, 12(sp)
-; RV64IP-NEXT:    lh a0, 22(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    addi a2, zero, -4
-; RV64IP-NEXT:    sd a2, 0(sp)
-; RV64IP-NEXT:    lh a2, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    sh a0, 30(sp)
-; RV64IP-NEXT:    lh a0, 4(sp)
-; RV64IP-NEXT:    add a1, a5, a4
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sh a0, 28(sp)
-; RV64IP-NEXT:    lh a0, 2(sp)
-; RV64IP-NEXT:    add a1, a3, t0
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sh a0, 26(sp)
-; RV64IP-NEXT:    lh a0, 0(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    and a0, a1, a0
-; RV64IP-NEXT:    sh a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    andi a0, a0, -4
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andvi4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lh a6, 16(sp)
-; RV64IPN-NEXT:    lh a7, 8(sp)
-; RV64IPN-NEXT:    lh t0, 18(sp)
-; RV64IPN-NEXT:    lh a3, 10(sp)
-; RV64IPN-NEXT:    lh a4, 20(sp)
-; RV64IPN-NEXT:    lh a5, 12(sp)
-; RV64IPN-NEXT:    lh a0, 22(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    addi a2, zero, -4
-; RV64IPN-NEXT:    sd a2, 0(sp)
-; RV64IPN-NEXT:    lh a2, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    sh a0, 30(sp)
-; RV64IPN-NEXT:    lh a0, 4(sp)
-; RV64IPN-NEXT:    add a1, a5, a4
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 28(sp)
-; RV64IPN-NEXT:    lh a0, 2(sp)
-; RV64IPN-NEXT:    add a1, a3, t0
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 26(sp)
-; RV64IPN-NEXT:    lh a0, 0(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    and a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    andi a0, a0, -4
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -1624,48 +596,14 @@
 define i64 @andiv2i32(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: andiv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 16(sp)
-; RV64IP-NEXT:    lw a1, 8(sp)
-; RV64IP-NEXT:    lw a2, 20(sp)
-; RV64IP-NEXT:    lw a3, 12(sp)
-; RV64IP-NEXT:    addi a4, zero, -5
-; RV64IP-NEXT:    sd a4, 0(sp)
-; RV64IP-NEXT:    lw a4, 4(sp)
-; RV64IP-NEXT:    add a2, a3, a2
-; RV64IP-NEXT:    and a2, a2, a4
-; RV64IP-NEXT:    sw a2, 28(sp)
-; RV64IP-NEXT:    lw a2, 0(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    and a0, a0, a2
-; RV64IP-NEXT:    sw a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add32 a0, a0, a1
+; RV64IP-NEXT:    andi a0, a0, -5
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: andiv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 16(sp)
-; RV64IPN-NEXT:    lw a1, 8(sp)
-; RV64IPN-NEXT:    lw a2, 20(sp)
-; RV64IPN-NEXT:    lw a3, 12(sp)
-; RV64IPN-NEXT:    addi a4, zero, -5
-; RV64IPN-NEXT:    sd a4, 0(sp)
-; RV64IPN-NEXT:    lw a4, 4(sp)
-; RV64IPN-NEXT:    add a2, a3, a2
-; RV64IPN-NEXT:    and a2, a2, a4
-; RV64IPN-NEXT:    sw a2, 28(sp)
-; RV64IPN-NEXT:    lw a2, 0(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    and a0, a0, a2
-; RV64IPN-NEXT:    sw a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add32 a0, a0, a1
+; RV64IPN-NEXT:    andi a0, a0, -5
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <2 x i32>
   %tmp2 = bitcast i64 %b to <2 x i32>
@@ -1679,72 +617,16 @@
 define signext i32 @oriv4i8(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: oriv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 4(sp)
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    lb a0, 7(sp)
-; RV64IP-NEXT:    lb a1, 11(sp)
-; RV64IP-NEXT:    lb a2, 6(sp)
-; RV64IP-NEXT:    lb a3, 10(sp)
-; RV64IP-NEXT:    lb t0, 5(sp)
-; RV64IP-NEXT:    lb a5, 9(sp)
-; RV64IP-NEXT:    lb a6, 4(sp)
-; RV64IP-NEXT:    lb a7, 8(sp)
-; RV64IP-NEXT:    addi a4, zero, 1
-; RV64IP-NEXT:    sw a4, 12(sp)
-; RV64IP-NEXT:    lb a4, 15(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    or a0, a0, a4
-; RV64IP-NEXT:    sb a0, 3(sp)
-; RV64IP-NEXT:    lb a0, 14(sp)
-; RV64IP-NEXT:    add a1, a3, a2
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 2(sp)
-; RV64IP-NEXT:    lb a0, 13(sp)
-; RV64IP-NEXT:    add a1, a5, t0
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 1(sp)
-; RV64IP-NEXT:    lb a0, 12(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    ori a0, a0, 1
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: oriv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 4(sp)
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    lb a0, 7(sp)
-; RV64IPN-NEXT:    lb a1, 11(sp)
-; RV64IPN-NEXT:    lb a2, 6(sp)
-; RV64IPN-NEXT:    lb a3, 10(sp)
-; RV64IPN-NEXT:    lb t0, 5(sp)
-; RV64IPN-NEXT:    lb a5, 9(sp)
-; RV64IPN-NEXT:    lb a6, 4(sp)
-; RV64IPN-NEXT:    lb a7, 8(sp)
-; RV64IPN-NEXT:    addi a4, zero, 1
-; RV64IPN-NEXT:    sw a4, 12(sp)
-; RV64IPN-NEXT:    lb a4, 15(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    or a0, a0, a4
-; RV64IPN-NEXT:    sb a0, 3(sp)
-; RV64IPN-NEXT:    lb a0, 14(sp)
-; RV64IPN-NEXT:    add a1, a3, a2
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 2(sp)
-; RV64IPN-NEXT:    lb a0, 13(sp)
-; RV64IPN-NEXT:    add a1, a5, t0
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 1(sp)
-; RV64IPN-NEXT:    lb a0, 12(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    ori a0, a0, 1
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -1758,52 +640,14 @@
 define signext i32 @oriv2i16(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: oriv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 4(sp)
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    lh a0, 6(sp)
-; RV64IP-NEXT:    lh a1, 10(sp)
-; RV64IP-NEXT:    lh a2, 4(sp)
-; RV64IP-NEXT:    lh a3, 8(sp)
-; RV64IP-NEXT:    addi a4, zero, 1
-; RV64IP-NEXT:    slli a4, a4, 32
-; RV64IP-NEXT:    addi a4, a4, -2
-; RV64IP-NEXT:    sw a4, 12(sp)
-; RV64IP-NEXT:    lh a4, 14(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    or a0, a0, a4
-; RV64IP-NEXT:    sh a0, 2(sp)
-; RV64IP-NEXT:    lh a0, 12(sp)
-; RV64IP-NEXT:    add a1, a3, a2
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sh a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    ori a0, a0, -2
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: oriv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 4(sp)
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    lh a0, 6(sp)
-; RV64IPN-NEXT:    lh a1, 10(sp)
-; RV64IPN-NEXT:    lh a2, 4(sp)
-; RV64IPN-NEXT:    lh a3, 8(sp)
-; RV64IPN-NEXT:    addi a4, zero, 1
-; RV64IPN-NEXT:    slli a4, a4, 32
-; RV64IPN-NEXT:    addi a4, a4, -2
-; RV64IPN-NEXT:    sw a4, 12(sp)
-; RV64IPN-NEXT:    lh a4, 14(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    or a0, a0, a4
-; RV64IPN-NEXT:    sh a0, 2(sp)
-; RV64IPN-NEXT:    lh a0, 12(sp)
-; RV64IPN-NEXT:    add a1, a3, a2
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    ori a0, a0, -2
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -1817,128 +661,14 @@
 define i64 @oriv8i8(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: oriv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -48
-; RV64IP-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
-; RV64IP-NEXT:    sd s1, 32(sp) # 8-byte Folded Spill
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lb a6, 16(sp)
-; RV64IP-NEXT:    lb a7, 8(sp)
-; RV64IP-NEXT:    lb t0, 17(sp)
-; RV64IP-NEXT:    lb t1, 9(sp)
-; RV64IP-NEXT:    lb t2, 18(sp)
-; RV64IP-NEXT:    lb t3, 10(sp)
-; RV64IP-NEXT:    lb t4, 19(sp)
-; RV64IP-NEXT:    lb t5, 11(sp)
-; RV64IP-NEXT:    lb t6, 20(sp)
-; RV64IP-NEXT:    lb a3, 12(sp)
-; RV64IP-NEXT:    lb a4, 21(sp)
-; RV64IP-NEXT:    lb a5, 13(sp)
-; RV64IP-NEXT:    lb a0, 22(sp)
-; RV64IP-NEXT:    lb a1, 14(sp)
-; RV64IP-NEXT:    lb a2, 23(sp)
-; RV64IP-NEXT:    lb s0, 15(sp)
-; RV64IP-NEXT:    addi s1, zero, -3
-; RV64IP-NEXT:    sd s1, 0(sp)
-; RV64IP-NEXT:    lb s1, 7(sp)
-; RV64IP-NEXT:    add a2, s0, a2
-; RV64IP-NEXT:    or a2, a2, s1
-; RV64IP-NEXT:    sb a2, 31(sp)
-; RV64IP-NEXT:    lb a2, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    sb a0, 30(sp)
-; RV64IP-NEXT:    lb a0, 5(sp)
-; RV64IP-NEXT:    add a1, a5, a4
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 29(sp)
-; RV64IP-NEXT:    lb a0, 4(sp)
-; RV64IP-NEXT:    add a1, a3, t6
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 28(sp)
-; RV64IP-NEXT:    lb a0, 3(sp)
-; RV64IP-NEXT:    add a1, t5, t4
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 27(sp)
-; RV64IP-NEXT:    lb a0, 2(sp)
-; RV64IP-NEXT:    add a1, t3, t2
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 26(sp)
-; RV64IP-NEXT:    lb a0, 1(sp)
-; RV64IP-NEXT:    add a1, t1, t0
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 25(sp)
-; RV64IP-NEXT:    lb a0, 0(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sb a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    ld s1, 32(sp) # 8-byte Folded Reload
-; RV64IP-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
-; RV64IP-NEXT:    addi sp, sp, 48
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    ori a0, a0, -3
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: oriv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -48
-; RV64IPN-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
-; RV64IPN-NEXT:    sd s1, 32(sp) # 8-byte Folded Spill
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lb a6, 16(sp)
-; RV64IPN-NEXT:    lb a7, 8(sp)
-; RV64IPN-NEXT:    lb t0, 17(sp)
-; RV64IPN-NEXT:    lb t1, 9(sp)
-; RV64IPN-NEXT:    lb t2, 18(sp)
-; RV64IPN-NEXT:    lb t3, 10(sp)
-; RV64IPN-NEXT:    lb t4, 19(sp)
-; RV64IPN-NEXT:    lb t5, 11(sp)
-; RV64IPN-NEXT:    lb t6, 20(sp)
-; RV64IPN-NEXT:    lb a3, 12(sp)
-; RV64IPN-NEXT:    lb a4, 21(sp)
-; RV64IPN-NEXT:    lb a5, 13(sp)
-; RV64IPN-NEXT:    lb a0, 22(sp)
-; RV64IPN-NEXT:    lb a1, 14(sp)
-; RV64IPN-NEXT:    lb a2, 23(sp)
-; RV64IPN-NEXT:    lb s0, 15(sp)
-; RV64IPN-NEXT:    addi s1, zero, -3
-; RV64IPN-NEXT:    sd s1, 0(sp)
-; RV64IPN-NEXT:    lb s1, 7(sp)
-; RV64IPN-NEXT:    add a2, s0, a2
-; RV64IPN-NEXT:    or a2, a2, s1
-; RV64IPN-NEXT:    sb a2, 31(sp)
-; RV64IPN-NEXT:    lb a2, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    sb a0, 30(sp)
-; RV64IPN-NEXT:    lb a0, 5(sp)
-; RV64IPN-NEXT:    add a1, a5, a4
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 29(sp)
-; RV64IPN-NEXT:    lb a0, 4(sp)
-; RV64IPN-NEXT:    add a1, a3, t6
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 28(sp)
-; RV64IPN-NEXT:    lb a0, 3(sp)
-; RV64IPN-NEXT:    add a1, t5, t4
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 27(sp)
-; RV64IPN-NEXT:    lb a0, 2(sp)
-; RV64IPN-NEXT:    add a1, t3, t2
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 26(sp)
-; RV64IPN-NEXT:    lb a0, 1(sp)
-; RV64IPN-NEXT:    add a1, t1, t0
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 25(sp)
-; RV64IPN-NEXT:    lb a0, 0(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    ld s1, 32(sp) # 8-byte Folded Reload
-; RV64IPN-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
-; RV64IPN-NEXT:    addi sp, sp, 48
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    ori a0, a0, -3
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -1952,72 +682,14 @@
 define i64 @orvi4i16(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: orvi4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lh a6, 16(sp)
-; RV64IP-NEXT:    lh a7, 8(sp)
-; RV64IP-NEXT:    lh t0, 18(sp)
-; RV64IP-NEXT:    lh a3, 10(sp)
-; RV64IP-NEXT:    lh a4, 20(sp)
-; RV64IP-NEXT:    lh a5, 12(sp)
-; RV64IP-NEXT:    lh a0, 22(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    addi a2, zero, -4
-; RV64IP-NEXT:    sd a2, 0(sp)
-; RV64IP-NEXT:    lh a2, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    sh a0, 30(sp)
-; RV64IP-NEXT:    lh a0, 4(sp)
-; RV64IP-NEXT:    add a1, a5, a4
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sh a0, 28(sp)
-; RV64IP-NEXT:    lh a0, 2(sp)
-; RV64IP-NEXT:    add a1, a3, t0
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sh a0, 26(sp)
-; RV64IP-NEXT:    lh a0, 0(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    or a0, a1, a0
-; RV64IP-NEXT:    sh a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    ori a0, a0, -4
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: orvi4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lh a6, 16(sp)
-; RV64IPN-NEXT:    lh a7, 8(sp)
-; RV64IPN-NEXT:    lh t0, 18(sp)
-; RV64IPN-NEXT:    lh a3, 10(sp)
-; RV64IPN-NEXT:    lh a4, 20(sp)
-; RV64IPN-NEXT:    lh a5, 12(sp)
-; RV64IPN-NEXT:    lh a0, 22(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    addi a2, zero, -4
-; RV64IPN-NEXT:    sd a2, 0(sp)
-; RV64IPN-NEXT:    lh a2, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    sh a0, 30(sp)
-; RV64IPN-NEXT:    lh a0, 4(sp)
-; RV64IPN-NEXT:    add a1, a5, a4
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 28(sp)
-; RV64IPN-NEXT:    lh a0, 2(sp)
-; RV64IPN-NEXT:    add a1, a3, t0
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 26(sp)
-; RV64IPN-NEXT:    lh a0, 0(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    or a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    ori a0, a0, -4
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -2031,48 +703,14 @@
 define i64 @oriv2i32(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: oriv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 16(sp)
-; RV64IP-NEXT:    lw a1, 8(sp)
-; RV64IP-NEXT:    lw a2, 20(sp)
-; RV64IP-NEXT:    lw a3, 12(sp)
-; RV64IP-NEXT:    addi a4, zero, -5
-; RV64IP-NEXT:    sd a4, 0(sp)
-; RV64IP-NEXT:    lw a4, 4(sp)
-; RV64IP-NEXT:    add a2, a3, a2
-; RV64IP-NEXT:    or a2, a2, a4
-; RV64IP-NEXT:    sw a2, 28(sp)
-; RV64IP-NEXT:    lw a2, 0(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    or a0, a0, a2
-; RV64IP-NEXT:    sw a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add32 a0, a0, a1
+; RV64IP-NEXT:    ori a0, a0, -5
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: oriv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 16(sp)
-; RV64IPN-NEXT:    lw a1, 8(sp)
-; RV64IPN-NEXT:    lw a2, 20(sp)
-; RV64IPN-NEXT:    lw a3, 12(sp)
-; RV64IPN-NEXT:    addi a4, zero, -5
-; RV64IPN-NEXT:    sd a4, 0(sp)
-; RV64IPN-NEXT:    lw a4, 4(sp)
-; RV64IPN-NEXT:    add a2, a3, a2
-; RV64IPN-NEXT:    or a2, a2, a4
-; RV64IPN-NEXT:    sw a2, 28(sp)
-; RV64IPN-NEXT:    lw a2, 0(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    or a0, a0, a2
-; RV64IPN-NEXT:    sw a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add32 a0, a0, a1
+; RV64IPN-NEXT:    ori a0, a0, -5
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <2 x i32>
   %tmp2 = bitcast i64 %b to <2 x i32>
@@ -2086,74 +724,16 @@
 define signext i32 @xoriv4i8(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: xoriv4i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 4(sp)
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    lb a0, 7(sp)
-; RV64IP-NEXT:    lb a1, 11(sp)
-; RV64IP-NEXT:    lb a2, 6(sp)
-; RV64IP-NEXT:    lb a3, 10(sp)
-; RV64IP-NEXT:    lb t0, 5(sp)
-; RV64IP-NEXT:    lb a5, 9(sp)
-; RV64IP-NEXT:    lb a6, 4(sp)
-; RV64IP-NEXT:    lb a7, 8(sp)
-; RV64IP-NEXT:    addi a4, zero, -1
-; RV64IP-NEXT:    srli a4, a4, 32
-; RV64IP-NEXT:    sw a4, 12(sp)
-; RV64IP-NEXT:    lb a4, 15(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    xor a0, a0, a4
-; RV64IP-NEXT:    sb a0, 3(sp)
-; RV64IP-NEXT:    lb a0, 14(sp)
-; RV64IP-NEXT:    add a1, a3, a2
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 2(sp)
-; RV64IP-NEXT:    lb a0, 13(sp)
-; RV64IP-NEXT:    add a1, a5, t0
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 1(sp)
-; RV64IP-NEXT:    lb a0, 12(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    not a0, a0
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xoriv4i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 4(sp)
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    lb a0, 7(sp)
-; RV64IPN-NEXT:    lb a1, 11(sp)
-; RV64IPN-NEXT:    lb a2, 6(sp)
-; RV64IPN-NEXT:    lb a3, 10(sp)
-; RV64IPN-NEXT:    lb t0, 5(sp)
-; RV64IPN-NEXT:    lb a5, 9(sp)
-; RV64IPN-NEXT:    lb a6, 4(sp)
-; RV64IPN-NEXT:    lb a7, 8(sp)
-; RV64IPN-NEXT:    addi a4, zero, -1
-; RV64IPN-NEXT:    srli a4, a4, 32
-; RV64IPN-NEXT:    sw a4, 12(sp)
-; RV64IPN-NEXT:    lb a4, 15(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    xor a0, a0, a4
-; RV64IPN-NEXT:    sb a0, 3(sp)
-; RV64IPN-NEXT:    lb a0, 14(sp)
-; RV64IPN-NEXT:    add a1, a3, a2
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 2(sp)
-; RV64IPN-NEXT:    lb a0, 13(sp)
-; RV64IPN-NEXT:    add a1, a5, t0
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 1(sp)
-; RV64IPN-NEXT:    lb a0, 12(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    not a0, a0
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <4 x i8>
   %tmp2 = bitcast i32 %b to <4 x i8>
@@ -2167,52 +747,16 @@
 define signext i32 @xoriv2i16(i32 signext %a, i32 signext %b) nounwind {
 ; RV64IP-LABEL: xoriv2i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -16
-; RV64IP-NEXT:    sw a1, 4(sp)
-; RV64IP-NEXT:    sw a0, 8(sp)
-; RV64IP-NEXT:    lh a0, 6(sp)
-; RV64IP-NEXT:    lh a1, 10(sp)
-; RV64IP-NEXT:    lh a2, 4(sp)
-; RV64IP-NEXT:    lh a3, 8(sp)
-; RV64IP-NEXT:    addi a4, zero, 1
-; RV64IP-NEXT:    slli a4, a4, 32
-; RV64IP-NEXT:    addi a4, a4, -2
-; RV64IP-NEXT:    sw a4, 12(sp)
-; RV64IP-NEXT:    lh a4, 14(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    xor a0, a0, a4
-; RV64IP-NEXT:    sh a0, 2(sp)
-; RV64IP-NEXT:    lh a0, 12(sp)
-; RV64IP-NEXT:    add a1, a3, a2
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sh a0, 0(sp)
-; RV64IP-NEXT:    lw a0, 0(sp)
-; RV64IP-NEXT:    addi sp, sp, 16
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    xori a0, a0, -2
+; RV64IP-NEXT:    sext.w a0, a0
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xoriv2i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -16
-; RV64IPN-NEXT:    sw a1, 4(sp)
-; RV64IPN-NEXT:    sw a0, 8(sp)
-; RV64IPN-NEXT:    lh a0, 6(sp)
-; RV64IPN-NEXT:    lh a1, 10(sp)
-; RV64IPN-NEXT:    lh a2, 4(sp)
-; RV64IPN-NEXT:    lh a3, 8(sp)
-; RV64IPN-NEXT:    addi a4, zero, 1
-; RV64IPN-NEXT:    slli a4, a4, 32
-; RV64IPN-NEXT:    addi a4, a4, -2
-; RV64IPN-NEXT:    sw a4, 12(sp)
-; RV64IPN-NEXT:    lh a4, 14(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    xor a0, a0, a4
-; RV64IPN-NEXT:    sh a0, 2(sp)
-; RV64IPN-NEXT:    lh a0, 12(sp)
-; RV64IPN-NEXT:    add a1, a3, a2
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 0(sp)
-; RV64IPN-NEXT:    lw a0, 0(sp)
-; RV64IPN-NEXT:    addi sp, sp, 16
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    xori a0, a0, -2
+; RV64IPN-NEXT:    sext.w a0, a0
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i32 %a to <2 x i16>
   %tmp2 = bitcast i32 %b to <2 x i16>
@@ -2226,128 +770,14 @@
 define i64 @xoriv8i8(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: xoriv8i8:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -48
-; RV64IP-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
-; RV64IP-NEXT:    sd s1, 32(sp) # 8-byte Folded Spill
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lb a6, 16(sp)
-; RV64IP-NEXT:    lb a7, 8(sp)
-; RV64IP-NEXT:    lb t0, 17(sp)
-; RV64IP-NEXT:    lb t1, 9(sp)
-; RV64IP-NEXT:    lb t2, 18(sp)
-; RV64IP-NEXT:    lb t3, 10(sp)
-; RV64IP-NEXT:    lb t4, 19(sp)
-; RV64IP-NEXT:    lb t5, 11(sp)
-; RV64IP-NEXT:    lb t6, 20(sp)
-; RV64IP-NEXT:    lb a3, 12(sp)
-; RV64IP-NEXT:    lb a4, 21(sp)
-; RV64IP-NEXT:    lb a5, 13(sp)
-; RV64IP-NEXT:    lb a0, 22(sp)
-; RV64IP-NEXT:    lb a1, 14(sp)
-; RV64IP-NEXT:    lb a2, 23(sp)
-; RV64IP-NEXT:    lb s0, 15(sp)
-; RV64IP-NEXT:    addi s1, zero, -3
-; RV64IP-NEXT:    sd s1, 0(sp)
-; RV64IP-NEXT:    lb s1, 7(sp)
-; RV64IP-NEXT:    add a2, s0, a2
-; RV64IP-NEXT:    xor a2, a2, s1
-; RV64IP-NEXT:    sb a2, 31(sp)
-; RV64IP-NEXT:    lb a2, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    xor a0, a0, a2
-; RV64IP-NEXT:    sb a0, 30(sp)
-; RV64IP-NEXT:    lb a0, 5(sp)
-; RV64IP-NEXT:    add a1, a5, a4
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 29(sp)
-; RV64IP-NEXT:    lb a0, 4(sp)
-; RV64IP-NEXT:    add a1, a3, t6
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 28(sp)
-; RV64IP-NEXT:    lb a0, 3(sp)
-; RV64IP-NEXT:    add a1, t5, t4
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 27(sp)
-; RV64IP-NEXT:    lb a0, 2(sp)
-; RV64IP-NEXT:    add a1, t3, t2
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 26(sp)
-; RV64IP-NEXT:    lb a0, 1(sp)
-; RV64IP-NEXT:    add a1, t1, t0
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 25(sp)
-; RV64IP-NEXT:    lb a0, 0(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sb a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    ld s1, 32(sp) # 8-byte Folded Reload
-; RV64IP-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
-; RV64IP-NEXT:    addi sp, sp, 48
+; RV64IP-NEXT:    add8 a0, a0, a1
+; RV64IP-NEXT:    xori a0, a0, -3
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xoriv8i8:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -48
-; RV64IPN-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
-; RV64IPN-NEXT:    sd s1, 32(sp) # 8-byte Folded Spill
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lb a6, 16(sp)
-; RV64IPN-NEXT:    lb a7, 8(sp)
-; RV64IPN-NEXT:    lb t0, 17(sp)
-; RV64IPN-NEXT:    lb t1, 9(sp)
-; RV64IPN-NEXT:    lb t2, 18(sp)
-; RV64IPN-NEXT:    lb t3, 10(sp)
-; RV64IPN-NEXT:    lb t4, 19(sp)
-; RV64IPN-NEXT:    lb t5, 11(sp)
-; RV64IPN-NEXT:    lb t6, 20(sp)
-; RV64IPN-NEXT:    lb a3, 12(sp)
-; RV64IPN-NEXT:    lb a4, 21(sp)
-; RV64IPN-NEXT:    lb a5, 13(sp)
-; RV64IPN-NEXT:    lb a0, 22(sp)
-; RV64IPN-NEXT:    lb a1, 14(sp)
-; RV64IPN-NEXT:    lb a2, 23(sp)
-; RV64IPN-NEXT:    lb s0, 15(sp)
-; RV64IPN-NEXT:    addi s1, zero, -3
-; RV64IPN-NEXT:    sd s1, 0(sp)
-; RV64IPN-NEXT:    lb s1, 7(sp)
-; RV64IPN-NEXT:    add a2, s0, a2
-; RV64IPN-NEXT:    xor a2, a2, s1
-; RV64IPN-NEXT:    sb a2, 31(sp)
-; RV64IPN-NEXT:    lb a2, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    xor a0, a0, a2
-; RV64IPN-NEXT:    sb a0, 30(sp)
-; RV64IPN-NEXT:    lb a0, 5(sp)
-; RV64IPN-NEXT:    add a1, a5, a4
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 29(sp)
-; RV64IPN-NEXT:    lb a0, 4(sp)
-; RV64IPN-NEXT:    add a1, a3, t6
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 28(sp)
-; RV64IPN-NEXT:    lb a0, 3(sp)
-; RV64IPN-NEXT:    add a1, t5, t4
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 27(sp)
-; RV64IPN-NEXT:    lb a0, 2(sp)
-; RV64IPN-NEXT:    add a1, t3, t2
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 26(sp)
-; RV64IPN-NEXT:    lb a0, 1(sp)
-; RV64IPN-NEXT:    add a1, t1, t0
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 25(sp)
-; RV64IPN-NEXT:    lb a0, 0(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sb a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    ld s1, 32(sp) # 8-byte Folded Reload
-; RV64IPN-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
-; RV64IPN-NEXT:    addi sp, sp, 48
+; RV64IPN-NEXT:    add8 a0, a0, a1
+; RV64IPN-NEXT:    xori a0, a0, -3
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <8 x i8>
   %tmp2 = bitcast i64 %b to <8 x i8>
@@ -2361,72 +791,14 @@
 define i64 @xorvi4i16(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: xorvi4i16:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lh a6, 16(sp)
-; RV64IP-NEXT:    lh a7, 8(sp)
-; RV64IP-NEXT:    lh t0, 18(sp)
-; RV64IP-NEXT:    lh a3, 10(sp)
-; RV64IP-NEXT:    lh a4, 20(sp)
-; RV64IP-NEXT:    lh a5, 12(sp)
-; RV64IP-NEXT:    lh a0, 22(sp)
-; RV64IP-NEXT:    lh a1, 14(sp)
-; RV64IP-NEXT:    addi a2, zero, -4
-; RV64IP-NEXT:    sd a2, 0(sp)
-; RV64IP-NEXT:    lh a2, 6(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    xor a0, a0, a2
-; RV64IP-NEXT:    sh a0, 30(sp)
-; RV64IP-NEXT:    lh a0, 4(sp)
-; RV64IP-NEXT:    add a1, a5, a4
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sh a0, 28(sp)
-; RV64IP-NEXT:    lh a0, 2(sp)
-; RV64IP-NEXT:    add a1, a3, t0
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sh a0, 26(sp)
-; RV64IP-NEXT:    lh a0, 0(sp)
-; RV64IP-NEXT:    add a1, a7, a6
-; RV64IP-NEXT:    xor a0, a1, a0
-; RV64IP-NEXT:    sh a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add16 a0, a0, a1
+; RV64IP-NEXT:    xori a0, a0, -4
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xorvi4i16:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lh a6, 16(sp)
-; RV64IPN-NEXT:    lh a7, 8(sp)
-; RV64IPN-NEXT:    lh t0, 18(sp)
-; RV64IPN-NEXT:    lh a3, 10(sp)
-; RV64IPN-NEXT:    lh a4, 20(sp)
-; RV64IPN-NEXT:    lh a5, 12(sp)
-; RV64IPN-NEXT:    lh a0, 22(sp)
-; RV64IPN-NEXT:    lh a1, 14(sp)
-; RV64IPN-NEXT:    addi a2, zero, -4
-; RV64IPN-NEXT:    sd a2, 0(sp)
-; RV64IPN-NEXT:    lh a2, 6(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    xor a0, a0, a2
-; RV64IPN-NEXT:    sh a0, 30(sp)
-; RV64IPN-NEXT:    lh a0, 4(sp)
-; RV64IPN-NEXT:    add a1, a5, a4
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 28(sp)
-; RV64IPN-NEXT:    lh a0, 2(sp)
-; RV64IPN-NEXT:    add a1, a3, t0
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 26(sp)
-; RV64IPN-NEXT:    lh a0, 0(sp)
-; RV64IPN-NEXT:    add a1, a7, a6
-; RV64IPN-NEXT:    xor a0, a1, a0
-; RV64IPN-NEXT:    sh a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add16 a0, a0, a1
+; RV64IPN-NEXT:    xori a0, a0, -4
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <4 x i16>
   %tmp2 = bitcast i64 %b to <4 x i16>
@@ -2440,48 +812,14 @@
 define i64 @xoriv2i32(i64 %a, i64 %b) nounwind {
 ; RV64IP-LABEL: xoriv2i32:
 ; RV64IP:       # %bb.0:
-; RV64IP-NEXT:    addi sp, sp, -32
-; RV64IP-NEXT:    sd a1, 16(sp)
-; RV64IP-NEXT:    sd a0, 8(sp)
-; RV64IP-NEXT:    lw a0, 16(sp)
-; RV64IP-NEXT:    lw a1, 8(sp)
-; RV64IP-NEXT:    lw a2, 20(sp)
-; RV64IP-NEXT:    lw a3, 12(sp)
-; RV64IP-NEXT:    addi a4, zero, -5
-; RV64IP-NEXT:    sd a4, 0(sp)
-; RV64IP-NEXT:    lw a4, 4(sp)
-; RV64IP-NEXT:    add a2, a3, a2
-; RV64IP-NEXT:    xor a2, a2, a4
-; RV64IP-NEXT:    sw a2, 28(sp)
-; RV64IP-NEXT:    lw a2, 0(sp)
-; RV64IP-NEXT:    add a0, a1, a0
-; RV64IP-NEXT:    xor a0, a0, a2
-; RV64IP-NEXT:    sw a0, 24(sp)
-; RV64IP-NEXT:    ld a0, 24(sp)
-; RV64IP-NEXT:    addi sp, sp, 32
+; RV64IP-NEXT:    add32 a0, a0, a1
+; RV64IP-NEXT:    xori a0, a0, -5
 ; RV64IP-NEXT:    ret
 ;
 ; RV64IPN-LABEL: xoriv2i32:
 ; RV64IPN:       # %bb.0:
-; RV64IPN-NEXT:    addi sp, sp, -32
-; RV64IPN-NEXT:    sd a1, 16(sp)
-; RV64IPN-NEXT:    sd a0, 8(sp)
-; RV64IPN-NEXT:    lw a0, 16(sp)
-; RV64IPN-NEXT:    lw a1, 8(sp)
-; RV64IPN-NEXT:    lw a2, 20(sp)
-; RV64IPN-NEXT:    lw a3, 12(sp)
-; RV64IPN-NEXT:    addi a4, zero, -5
-; RV64IPN-NEXT:    sd a4, 0(sp)
-; RV64IPN-NEXT:    lw a4, 4(sp)
-; RV64IPN-NEXT:    add a2, a3, a2
-; RV64IPN-NEXT:    xor a2, a2, a4
-; RV64IPN-NEXT:    sw a2, 28(sp)
-; RV64IPN-NEXT:    lw a2, 0(sp)
-; RV64IPN-NEXT:    add a0, a1, a0
-; RV64IPN-NEXT:    xor a0, a0, a2
-; RV64IPN-NEXT:    sw a0, 24(sp)
-; RV64IPN-NEXT:    ld a0, 24(sp)
-; RV64IPN-NEXT:    addi sp, sp, 32
+; RV64IPN-NEXT:    add32 a0, a0, a1
+; RV64IPN-NEXT:    xori a0, a0, -5
 ; RV64IPN-NEXT:    ret
   %tmp1 = bitcast i64 %a to <2 x i32>
   %tmp2 = bitcast i64 %b to <2 x i32>