Index: llvm/test/CodeGen/RISCV/rv32zbs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -709,3 +709,141 @@
   %xor = xor i32 %a, 2147483648
   ret i32 %xor
 }
+
+define i32 @xor_i32_4098(i32 %a) nounwind {
+; RV32I-LABEL: xor_i32_4098:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: xor_i32_4098:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 2
+; RV32IB-NEXT:    xor a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: xor_i32_4098:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 1
+; RV32IBS-NEXT:    addi a1, a1, 2
+; RV32IBS-NEXT:    xor a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %xor = xor i32 %a, 4098
+  ret i32 %xor
+}
+
+define i32 @xor_i32_4099(i32 %a) nounwind {
+; RV32I-LABEL: xor_i32_4099:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 3
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: xor_i32_4099:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 3
+; RV32IB-NEXT:    xor a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: xor_i32_4099:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 1
+; RV32IBS-NEXT:    addi a1, a1, 3
+; RV32IBS-NEXT:    xor a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %xor = xor i32 %a, 4099
+  ret i32 %xor
+}
+
+define i32 @xor_i32_96(i32 %a) nounwind {
+; RV32I-LABEL: xor_i32_96:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xori a0, a0, 96
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: xor_i32_96:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    xori a0, a0, 96
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: xor_i32_96:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    xori a0, a0, 96
+; RV32IBS-NEXT:    ret
+  %xor = xor i32 %a, 96
+  ret i32 %xor
+}
+
+define i32 @or_i32_4098(i32 %a) nounwind {
+; RV32I-LABEL: or_i32_4098:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: or_i32_4098:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 2
+; RV32IB-NEXT:    or a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: or_i32_4098:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 1
+; RV32IBS-NEXT:    addi a1, a1, 2
+; RV32IBS-NEXT:    or a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %or = or i32 %a, 4098
+  ret i32 %or
+}
+
+define i32 @or_i32_4099(i32 %a) nounwind {
+; RV32I-LABEL: or_i32_4099:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 3
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: or_i32_4099:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 3
+; RV32IB-NEXT:    or a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: or_i32_4099:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 1
+; RV32IBS-NEXT:    addi a1, a1, 3
+; RV32IBS-NEXT:    or a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %or = or i32 %a, 4099
+  ret i32 %or
+}
+
+define i32 @or_i32_96(i32 %a) nounwind {
+; RV32I-LABEL: or_i32_96:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ori a0, a0, 96
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: or_i32_96:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    ori a0, a0, 96
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: or_i32_96:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    ori a0, a0, 96
+; RV32IBS-NEXT:    ret
+  %or = or i32 %a, 96
+  ret i32 %or
+}
Index: llvm/test/CodeGen/RISCV/rv64zbs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -1209,3 +1209,147 @@
   %xor = xor i64 %a, 9223372036854775808
   ret i64 %xor
 }
+
+define i64 @xor_i64_large(i64 %a) nounwind {
+; RV64I-LABEL: xor_i64_large:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: xor_i64_large:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 1
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    addi a1, a1, 1
+; RV64IB-NEXT:    xor a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: xor_i64_large:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    addi a1, zero, 1
+; RV64IBS-NEXT:    slli a1, a1, 32
+; RV64IBS-NEXT:    addi a1, a1, 1
+; RV64IBS-NEXT:    xor a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %xor = xor i64 %a, 4294967297
+  ret i64 %xor
+}
+
+define i64 @xor_i64_4099(i64 %a) nounwind {
+; RV64I-LABEL: xor_i64_4099:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 3
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: xor_i64_4099:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1
+; RV64IB-NEXT:    addiw a1, a1, 3
+; RV64IB-NEXT:    xor a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: xor_i64_4099:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 1
+; RV64IBS-NEXT:    addiw a1, a1, 3
+; RV64IBS-NEXT:    xor a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %xor = xor i64 %a, 4099
+  ret i64 %xor
+}
+
+define i64 @xor_i64_96(i64 %a) nounwind {
+; RV64I-LABEL: xor_i64_96:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xori a0, a0, 96
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: xor_i64_96:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    xori a0, a0, 96
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: xor_i64_96:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    xori a0, a0, 96
+; RV64IBS-NEXT:    ret
+  %xor = xor i64 %a, 96
+  ret i64 %xor
+}
+
+define i64 @or_i64_large(i64 %a) nounwind {
+; RV64I-LABEL: or_i64_large:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: or_i64_large:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 1
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    addi a1, a1, 1
+; RV64IB-NEXT:    or a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: or_i64_large:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    addi a1, zero, 1
+; RV64IBS-NEXT:    slli a1, a1, 32
+; RV64IBS-NEXT:    addi a1, a1, 1
+; RV64IBS-NEXT:    or a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %or = or i64 %a, 4294967297
+  ret i64 %or
+}
+
+define i64 @or_i64_4099(i64 %a) nounwind {
+; RV64I-LABEL: or_i64_4099:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 3
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: or_i64_4099:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1
+; RV64IB-NEXT:    addiw a1, a1, 3
+; RV64IB-NEXT:    or a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: or_i64_4099:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 1
+; RV64IBS-NEXT:    addiw a1, a1, 3
+; RV64IBS-NEXT:    or a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %or = or i64 %a, 4099
+  ret i64 %or
+}
+
+define i64 @or_i64_96(i64 %a) nounwind {
+; RV64I-LABEL: or_i64_96:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    ori a0, a0, 96
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: or_i64_96:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    ori a0, a0, 96
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: or_i64_96:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    ori a0, a0, 96
+; RV64IBS-NEXT:    ret
+  %or = or i64 %a, 96
+  ret i64 %or
+}