Index: llvm/lib/CodeGen/VirtRegMap.cpp =================================================================== --- llvm/lib/CodeGen/VirtRegMap.cpp +++ llvm/lib/CodeGen/VirtRegMap.cpp @@ -240,8 +240,10 @@ AU.addPreserved(); AU.addRequired(); - if (!ClearVirtRegs) + if (!ClearVirtRegs) { AU.addPreserved(); + AU.addPreserved(); + } MachineFunctionPass::getAnalysisUsage(AU); } Index: llvm/test/CodeGen/AMDGPU/llc-pipeline.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/llc-pipeline.ll +++ llvm/test/CodeGen/AMDGPU/llc-pipeline.ll @@ -366,7 +366,6 @@ ; GCN-O1-NEXT: Greedy Register Allocator ; GCN-O1-NEXT: Virtual Register Rewriter ; GCN-O1-NEXT: SI lower SGPR spill instructions -; GCN-O1-NEXT: Virtual Register Map ; GCN-O1-NEXT: Live Register Matrix ; GCN-O1-NEXT: Machine Optimization Remark Emitter ; GCN-O1-NEXT: Greedy Register Allocator @@ -655,7 +654,6 @@ ; GCN-O1-OPTS-NEXT: Greedy Register Allocator ; GCN-O1-OPTS-NEXT: Virtual Register Rewriter ; GCN-O1-OPTS-NEXT: SI lower SGPR spill instructions -; GCN-O1-OPTS-NEXT: Virtual Register Map ; GCN-O1-OPTS-NEXT: Live Register Matrix ; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter ; GCN-O1-OPTS-NEXT: Greedy Register Allocator @@ -944,7 +942,6 @@ ; GCN-O2-NEXT: Greedy Register Allocator ; GCN-O2-NEXT: Virtual Register Rewriter ; GCN-O2-NEXT: SI lower SGPR spill instructions -; GCN-O2-NEXT: Virtual Register Map ; GCN-O2-NEXT: Live Register Matrix ; GCN-O2-NEXT: Machine Optimization Remark Emitter ; GCN-O2-NEXT: Greedy Register Allocator @@ -1246,7 +1243,6 @@ ; GCN-O3-NEXT: Greedy Register Allocator ; GCN-O3-NEXT: Virtual Register Rewriter ; GCN-O3-NEXT: SI lower SGPR spill instructions -; GCN-O3-NEXT: Virtual Register Map ; GCN-O3-NEXT: Live Register Matrix ; GCN-O3-NEXT: Machine Optimization Remark Emitter ; GCN-O3-NEXT: Greedy Register Allocator