diff --git a/clang/test/OpenMP/cancel_codegen.cpp b/clang/test/OpenMP/cancel_codegen.cpp --- a/clang/test/OpenMP/cancel_codegen.cpp +++ b/clang/test/OpenMP/cancel_codegen.cpp @@ -7,9 +7,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.1 %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-enable-irbuilder -std=c++11 -include-pch %t.1 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.2 %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -std=c++11 -include-pch %t.2 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -std=c++11 -include-pch %t.2 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.3 %s @@ -19,9 +19,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.4 %s // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -std=c++11 -include-pch %t.4 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t.5 %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t.5 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t.5 -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2562,142 +2562,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK5-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK5-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7:%.*]] -// CHECK5: for.cond7: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK5-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK5: for.body9: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK5-NEXT: br label [[FOR_INC11:%.*]] -// CHECK5: for.inc11: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK5-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end13: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: ret i32 [[TMP15]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK6-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK6-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7:%.*]] -// CHECK6: for.cond7: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK6-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK6: for.body9: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK6-NEXT: br label [[FOR_INC11:%.*]] -// CHECK6: for.inc11: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK6-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end13: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: ret i32 [[TMP15]] -// -// // CHECK7-LABEL: define {{[^@]+}}@main // CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: @@ -5181,139 +5045,4 @@ // CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK11-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK11-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK11-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK11-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK11-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK11-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK11-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK11-NEXT: br label [[FOR_COND7:%.*]] -// CHECK11: for.cond7: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK11: for.body9: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK11-NEXT: br label [[FOR_INC11:%.*]] -// CHECK11: for.inc11: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK11-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK11-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK11: for.end13: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: ret i32 [[TMP15]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[R:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK12-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK12-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8*, i8** [[TMP4]], i64 0 -// CHECK12-NEXT: [[TMP5:%.*]] = load i8*, i8** [[ARRAYIDX2]], align 8 -// CHECK12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, i8* [[TMP5]], i64 0 -// CHECK12-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX3]], align 1 -// CHECK12-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[TMP3]] -// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD]] to i8 -// CHECK12-NEXT: store i8 [[CONV5]], i8* [[ARRAYIDX3]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[R]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK12-NEXT: br label [[FOR_COND7:%.*]] -// CHECK12: for.cond7: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END13:%.*]] -// CHECK12: for.body9: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[R]], align 4 -// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[R]], align 4 -// CHECK12-NEXT: br label [[FOR_INC11:%.*]] -// CHECK12: for.inc11: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK12-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC12]], i32* [[I6]], align 4 -// CHECK12-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK12: for.end13: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: ret i32 [[TMP15]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/cancellation_point_codegen.cpp b/clang/test/OpenMP/cancellation_point_codegen.cpp --- a/clang/test/OpenMP/cancellation_point_codegen.cpp +++ b/clang/test/OpenMP/cancellation_point_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin13.4.0 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-apple-darwin13.4.0 -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1335,107 +1335,4 @@ // CHECK2: cancel.cont: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK3-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK3-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: ret i32 [[TMP9]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK4-NEXT: [[TMP1:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP1]], i64 0 -// CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 0 -// CHECK4-NEXT: store i8 [[CONV]], i8* [[ARRAYIDX1]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: ret i32 [[TMP9]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/debug-info-complex-byval.cpp b/clang/test/OpenMP/debug-info-complex-byval.cpp --- a/clang/test/OpenMP/debug-info-complex-byval.cpp +++ b/clang/test/OpenMP/debug-info-complex-byval.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -fopenmp -x c++ %s -verify -debug-info-kind=limited -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -triple x86_64-unknown-unknown -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics void a() { @@ -61,11 +61,4 @@ // CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG37]] // CHECK1-NEXT: ret void, !dbg [[DBG37]] // -// -// CHECK2-LABEL: define {{[^@]+}}@_Z1av -// CHECK2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[B:%.*]] = alloca { float, float }, align 4 -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata { float, float }* [[B]], metadata [[META10:![0-9]+]], metadata !DIExpression()), !dbg [[DBG12:![0-9]+]] -// CHECK2-NEXT: ret void, !dbg [[DBG13:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/debug-info-openmp-array.cpp b/clang/test/OpenMP/debug-info-openmp-array.cpp --- a/clang/test/OpenMP/debug-info-openmp-array.cpp +++ b/clang/test/OpenMP/debug-info-openmp-array.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -fopenmp-simd -x c++ %s -verify -debug-info-kind=limited -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics void f(int m) { @@ -175,46 +175,4 @@ // CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP3]], i32* [[TMP4]], i32* [[TMP5]], i64 [[TMP1]], i32* [[TMP6]]) #[[ATTR4:[0-9]+]], !dbg [[DBG71]] // CHECK1-NEXT: ret void, !dbg [[DBG71]] // -// -// CHECK2-LABEL: define {{[^@]+}}@_Z1fi -// CHECK2-SAME: (i32 [[M:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[M_ADDR]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG12:![0-9]+]] -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG14:![0-9]+]] -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[M_ADDR]], align 4, !dbg [[DBG15:![0-9]+]] -// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG16:![0-9]+]] -// CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG16]] -// CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG16]] -// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG16]] -// CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG16]] -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] -// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24:![0-9]+]] -// CHECK2-NEXT: store i32 0, i32* [[I]], align 4, !dbg [[DBG25:![0-9]+]] -// CHECK2-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK2: for.cond: -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG29:![0-9]+]] -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4, !dbg [[DBG31:![0-9]+]] -// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]], !dbg [[DBG32:![0-9]+]] -// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG33:![0-9]+]] -// CHECK2: for.body: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG34:![0-9]+]] -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64, !dbg [[DBG37:![0-9]+]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]], !dbg [[DBG37]] -// CHECK2-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !dbg [[DBG38:![0-9]+]] -// CHECK2-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG39:![0-9]+]] -// CHECK2: for.inc: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG40:![0-9]+]] -// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1, !dbg [[DBG40]] -// CHECK2-NEXT: store i32 [[INC]], i32* [[I]], align 4, !dbg [[DBG40]] -// CHECK2-NEXT: br label [[FOR_COND]], !dbg [[DBG41:![0-9]+]], !llvm.loop [[LOOP42:![0-9]+]] -// CHECK2: for.end: -// CHECK2-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG45:![0-9]+]] -// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]), !dbg [[DBG45]] -// CHECK2-NEXT: ret void, !dbg [[DBG45]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_codegen.cpp b/clang/test/OpenMP/distribute_codegen.cpp --- a/clang/test/OpenMP/distribute_codegen.cpp +++ b/clang/test/OpenMP/distribute_codegen.cpp @@ -14,19 +14,19 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -39,13 +39,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -6708,1622 +6708,6 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK9-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK9-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK9-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK9-SAME: () #[[ATTR0]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK10-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK10-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK10-SAME: () #[[ATTR0]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK11-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK11-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK11-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK11-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK11-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK11-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK11-SAME: () #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK12-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK12-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK12-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK12-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK12-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK12-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK12-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK12-SAME: () #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK13-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK13-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK13-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK13-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK13-SAME: () #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK14-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK14-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK14-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK14-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK14-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK14-SAME: () #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK15-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK15-SAME: () #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK15-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK15-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK15-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK15-SAME: () #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK15-SAME: () #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK16-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK16-SAME: () #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK16-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK16-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK16-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK16-SAME: () #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK16-SAME: () #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret i32 0 -// -// // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -10455,811 +8839,4 @@ // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK20-NEXT: ret void // -// -// CHECK21-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK21-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK21-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK21-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK21-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK21-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK21-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK21-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK21-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK21-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK21-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK21-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK21-SAME: () #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK22-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK22-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK22-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK22-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK22-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK22-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK22-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK22-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK22-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK22-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK22-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK22-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK22-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK22-SAME: () #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK23-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK23-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK23-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK23-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK23-SAME: () #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK23-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK23-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK23-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK23-SAME: () #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK23-SAME: () #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: ret i32 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK24-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK24-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4 -// CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4 -// CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4 -// CHECK24-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 [[TMP2]] -// CHECK24-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]] -// CHECK24-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK24-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]] -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]] -// CHECK24-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z12test_precondv -// CHECK24-SAME: () #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store i8 0, i8* [[A]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK24-NEXT: store i8 [[TMP0]], i8* [[I]], align 1 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK24-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[I]], align 1 -// CHECK24-NEXT: [[INC:%.*]] = add i8 [[TMP2]], 1 -// CHECK24-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z4fintv -// CHECK24-SAME: () #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v -// CHECK24-SAME: () #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -826,78 +826,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3533,1119 +3461,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -804,78 +804,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3659,1123 +3587,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done6: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done5: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done5: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -21,12 +21,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -7807,114 +7807,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK5-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[N]], i32** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: store double** [[A]], double*** [[TMP1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store double** [[B]], double*** [[TMP2]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK5-NEXT: store double** [[C]], double*** [[TMP3]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK5-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK6-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[N]], i32** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: store double** [[A]], double*** [[TMP1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK6-NEXT: store double** [[B]], double*** [[TMP2]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK6-NEXT: store double** [[C]], double*** [[TMP3]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK6-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK7-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[N]], i32** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: store double** [[A]], double*** [[TMP1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store double** [[B]], double*** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: store double** [[C]], double*** [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK7-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK8-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[N]], i32** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: store double** [[A]], double*** [[TMP1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK8-NEXT: store double** [[B]], double*** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK8-NEXT: store double** [[C]], double*** [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 -// CHECK8-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -25334,1875 +25226,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX2]], align 8 -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK13-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[TMP8]], i64 [[IDXPROM3]] -// CHECK13-NEXT: store double [[ADD]], double* [[ARRAYIDX4]], align 8 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6:%.*]] -// CHECK13: for.cond6: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body8: -// CHECK13-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 [[IDXPROM9]] -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX10]], align 8 -// CHECK13-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP16]], i64 [[IDXPROM11]] -// CHECK13-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK13-NEXT: [[ADD13:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK13-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP19]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store double [[ADD13]], double* [[ARRAYIDX15]], align 8 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20:%.*]] -// CHECK13: for.cond20: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK13: for.body22: -// CHECK13-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK13-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM23]] -// CHECK13-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX24]], align 8 -// CHECK13-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM25]] -// CHECK13-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX26]], align 8 -// CHECK13-NEXT: [[ADD27:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK13-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP30]], i64 [[IDXPROM28]] -// CHECK13-NEXT: store double [[ADD27]], double* [[ARRAYIDX29]], align 8 -// CHECK13-NEXT: br label [[FOR_INC30:%.*]] -// CHECK13: for.inc30: -// CHECK13-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK13-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end32: -// CHECK13-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34:%.*]] -// CHECK13: for.cond34: -// CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK13-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK13: for.body36: -// CHECK13-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK13-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds double, double* [[TMP35]], i64 [[IDXPROM37]] -// CHECK13-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX38]], align 8 -// CHECK13-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK13-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP38]], i64 [[IDXPROM39]] -// CHECK13-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX40]], align 8 -// CHECK13-NEXT: [[ADD41:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK13-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP41]], i64 [[IDXPROM42]] -// CHECK13-NEXT: store double [[ADD41]], double* [[ARRAYIDX43]], align 8 -// CHECK13-NEXT: br label [[FOR_INC44:%.*]] -// CHECK13: for.inc44: -// CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK13-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end46: -// CHECK13-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48:%.*]] -// CHECK13: for.cond48: -// CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK13-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK13: for.body50: -// CHECK13-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK13-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP47]], i64 [[IDXPROM51]] -// CHECK13-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX52]], align 8 -// CHECK13-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK13-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP50]], i64 [[IDXPROM53]] -// CHECK13-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX54]], align 8 -// CHECK13-NEXT: [[ADD55:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK13-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK13-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 [[IDXPROM56]] -// CHECK13-NEXT: store double [[ADD55]], double* [[ARRAYIDX57]], align 8 -// CHECK13-NEXT: br label [[FOR_INC58:%.*]] -// CHECK13: for.inc58: -// CHECK13-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK13-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end60: -// CHECK13-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62:%.*]] -// CHECK13: for.cond62: -// CHECK13-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK13-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK13: for.body64: -// CHECK13-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK13-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP58]], i64 [[IDXPROM65]] -// CHECK13-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX66]], align 8 -// CHECK13-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK13-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds double, double* [[TMP61]], i64 [[IDXPROM67]] -// CHECK13-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX68]], align 8 -// CHECK13-NEXT: [[ADD69:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK13-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK13-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds double, double* [[TMP64]], i64 [[IDXPROM70]] -// CHECK13-NEXT: store double [[ADD69]], double* [[ARRAYIDX71]], align 8 -// CHECK13-NEXT: br label [[FOR_INC72:%.*]] -// CHECK13: for.inc72: -// CHECK13-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK13-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end74: -// CHECK13-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77:%.*]] -// CHECK13: for.cond77: -// CHECK13-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK13-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK13: for.body79: -// CHECK13-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 8 -// CHECK13-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK13-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds double, double* [[TMP70]], i64 [[IDXPROM80]] -// CHECK13-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX81]], align 8 -// CHECK13-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 8 -// CHECK13-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds double, double* [[TMP73]], i64 [[IDXPROM82]] -// CHECK13-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX83]], align 8 -// CHECK13-NEXT: [[ADD84:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK13-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 8 -// CHECK13-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK13-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds double, double* [[TMP76]], i64 [[IDXPROM85]] -// CHECK13-NEXT: store double [[ADD84]], double* [[ARRAYIDX86]], align 8 -// CHECK13-NEXT: br label [[FOR_INC87:%.*]] -// CHECK13: for.inc87: -// CHECK13-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK13-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end89: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: ret i32 [[CALL]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM3]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX4]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6:%.*]] -// CHECK13: for.cond6: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body8: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i64 [[IDXPROM9]] -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX10]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i64 [[IDXPROM11]] -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK13-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 [[ADD13]], i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK13-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20:%.*]] -// CHECK13: for.cond20: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK13: for.body22: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK13-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM23]] -// CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX24]], align 4 -// CHECK13-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM25]] -// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX26]], align 4 -// CHECK13-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK13-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM28]] -// CHECK13-NEXT: store i32 [[ADD27]], i32* [[ARRAYIDX29]], align 4 -// CHECK13-NEXT: br label [[FOR_INC30:%.*]] -// CHECK13: for.inc30: -// CHECK13-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK13-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK13: for.end32: -// CHECK13-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34:%.*]] -// CHECK13: for.cond34: -// CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK13-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK13: for.body36: -// CHECK13-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK13-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i64 [[IDXPROM37]] -// CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX38]], align 4 -// CHECK13-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK13-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i64 [[IDXPROM39]] -// CHECK13-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK13-NEXT: [[ADD41:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK13-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i64 [[IDXPROM42]] -// CHECK13-NEXT: store i32 [[ADD41]], i32* [[ARRAYIDX43]], align 4 -// CHECK13-NEXT: br label [[FOR_INC44:%.*]] -// CHECK13: for.inc44: -// CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK13-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK13-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK13-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK13: for.end46: -// CHECK13-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48:%.*]] -// CHECK13: for.cond48: -// CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK13-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK13: for.body50: -// CHECK13-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK13-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i64 [[IDXPROM51]] -// CHECK13-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK13-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK13-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i64 [[IDXPROM53]] -// CHECK13-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX54]], align 4 -// CHECK13-NEXT: [[ADD55:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK13-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK13-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i64 [[IDXPROM56]] -// CHECK13-NEXT: store i32 [[ADD55]], i32* [[ARRAYIDX57]], align 4 -// CHECK13-NEXT: br label [[FOR_INC58:%.*]] -// CHECK13: for.inc58: -// CHECK13-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK13-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK13-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK13-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK13: for.end60: -// CHECK13-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62:%.*]] -// CHECK13: for.cond62: -// CHECK13-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK13-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK13: for.body64: -// CHECK13-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK13-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i64 [[IDXPROM65]] -// CHECK13-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX66]], align 4 -// CHECK13-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK13-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i64 [[IDXPROM67]] -// CHECK13-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX68]], align 4 -// CHECK13-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK13-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK13-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i64 [[IDXPROM70]] -// CHECK13-NEXT: store i32 [[ADD69]], i32* [[ARRAYIDX71]], align 4 -// CHECK13-NEXT: br label [[FOR_INC72:%.*]] -// CHECK13: for.inc72: -// CHECK13-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK13-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK13-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK13-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK13: for.end74: -// CHECK13-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK13-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77:%.*]] -// CHECK13: for.cond77: -// CHECK13-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK13-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK13: for.body79: -// CHECK13-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK13-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK13-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i64 [[IDXPROM80]] -// CHECK13-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX81]], align 4 -// CHECK13-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK13-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i64 [[IDXPROM82]] -// CHECK13-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX83]], align 4 -// CHECK13-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK13-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK13-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i64 [[IDXPROM85]] -// CHECK13-NEXT: store i32 [[ADD84]], i32* [[ARRAYIDX86]], align 4 -// CHECK13-NEXT: br label [[FOR_INC87:%.*]] -// CHECK13: for.inc87: -// CHECK13-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK13-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK13-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK13-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK13: for.end89: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[B:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX2]], align 8 -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK14-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[TMP8]], i64 [[IDXPROM3]] -// CHECK14-NEXT: store double [[ADD]], double* [[ARRAYIDX4]], align 8 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6:%.*]] -// CHECK14: for.cond6: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body8: -// CHECK14-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 [[IDXPROM9]] -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX10]], align 8 -// CHECK14-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP16]], i64 [[IDXPROM11]] -// CHECK14-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX12]], align 8 -// CHECK14-NEXT: [[ADD13:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK14-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP19]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store double [[ADD13]], double* [[ARRAYIDX15]], align 8 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20:%.*]] -// CHECK14: for.cond20: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK14: for.body22: -// CHECK14-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK14-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds double, double* [[TMP24]], i64 [[IDXPROM23]] -// CHECK14-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX24]], align 8 -// CHECK14-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK14-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds double, double* [[TMP27]], i64 [[IDXPROM25]] -// CHECK14-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX26]], align 8 -// CHECK14-NEXT: [[ADD27:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK14-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK14-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP30]], i64 [[IDXPROM28]] -// CHECK14-NEXT: store double [[ADD27]], double* [[ARRAYIDX29]], align 8 -// CHECK14-NEXT: br label [[FOR_INC30:%.*]] -// CHECK14: for.inc30: -// CHECK14-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK14-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end32: -// CHECK14-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34:%.*]] -// CHECK14: for.cond34: -// CHECK14-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK14-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK14: for.body36: -// CHECK14-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK14-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds double, double* [[TMP35]], i64 [[IDXPROM37]] -// CHECK14-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX38]], align 8 -// CHECK14-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK14-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP38]], i64 [[IDXPROM39]] -// CHECK14-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX40]], align 8 -// CHECK14-NEXT: [[ADD41:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK14-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP41]], i64 [[IDXPROM42]] -// CHECK14-NEXT: store double [[ADD41]], double* [[ARRAYIDX43]], align 8 -// CHECK14-NEXT: br label [[FOR_INC44:%.*]] -// CHECK14: for.inc44: -// CHECK14-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK14-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end46: -// CHECK14-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48:%.*]] -// CHECK14: for.cond48: -// CHECK14-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK14-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK14: for.body50: -// CHECK14-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK14-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP47]], i64 [[IDXPROM51]] -// CHECK14-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX52]], align 8 -// CHECK14-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK14-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP50]], i64 [[IDXPROM53]] -// CHECK14-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX54]], align 8 -// CHECK14-NEXT: [[ADD55:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK14-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK14-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 [[IDXPROM56]] -// CHECK14-NEXT: store double [[ADD55]], double* [[ARRAYIDX57]], align 8 -// CHECK14-NEXT: br label [[FOR_INC58:%.*]] -// CHECK14: for.inc58: -// CHECK14-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK14-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end60: -// CHECK14-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62:%.*]] -// CHECK14: for.cond62: -// CHECK14-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK14-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK14: for.body64: -// CHECK14-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK14-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP58]], i64 [[IDXPROM65]] -// CHECK14-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX66]], align 8 -// CHECK14-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK14-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds double, double* [[TMP61]], i64 [[IDXPROM67]] -// CHECK14-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX68]], align 8 -// CHECK14-NEXT: [[ADD69:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK14-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK14-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds double, double* [[TMP64]], i64 [[IDXPROM70]] -// CHECK14-NEXT: store double [[ADD69]], double* [[ARRAYIDX71]], align 8 -// CHECK14-NEXT: br label [[FOR_INC72:%.*]] -// CHECK14: for.inc72: -// CHECK14-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK14-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end74: -// CHECK14-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77:%.*]] -// CHECK14: for.cond77: -// CHECK14-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK14-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK14: for.body79: -// CHECK14-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 8 -// CHECK14-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK14-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds double, double* [[TMP70]], i64 [[IDXPROM80]] -// CHECK14-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX81]], align 8 -// CHECK14-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 8 -// CHECK14-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK14-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds double, double* [[TMP73]], i64 [[IDXPROM82]] -// CHECK14-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX83]], align 8 -// CHECK14-NEXT: [[ADD84:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK14-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 8 -// CHECK14-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK14-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds double, double* [[TMP76]], i64 [[IDXPROM85]] -// CHECK14-NEXT: store double [[ADD84]], double* [[ARRAYIDX86]], align 8 -// CHECK14-NEXT: br label [[FOR_INC87:%.*]] -// CHECK14: for.inc87: -// CHECK14-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK14-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end89: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: ret i32 [[CALL]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I33:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_75:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I76:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM3]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX4]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6:%.*]] -// CHECK14: for.cond6: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body8: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i64 [[IDXPROM9]] -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX10]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i64 [[IDXPROM11]] -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK14-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 [[ADD13]], i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I5]], align 4 -// CHECK14-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20:%.*]] -// CHECK14: for.cond20: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END32:%.*]] -// CHECK14: for.body22: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK14-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i64 [[IDXPROM23]] -// CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX24]], align 4 -// CHECK14-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK14-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[IDXPROM25]] -// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX26]], align 4 -// CHECK14-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK14-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK14-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i64 [[IDXPROM28]] -// CHECK14-NEXT: store i32 [[ADD27]], i32* [[ARRAYIDX29]], align 4 -// CHECK14-NEXT: br label [[FOR_INC30:%.*]] -// CHECK14: for.inc30: -// CHECK14-NEXT: [[TMP32:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK14-NEXT: store i32 [[INC31]], i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK14: for.end32: -// CHECK14-NEXT: store i32 0, i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34:%.*]] -// CHECK14: for.cond34: -// CHECK14-NEXT: [[TMP33:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP35:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK14-NEXT: br i1 [[CMP35]], label [[FOR_BODY36:%.*]], label [[FOR_END46:%.*]] -// CHECK14: for.body36: -// CHECK14-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP36:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP36]] to i64 -// CHECK14-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i64 [[IDXPROM37]] -// CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX38]], align 4 -// CHECK14-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP39:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM39:%.*]] = sext i32 [[TMP39]] to i64 -// CHECK14-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i64 [[IDXPROM39]] -// CHECK14-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK14-NEXT: [[ADD41:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK14-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP42:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP42]] to i64 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i64 [[IDXPROM42]] -// CHECK14-NEXT: store i32 [[ADD41]], i32* [[ARRAYIDX43]], align 4 -// CHECK14-NEXT: br label [[FOR_INC44:%.*]] -// CHECK14: for.inc44: -// CHECK14-NEXT: [[TMP43:%.*]] = load i32, i32* [[I33]], align 4 -// CHECK14-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK14-NEXT: store i32 [[INC45]], i32* [[I33]], align 4 -// CHECK14-NEXT: br label [[FOR_COND34]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK14: for.end46: -// CHECK14-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48:%.*]] -// CHECK14: for.cond48: -// CHECK14-NEXT: [[TMP45:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK14-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END60:%.*]] -// CHECK14: for.body50: -// CHECK14-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP48:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM51:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK14-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i64 [[IDXPROM51]] -// CHECK14-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK14-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP51:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM53:%.*]] = sext i32 [[TMP51]] to i64 -// CHECK14-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i64 [[IDXPROM53]] -// CHECK14-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX54]], align 4 -// CHECK14-NEXT: [[ADD55:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK14-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP54:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[IDXPROM56:%.*]] = sext i32 [[TMP54]] to i64 -// CHECK14-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i64 [[IDXPROM56]] -// CHECK14-NEXT: store i32 [[ADD55]], i32* [[ARRAYIDX57]], align 4 -// CHECK14-NEXT: br label [[FOR_INC58:%.*]] -// CHECK14: for.inc58: -// CHECK14-NEXT: [[TMP55:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK14-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK14-NEXT: store i32 [[INC59]], i32* [[I47]], align 4 -// CHECK14-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK14: for.end60: -// CHECK14-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62:%.*]] -// CHECK14: for.cond62: -// CHECK14-NEXT: [[TMP56:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK14-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END74:%.*]] -// CHECK14: for.body64: -// CHECK14-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP59:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK14-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i64 [[IDXPROM65]] -// CHECK14-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX66]], align 4 -// CHECK14-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP62:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM67:%.*]] = sext i32 [[TMP62]] to i64 -// CHECK14-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i64 [[IDXPROM67]] -// CHECK14-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX68]], align 4 -// CHECK14-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK14-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP65:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[IDXPROM70:%.*]] = sext i32 [[TMP65]] to i64 -// CHECK14-NEXT: [[ARRAYIDX71:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i64 [[IDXPROM70]] -// CHECK14-NEXT: store i32 [[ADD69]], i32* [[ARRAYIDX71]], align 4 -// CHECK14-NEXT: br label [[FOR_INC72:%.*]] -// CHECK14: for.inc72: -// CHECK14-NEXT: [[TMP66:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK14-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK14-NEXT: store i32 [[INC73]], i32* [[I61]], align 4 -// CHECK14-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK14: for.end74: -// CHECK14-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK14-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_75]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77:%.*]] -// CHECK14: for.cond77: -// CHECK14-NEXT: [[TMP68:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP78:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK14-NEXT: br i1 [[CMP78]], label [[FOR_BODY79:%.*]], label [[FOR_END89:%.*]] -// CHECK14: for.body79: -// CHECK14-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK14-NEXT: [[TMP71:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM80:%.*]] = sext i32 [[TMP71]] to i64 -// CHECK14-NEXT: [[ARRAYIDX81:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i64 [[IDXPROM80]] -// CHECK14-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX81]], align 4 -// CHECK14-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK14-NEXT: [[TMP74:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM82:%.*]] = sext i32 [[TMP74]] to i64 -// CHECK14-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i64 [[IDXPROM82]] -// CHECK14-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX83]], align 4 -// CHECK14-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK14-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP77:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[IDXPROM85:%.*]] = sext i32 [[TMP77]] to i64 -// CHECK14-NEXT: [[ARRAYIDX86:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i64 [[IDXPROM85]] -// CHECK14-NEXT: store i32 [[ADD84]], i32* [[ARRAYIDX86]], align 4 -// CHECK14-NEXT: br label [[FOR_INC87:%.*]] -// CHECK14: for.inc87: -// CHECK14-NEXT: [[TMP78:%.*]] = load i32, i32* [[I76]], align 4 -// CHECK14-NEXT: [[INC88:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK14-NEXT: store i32 [[INC88]], i32* [[I76]], align 4 -// CHECK14-NEXT: br label [[FOR_COND77]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK14: for.end89: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 [[TMP3]] -// CHECK15-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK15-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP8]], i32 [[TMP9]] -// CHECK15-NEXT: store double [[ADD]], double* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4:%.*]] -// CHECK15: for.cond4: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK15: for.body6: -// CHECK15-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP13]], i32 [[TMP14]] -// CHECK15-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX7]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP16]], i32 [[TMP17]] -// CHECK15-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX8]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK15-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP19]], i32 [[TMP20]] -// CHECK15-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 -// CHECK15-NEXT: br label [[FOR_INC11:%.*]] -// CHECK15: for.inc11: -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end13: -// CHECK15-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15:%.*]] -// CHECK15: for.cond15: -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK15-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK15: for.body17: -// CHECK15-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] -// CHECK15-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX18]], align 4 -// CHECK15-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] -// CHECK15-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX19]], align 4 -// CHECK15-NEXT: [[ADD20:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK15-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[TMP30]], i32 [[TMP31]] -// CHECK15-NEXT: store double [[ADD20]], double* [[ARRAYIDX21]], align 4 -// CHECK15-NEXT: br label [[FOR_INC22:%.*]] -// CHECK15: for.inc22: -// CHECK15-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK15-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end24: -// CHECK15-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26:%.*]] -// CHECK15: for.cond26: -// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK15-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK15: for.body28: -// CHECK15-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP35]], i32 [[TMP36]] -// CHECK15-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX29]], align 4 -// CHECK15-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds double, double* [[TMP38]], i32 [[TMP39]] -// CHECK15-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX30]], align 4 -// CHECK15-NEXT: [[ADD31:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK15-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds double, double* [[TMP41]], i32 [[TMP42]] -// CHECK15-NEXT: store double [[ADD31]], double* [[ARRAYIDX32]], align 4 -// CHECK15-NEXT: br label [[FOR_INC33:%.*]] -// CHECK15: for.inc33: -// CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK15-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end35: -// CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37:%.*]] -// CHECK15: for.cond37: -// CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK15-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK15: for.body39: -// CHECK15-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP47]], i32 [[TMP48]] -// CHECK15-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX40]], align 4 -// CHECK15-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds double, double* [[TMP50]], i32 [[TMP51]] -// CHECK15-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX41]], align 4 -// CHECK15-NEXT: [[ADD42:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK15-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP53]], i32 [[TMP54]] -// CHECK15-NEXT: store double [[ADD42]], double* [[ARRAYIDX43]], align 4 -// CHECK15-NEXT: br label [[FOR_INC44:%.*]] -// CHECK15: for.inc44: -// CHECK15-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK15-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end46: -// CHECK15-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48:%.*]] -// CHECK15: for.cond48: -// CHECK15-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK15-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK15: for.body50: -// CHECK15-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds double, double* [[TMP58]], i32 [[TMP59]] -// CHECK15-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX51]], align 4 -// CHECK15-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP61]], i32 [[TMP62]] -// CHECK15-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX52]], align 4 -// CHECK15-NEXT: [[ADD53:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK15-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP64]], i32 [[TMP65]] -// CHECK15-NEXT: store double [[ADD53]], double* [[ARRAYIDX54]], align 4 -// CHECK15-NEXT: br label [[FOR_INC55:%.*]] -// CHECK15: for.inc55: -// CHECK15-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK15-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end57: -// CHECK15-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60:%.*]] -// CHECK15: for.cond60: -// CHECK15-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK15-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK15: for.body62: -// CHECK15-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 4 -// CHECK15-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds double, double* [[TMP70]], i32 [[TMP71]] -// CHECK15-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX63]], align 4 -// CHECK15-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 4 -// CHECK15-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds double, double* [[TMP73]], i32 [[TMP74]] -// CHECK15-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX64]], align 4 -// CHECK15-NEXT: [[ADD65:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK15-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 4 -// CHECK15-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP76]], i32 [[TMP77]] -// CHECK15-NEXT: store double [[ADD65]], double* [[ARRAYIDX66]], align 4 -// CHECK15-NEXT: br label [[FOR_INC67:%.*]] -// CHECK15: for.inc67: -// CHECK15-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK15-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end69: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP3]] -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 [[TMP6]] -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 [[TMP9]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX2]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4:%.*]] -// CHECK15: for.cond4: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK15: for.body6: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 [[TMP14]] -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 [[TMP17]] -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK15-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i32 [[TMP20]] -// CHECK15-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 -// CHECK15-NEXT: br label [[FOR_INC11:%.*]] -// CHECK15: for.inc11: -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end13: -// CHECK15-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15:%.*]] -// CHECK15: for.cond15: -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK15-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK15: for.body17: -// CHECK15-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX18]], align 4 -// CHECK15-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX19]], align 4 -// CHECK15-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK15-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] -// CHECK15-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX21]], align 4 -// CHECK15-NEXT: br label [[FOR_INC22:%.*]] -// CHECK15: for.inc22: -// CHECK15-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK15-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK15-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK15-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end24: -// CHECK15-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26:%.*]] -// CHECK15: for.cond26: -// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK15-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK15: for.body28: -// CHECK15-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i32 [[TMP36]] -// CHECK15-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX29]], align 4 -// CHECK15-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i32 [[TMP39]] -// CHECK15-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX30]], align 4 -// CHECK15-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK15-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i32 [[TMP42]] -// CHECK15-NEXT: store i32 [[ADD31]], i32* [[ARRAYIDX32]], align 4 -// CHECK15-NEXT: br label [[FOR_INC33:%.*]] -// CHECK15: for.inc33: -// CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK15-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK15-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK15-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end35: -// CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37:%.*]] -// CHECK15: for.cond37: -// CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK15-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK15: for.body39: -// CHECK15-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i32 [[TMP48]] -// CHECK15-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK15-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i32 [[TMP51]] -// CHECK15-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX41]], align 4 -// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK15-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i32 [[TMP54]] -// CHECK15-NEXT: store i32 [[ADD42]], i32* [[ARRAYIDX43]], align 4 -// CHECK15-NEXT: br label [[FOR_INC44:%.*]] -// CHECK15: for.inc44: -// CHECK15-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK15-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK15-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK15-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK15: for.end46: -// CHECK15-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48:%.*]] -// CHECK15: for.cond48: -// CHECK15-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK15-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK15: for.body50: -// CHECK15-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i32 [[TMP59]] -// CHECK15-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX51]], align 4 -// CHECK15-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i32 [[TMP62]] -// CHECK15-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK15-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK15-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 [[TMP65]] -// CHECK15-NEXT: store i32 [[ADD53]], i32* [[ARRAYIDX54]], align 4 -// CHECK15-NEXT: br label [[FOR_INC55:%.*]] -// CHECK15: for.inc55: -// CHECK15-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK15-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK15-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK15-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK15: for.end57: -// CHECK15-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK15-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60:%.*]] -// CHECK15: for.cond60: -// CHECK15-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK15-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK15: for.body62: -// CHECK15-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK15-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i32 [[TMP71]] -// CHECK15-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX63]], align 4 -// CHECK15-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK15-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i32 [[TMP74]] -// CHECK15-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX64]], align 4 -// CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK15-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK15-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i32 [[TMP77]] -// CHECK15-NEXT: store i32 [[ADD65]], i32* [[ARRAYIDX66]], align 4 -// CHECK15-NEXT: br label [[FOR_INC67:%.*]] -// CHECK15: for.inc67: -// CHECK15-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK15-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK15-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK15-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK15: for.end69: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 [[TMP3]] -// CHECK16-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[TMP4]], [[TMP7]] -// CHECK16-NEXT: [[TMP8:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP8]], i32 [[TMP9]] -// CHECK16-NEXT: store double [[ADD]], double* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4:%.*]] -// CHECK16: for.cond4: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK16: for.body6: -// CHECK16-NEXT: [[TMP13:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[TMP13]], i32 [[TMP14]] -// CHECK16-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX7]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[TMP16]], i32 [[TMP17]] -// CHECK16-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX8]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = fadd double [[TMP15]], [[TMP18]] -// CHECK16-NEXT: [[TMP19:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, double* [[TMP19]], i32 [[TMP20]] -// CHECK16-NEXT: store double [[ADD9]], double* [[ARRAYIDX10]], align 4 -// CHECK16-NEXT: br label [[FOR_INC11:%.*]] -// CHECK16: for.inc11: -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK16-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end13: -// CHECK16-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15:%.*]] -// CHECK16: for.cond15: -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK16-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK16: for.body17: -// CHECK16-NEXT: [[TMP24:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[TMP24]], i32 [[TMP25]] -// CHECK16-NEXT: [[TMP26:%.*]] = load double, double* [[ARRAYIDX18]], align 4 -// CHECK16-NEXT: [[TMP27:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP27]], i32 [[TMP28]] -// CHECK16-NEXT: [[TMP29:%.*]] = load double, double* [[ARRAYIDX19]], align 4 -// CHECK16-NEXT: [[ADD20:%.*]] = fadd double [[TMP26]], [[TMP29]] -// CHECK16-NEXT: [[TMP30:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[TMP30]], i32 [[TMP31]] -// CHECK16-NEXT: store double [[ADD20]], double* [[ARRAYIDX21]], align 4 -// CHECK16-NEXT: br label [[FOR_INC22:%.*]] -// CHECK16: for.inc22: -// CHECK16-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK16-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end24: -// CHECK16-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26:%.*]] -// CHECK16: for.cond26: -// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK16-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK16: for.body28: -// CHECK16-NEXT: [[TMP35:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds double, double* [[TMP35]], i32 [[TMP36]] -// CHECK16-NEXT: [[TMP37:%.*]] = load double, double* [[ARRAYIDX29]], align 4 -// CHECK16-NEXT: [[TMP38:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds double, double* [[TMP38]], i32 [[TMP39]] -// CHECK16-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX30]], align 4 -// CHECK16-NEXT: [[ADD31:%.*]] = fadd double [[TMP37]], [[TMP40]] -// CHECK16-NEXT: [[TMP41:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds double, double* [[TMP41]], i32 [[TMP42]] -// CHECK16-NEXT: store double [[ADD31]], double* [[ARRAYIDX32]], align 4 -// CHECK16-NEXT: br label [[FOR_INC33:%.*]] -// CHECK16: for.inc33: -// CHECK16-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK16-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end35: -// CHECK16-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37:%.*]] -// CHECK16: for.cond37: -// CHECK16-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK16-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK16: for.body39: -// CHECK16-NEXT: [[TMP47:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds double, double* [[TMP47]], i32 [[TMP48]] -// CHECK16-NEXT: [[TMP49:%.*]] = load double, double* [[ARRAYIDX40]], align 4 -// CHECK16-NEXT: [[TMP50:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds double, double* [[TMP50]], i32 [[TMP51]] -// CHECK16-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX41]], align 4 -// CHECK16-NEXT: [[ADD42:%.*]] = fadd double [[TMP49]], [[TMP52]] -// CHECK16-NEXT: [[TMP53:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds double, double* [[TMP53]], i32 [[TMP54]] -// CHECK16-NEXT: store double [[ADD42]], double* [[ARRAYIDX43]], align 4 -// CHECK16-NEXT: br label [[FOR_INC44:%.*]] -// CHECK16: for.inc44: -// CHECK16-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK16-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end46: -// CHECK16-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48:%.*]] -// CHECK16: for.cond48: -// CHECK16-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK16-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK16: for.body50: -// CHECK16-NEXT: [[TMP58:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds double, double* [[TMP58]], i32 [[TMP59]] -// CHECK16-NEXT: [[TMP60:%.*]] = load double, double* [[ARRAYIDX51]], align 4 -// CHECK16-NEXT: [[TMP61:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds double, double* [[TMP61]], i32 [[TMP62]] -// CHECK16-NEXT: [[TMP63:%.*]] = load double, double* [[ARRAYIDX52]], align 4 -// CHECK16-NEXT: [[ADD53:%.*]] = fadd double [[TMP60]], [[TMP63]] -// CHECK16-NEXT: [[TMP64:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds double, double* [[TMP64]], i32 [[TMP65]] -// CHECK16-NEXT: store double [[ADD53]], double* [[ARRAYIDX54]], align 4 -// CHECK16-NEXT: br label [[FOR_INC55:%.*]] -// CHECK16: for.inc55: -// CHECK16-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK16-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end57: -// CHECK16-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60:%.*]] -// CHECK16: for.cond60: -// CHECK16-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK16-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK16: for.body62: -// CHECK16-NEXT: [[TMP70:%.*]] = load double*, double** [[B]], align 4 -// CHECK16-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds double, double* [[TMP70]], i32 [[TMP71]] -// CHECK16-NEXT: [[TMP72:%.*]] = load double, double* [[ARRAYIDX63]], align 4 -// CHECK16-NEXT: [[TMP73:%.*]] = load double*, double** [[C]], align 4 -// CHECK16-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds double, double* [[TMP73]], i32 [[TMP74]] -// CHECK16-NEXT: [[TMP75:%.*]] = load double, double* [[ARRAYIDX64]], align 4 -// CHECK16-NEXT: [[ADD65:%.*]] = fadd double [[TMP72]], [[TMP75]] -// CHECK16-NEXT: [[TMP76:%.*]] = load double*, double** [[A]], align 4 -// CHECK16-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds double, double* [[TMP76]], i32 [[TMP77]] -// CHECK16-NEXT: store double [[ADD65]], double* [[ARRAYIDX66]], align 4 -// CHECK16-NEXT: br label [[FOR_INC67:%.*]] -// CHECK16: for.inc67: -// CHECK16-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK16-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end69: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[CH:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I59:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 10000, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP3]] -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 [[TMP6]] -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP7]] -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 [[TMP9]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX2]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4:%.*]] -// CHECK16: for.cond4: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END13:%.*]] -// CHECK16: for.body6: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 [[TMP14]] -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 [[TMP17]] -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], [[TMP18]] -// CHECK16-NEXT: [[TMP19:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i32 [[TMP20]] -// CHECK16-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX10]], align 4 -// CHECK16-NEXT: br label [[FOR_INC11:%.*]] -// CHECK16: for.inc11: -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK16-NEXT: store i32 [[INC12]], i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end13: -// CHECK16-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15:%.*]] -// CHECK16: for.cond15: -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] -// CHECK16-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK16: for.body17: -// CHECK16-NEXT: [[TMP24:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[TMP24]], i32 [[TMP25]] -// CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX18]], align 4 -// CHECK16-NEXT: [[TMP27:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i32 [[TMP28]] -// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[ARRAYIDX19]], align 4 -// CHECK16-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP26]], [[TMP29]] -// CHECK16-NEXT: [[TMP30:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP31:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[TMP30]], i32 [[TMP31]] -// CHECK16-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX21]], align 4 -// CHECK16-NEXT: br label [[FOR_INC22:%.*]] -// CHECK16: for.inc22: -// CHECK16-NEXT: [[TMP32:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK16-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK16-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK16-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end24: -// CHECK16-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26:%.*]] -// CHECK16: for.cond26: -// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[TMP34:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP33]], [[TMP34]] -// CHECK16-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK16: for.body28: -// CHECK16-NEXT: [[TMP35:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[TMP35]], i32 [[TMP36]] -// CHECK16-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARRAYIDX29]], align 4 -// CHECK16-NEXT: [[TMP38:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP39:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[TMP38]], i32 [[TMP39]] -// CHECK16-NEXT: [[TMP40:%.*]] = load i32, i32* [[ARRAYIDX30]], align 4 -// CHECK16-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP37]], [[TMP40]] -// CHECK16-NEXT: [[TMP41:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP42:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds i32, i32* [[TMP41]], i32 [[TMP42]] -// CHECK16-NEXT: store i32 [[ADD31]], i32* [[ARRAYIDX32]], align 4 -// CHECK16-NEXT: br label [[FOR_INC33:%.*]] -// CHECK16: for.inc33: -// CHECK16-NEXT: [[TMP43:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK16-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK16-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK16-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end35: -// CHECK16-NEXT: [[TMP44:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37:%.*]] -// CHECK16: for.cond37: -// CHECK16-NEXT: [[TMP45:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[TMP46:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP45]], [[TMP46]] -// CHECK16-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK16: for.body39: -// CHECK16-NEXT: [[TMP47:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP48:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[TMP47]], i32 [[TMP48]] -// CHECK16-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARRAYIDX40]], align 4 -// CHECK16-NEXT: [[TMP50:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP51:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds i32, i32* [[TMP50]], i32 [[TMP51]] -// CHECK16-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARRAYIDX41]], align 4 -// CHECK16-NEXT: [[ADD42:%.*]] = add nsw i32 [[TMP49]], [[TMP52]] -// CHECK16-NEXT: [[TMP53:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP54:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds i32, i32* [[TMP53]], i32 [[TMP54]] -// CHECK16-NEXT: store i32 [[ADD42]], i32* [[ARRAYIDX43]], align 4 -// CHECK16-NEXT: br label [[FOR_INC44:%.*]] -// CHECK16: for.inc44: -// CHECK16-NEXT: [[TMP55:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK16-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK16-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK16-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK16: for.end46: -// CHECK16-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48:%.*]] -// CHECK16: for.cond48: -// CHECK16-NEXT: [[TMP56:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP56]], [[TMP57]] -// CHECK16-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END57:%.*]] -// CHECK16: for.body50: -// CHECK16-NEXT: [[TMP58:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP59:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX51:%.*]] = getelementptr inbounds i32, i32* [[TMP58]], i32 [[TMP59]] -// CHECK16-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARRAYIDX51]], align 4 -// CHECK16-NEXT: [[TMP61:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP62:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX52:%.*]] = getelementptr inbounds i32, i32* [[TMP61]], i32 [[TMP62]] -// CHECK16-NEXT: [[TMP63:%.*]] = load i32, i32* [[ARRAYIDX52]], align 4 -// CHECK16-NEXT: [[ADD53:%.*]] = add nsw i32 [[TMP60]], [[TMP63]] -// CHECK16-NEXT: [[TMP64:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP65:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[ARRAYIDX54:%.*]] = getelementptr inbounds i32, i32* [[TMP64]], i32 [[TMP65]] -// CHECK16-NEXT: store i32 [[ADD53]], i32* [[ARRAYIDX54]], align 4 -// CHECK16-NEXT: br label [[FOR_INC55:%.*]] -// CHECK16: for.inc55: -// CHECK16-NEXT: [[TMP66:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK16-NEXT: [[INC56:%.*]] = add nsw i32 [[TMP66]], 1 -// CHECK16-NEXT: store i32 [[INC56]], i32* [[I47]], align 4 -// CHECK16-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK16: for.end57: -// CHECK16-NEXT: [[TMP67:%.*]] = load i32, i32* [[CH]], align 4 -// CHECK16-NEXT: store i32 [[TMP67]], i32* [[DOTCAPTURE_EXPR_58]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60:%.*]] -// CHECK16: for.cond60: -// CHECK16-NEXT: [[TMP68:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[TMP69:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP68]], [[TMP69]] -// CHECK16-NEXT: br i1 [[CMP61]], label [[FOR_BODY62:%.*]], label [[FOR_END69:%.*]] -// CHECK16: for.body62: -// CHECK16-NEXT: [[TMP70:%.*]] = load i32*, i32** [[B]], align 4 -// CHECK16-NEXT: [[TMP71:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX63:%.*]] = getelementptr inbounds i32, i32* [[TMP70]], i32 [[TMP71]] -// CHECK16-NEXT: [[TMP72:%.*]] = load i32, i32* [[ARRAYIDX63]], align 4 -// CHECK16-NEXT: [[TMP73:%.*]] = load i32*, i32** [[C]], align 4 -// CHECK16-NEXT: [[TMP74:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i32, i32* [[TMP73]], i32 [[TMP74]] -// CHECK16-NEXT: [[TMP75:%.*]] = load i32, i32* [[ARRAYIDX64]], align 4 -// CHECK16-NEXT: [[ADD65:%.*]] = add nsw i32 [[TMP72]], [[TMP75]] -// CHECK16-NEXT: [[TMP76:%.*]] = load i32*, i32** [[A]], align 4 -// CHECK16-NEXT: [[TMP77:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds i32, i32* [[TMP76]], i32 [[TMP77]] -// CHECK16-NEXT: store i32 [[ADD65]], i32* [[ARRAYIDX66]], align 4 -// CHECK16-NEXT: br label [[FOR_INC67:%.*]] -// CHECK16: for.inc67: -// CHECK16-NEXT: [[TMP78:%.*]] = load i32, i32* [[I59]], align 4 -// CHECK16-NEXT: [[INC68:%.*]] = add nsw i32 [[TMP78]], 1 -// CHECK16-NEXT: store i32 [[INC68]], i32* [[I59]], align 4 -// CHECK16-NEXT: br label [[FOR_COND60]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK16: for.end69: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp @@ -7,10 +7,10 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -19,12 +19,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1303,60 +1303,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// // CHECK8-LABEL: define {{[^@]+}}@main // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: @@ -5060,1119 +5006,4 @@ // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void // -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK12-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP14]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP14]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp @@ -3,32 +3,32 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2714,308 +2714,6 @@ // CHECK2-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: -// CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: -// CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: -// CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: -// CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: ret i32 0 -// -// // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: @@ -5610,308 +5308,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -8506,308 +7902,6 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z9gtid_testv() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn4v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn5v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn6v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn1v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn2v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn3v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z9gtid_testv() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn4v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn5v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn6v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn1v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn2v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn3v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: ret i32 0 -// -// // CHECK13-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -11401,305 +10495,4 @@ // CHECK14-NEXT: call void @__tgt_register_requires(i64 1) // CHECK14-NEXT: ret void // -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z9gtid_testv() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn4v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn5v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn6v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn1v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn2v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn3v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z9gtid_testv() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn4v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn5v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn6v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP6]]) -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn1v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn2v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP4]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn3v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1288,78 +1288,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -5343,1123 +5271,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done6: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done5: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP4]], %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done5: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp @@ -3,33 +3,33 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2337,504 +2337,6 @@ // CHECK2-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: lpad: -// CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: cleanup -// CHECK3-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK3-NEXT: br label [[EH_RESUME:%.*]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont6: -// CHECK3-NEXT: br label [[FOR_INC7:%.*]] -// CHECK3: for.inc7: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end9: -// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK3-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont10: -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK3-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont12: -// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK3-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP8]] -// CHECK3: eh.resume: -// CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK3-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK3-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_Z8mayThrowv() -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK3-NEXT: ret i8 [[CONV]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: ret i32 0 -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK3-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: ret i32 0 -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: lpad: -// CHECK4-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: cleanup -// CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK4-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK4-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK4-NEXT: br label [[EH_RESUME:%.*]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont6: -// CHECK4-NEXT: br label [[FOR_INC7:%.*]] -// CHECK4: for.inc7: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end9: -// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK4-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont10: -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK4-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont12: -// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK4-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP8]] -// CHECK4: eh.resume: -// CHECK4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK4-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK4-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_Z8mayThrowv() -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK4-NEXT: ret i8 [[CONV]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK4-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: ret i32 0 -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK4-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: ret i32 0 -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@main // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: @@ -5079,504 +4581,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK7-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont1: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: lpad: -// CHECK7-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: cleanup -// CHECK7-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK7-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK7-NEXT: br label [[EH_RESUME:%.*]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont6: -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK7-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont10: -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK7-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont12: -// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK7-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// CHECK7: eh.resume: -// CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK7-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_Z8mayThrowv() -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK7-NEXT: ret i8 [[CONV]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK7-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK8-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont1: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: lpad: -// CHECK8-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: cleanup -// CHECK8-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK8-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK8-NEXT: br label [[EH_RESUME:%.*]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont6: -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK8-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont10: -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK8-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont12: -// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK8-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// CHECK8: eh.resume: -// CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK8-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_Z8mayThrowv() -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK8-NEXT: ret i8 [[CONV]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: ret i32 0 -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK8-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: ret i32 0 -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: @@ -7821,504 +6825,6 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK11-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK11: invoke.cont: -// CHECK11-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK11: invoke.cont1: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: lpad: -// CHECK11-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: cleanup -// CHECK11-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK11-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK11-NEXT: br label [[EH_RESUME:%.*]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3:%.*]] -// CHECK11: for.cond3: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK11: for.body5: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK11: invoke.cont6: -// CHECK11-NEXT: br label [[FOR_INC7:%.*]] -// CHECK11: for.inc7: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end9: -// CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK11-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK11-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK11: invoke.cont10: -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK11-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK11-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK11: invoke.cont12: -// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK11-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: ret i32 [[TMP8]] -// CHECK11: eh.resume: -// CHECK11-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK11-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK11-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK11-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK11-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK11: terminate.lpad: -// CHECK11-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: catch i8* null -// CHECK11-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK11-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_Z8mayThrowv() -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK11-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK11-NEXT: ret i8 [[CONV]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK11-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK11: invoke.cont: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK11: invoke.cont5: -// CHECK11-NEXT: br label [[FOR_INC6:%.*]] -// CHECK11: for.inc6: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end8: -// CHECK11-NEXT: ret i32 0 -// CHECK11: terminate.lpad: -// CHECK11-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: catch i8* null -// CHECK11-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK11-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK11-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK11: invoke.cont: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: invoke void @_Z3foov() -// CHECK11-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK11: invoke.cont5: -// CHECK11-NEXT: br label [[FOR_INC6:%.*]] -// CHECK11: for.inc6: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end8: -// CHECK11-NEXT: ret i32 0 -// CHECK11: terminate.lpad: -// CHECK11-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK11-NEXT: catch i8* null -// CHECK11-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK11-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK11-NEXT: unreachable -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK12-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK12-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK12: invoke.cont: -// CHECK12-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK12: invoke.cont1: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: lpad: -// CHECK12-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: cleanup -// CHECK12-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK12-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK12-NEXT: br label [[EH_RESUME:%.*]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3:%.*]] -// CHECK12: for.cond3: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK12: for.body5: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK12: invoke.cont6: -// CHECK12-NEXT: br label [[FOR_INC7:%.*]] -// CHECK12: for.inc7: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end9: -// CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK12-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK12-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK12: invoke.cont10: -// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK12-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK12-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK12: invoke.cont12: -// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK12-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: ret i32 [[TMP8]] -// CHECK12: eh.resume: -// CHECK12-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK12-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK12-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK12-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK12-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK12: terminate.lpad: -// CHECK12-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: catch i8* null -// CHECK12-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK12-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_Z8mayThrowv() -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK12-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK12-NEXT: ret i8 [[CONV]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK12-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK12: invoke.cont: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK12: invoke.cont5: -// CHECK12-NEXT: br label [[FOR_INC6:%.*]] -// CHECK12: for.inc6: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end8: -// CHECK12-NEXT: ret i32 0 -// CHECK12: terminate.lpad: -// CHECK12-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: catch i8* null -// CHECK12-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK12-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK12-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK12: invoke.cont: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: invoke void @_Z3foov() -// CHECK12-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK12: invoke.cont5: -// CHECK12-NEXT: br label [[FOR_INC6:%.*]] -// CHECK12: for.inc6: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end8: -// CHECK12-NEXT: ret i32 0 -// CHECK12: terminate.lpad: -// CHECK12-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK12-NEXT: catch i8* null -// CHECK12-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK12-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK12-NEXT: unreachable -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// // CHECK13-LABEL: define {{[^@]+}}@main // CHECK13-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: @@ -10562,501 +9068,4 @@ // CHECK14-NEXT: call void @__tgt_register_requires(i64 1) // CHECK14-NEXT: ret void // -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK15-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK15-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK15: invoke.cont: -// CHECK15-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK15: invoke.cont1: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: lpad: -// CHECK15-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: cleanup -// CHECK15-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK15-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK15-NEXT: br label [[EH_RESUME:%.*]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3:%.*]] -// CHECK15: for.cond3: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK15: for.body5: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK15: invoke.cont6: -// CHECK15-NEXT: br label [[FOR_INC7:%.*]] -// CHECK15: for.inc7: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end9: -// CHECK15-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK15-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK15-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK15: invoke.cont10: -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK15-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK15-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK15: invoke.cont12: -// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK15-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// CHECK15: eh.resume: -// CHECK15-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK15-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK15-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK15-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK15-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK15: terminate.lpad: -// CHECK15-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: catch i8* null -// CHECK15-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK15-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_Z8mayThrowv() -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK15-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK15-NEXT: ret i8 [[CONV]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK15-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK15-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK15-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK15: invoke.cont: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK15: invoke.cont5: -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: ret i32 0 -// CHECK15: terminate.lpad: -// CHECK15-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: catch i8* null -// CHECK15-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK15-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK15-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK15: invoke.cont: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: invoke void @_Z3foov() -// CHECK15-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK15: invoke.cont5: -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: ret i32 0 -// CHECK15: terminate.lpad: -// CHECK15-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK15-NEXT: catch i8* null -// CHECK15-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK15-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK15-NEXT: unreachable -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK16-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK16-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK16: invoke.cont: -// CHECK16-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK16: invoke.cont1: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: lpad: -// CHECK16-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: cleanup -// CHECK16-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK16-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] -// CHECK16-NEXT: br label [[EH_RESUME:%.*]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3:%.*]] -// CHECK16: for.cond3: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK16: for.body5: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK16: invoke.cont6: -// CHECK16-NEXT: br label [[FOR_INC7:%.*]] -// CHECK16: for.inc7: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end9: -// CHECK16-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1 -// CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK16-NEXT: [[CALL11:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() -// CHECK16-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK16: invoke.cont10: -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK16-NEXT: [[CALL13:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() -// CHECK16-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK16: invoke.cont12: -// CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK16-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// CHECK16: eh.resume: -// CHECK16-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK16-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK16-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK16-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK16-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK16: terminate.lpad: -// CHECK16-NEXT: [[TMP9:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: catch i8* null -// CHECK16-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP9]], 0 -// CHECK16-NEXT: call void @__clang_call_terminate(i8* [[TMP10]]) #[[ATTR8:[0-9]+]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: call void @_Z8mayThrowv() -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK16-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK16-NEXT: ret i8 [[CONV]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK16-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR7]] -// CHECK16-NEXT: call void @_ZSt9terminatev() #[[ATTR8]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK16-SAME: () #[[ATTR5:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK16: invoke.cont: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK16: invoke.cont5: -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: ret i32 0 -// CHECK16: terminate.lpad: -// CHECK16-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: catch i8* null -// CHECK16-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK16-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK16-SAME: () #[[ATTR5]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK16: invoke.cont: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: invoke void @_Z3foov() -// CHECK16-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK16: invoke.cont5: -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: ret i32 0 -// CHECK16: terminate.lpad: -// CHECK16-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK16-NEXT: catch i8* null -// CHECK16-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK16-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR8]] -// CHECK16-NEXT: unreachable -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -883,58 +883,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3598,1267 +3546,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK13: arraydestroy.body10: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK13: arraydestroy.done14: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP11]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK13: arraydestroy.body10: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK13: arraydestroy.done14: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP11]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK14: arraydestroy.body10: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK14: arraydestroy.done14: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP11]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK14: arraydestroy.body10: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK14: arraydestroy.done14: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP11]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP11]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP11]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP11]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP11]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp @@ -5,9 +5,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -978,123 +978,4 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1273,62 +1273,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG23]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG25:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG27:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG31:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG31]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG31]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG32:![0-9]+]], !llvm.loop [[LOOP33:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG36]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_private_codegen.cpp b/clang/test/OpenMP/distribute_private_codegen.cpp --- a/clang/test/OpenMP/distribute_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_private_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -558,58 +558,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -2765,1331 +2713,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: br label [[FOR_INC14:%.*]] -// CHECK13: for.inc14: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end16: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK13: arraydestroy.body18: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK13: arraydestroy.done22: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK13-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK13: arraydestroy.body10: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK13: arraydestroy.done14: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP11]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: br label [[FOR_INC14:%.*]] -// CHECK14: for.inc14: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end16: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK14: arraydestroy.body18: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK14: arraydestroy.done22: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK14-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done8: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK14: arraydestroy.body10: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK14: arraydestroy.done14: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP11]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END15:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: br label [[FOR_INC13:%.*]] -// CHECK15: for.inc13: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC14]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end15: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] -// CHECK15: arraydestroy.body17: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] -// CHECK15: arraydestroy.done21: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK15-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP11]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END15:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: br label [[FOR_INC13:%.*]] -// CHECK16: for.inc13: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC14]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end15: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] -// CHECK16: arraydestroy.body17: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] -// CHECK16: arraydestroy.done21: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP11]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_firstprivate_codegen.cpp b/clang/test/OpenMP/for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/for_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1848,961 +1848,4 @@ // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP12]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP12]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store volatile i32 1, i32* [[TMP2]], align 4 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP3]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP4]], i32** [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED3]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP6]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP10]](i8* [[TMP8]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store i32 2, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_lastprivate_codegen.cpp b/clang/test/OpenMP/for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/for_lastprivate_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -7858,3411 +7858,4 @@ // CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK9-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK9-NEXT: br label [[FOR_COND4:%.*]] -// CHECK9: for.cond4: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK9-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK9: for.body6: -// CHECK9-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: br label [[FOR_INC8:%.*]] -// CHECK9: for.inc8: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK9-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK9-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end10: -// CHECK9-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK9-NEXT: br label [[FOR_COND12:%.*]] -// CHECK9: for.cond12: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK9-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK9: for.body14: -// CHECK9-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: br label [[FOR_INC16:%.*]] -// CHECK9: for.inc16: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK9-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK9-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end18: -// CHECK9-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK9-NEXT: br label [[FOR_COND19:%.*]] -// CHECK9: for.cond19: -// CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK9-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK9-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK9: for.body21: -// CHECK9-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK9-NEXT: br label [[FOR_INC23:%.*]] -// CHECK9: for.inc23: -// CHECK9-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK9-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK9-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK9-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end25: -// CHECK9-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done27: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP18]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done4: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP10]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK9-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK9-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK9-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK9-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK9-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK9-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK9-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK9-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK9-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK9-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK9-NEXT: br label [[FOR_COND14:%.*]] -// CHECK9: for.cond14: -// CHECK9-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK9-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK9-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK9: for.body17: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK9-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK9-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK9-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK9-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK9-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK9-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK9-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK9-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK9-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK9-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK9-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK9-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK9-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK9-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK9-NEXT: br label [[FOR_INC26:%.*]] -// CHECK9: for.inc26: -// CHECK9-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK9-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK9-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK9-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK9: for.end29: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK9-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK9-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK9-NEXT: br label [[FOR_COND8:%.*]] -// CHECK9: for.cond8: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK9-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK9-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK9: for.body10: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK9-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC12:%.*]] -// CHECK9: for.inc12: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK9-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK9-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK9: for.end14: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK10-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK10-NEXT: br label [[FOR_COND4:%.*]] -// CHECK10: for.cond4: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK10-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK10: for.body6: -// CHECK10-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: br label [[FOR_INC8:%.*]] -// CHECK10: for.inc8: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK10-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK10-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end10: -// CHECK10-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK10-NEXT: br label [[FOR_COND12:%.*]] -// CHECK10: for.cond12: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK10-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK10-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK10: for.body14: -// CHECK10-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: br label [[FOR_INC16:%.*]] -// CHECK10: for.inc16: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK10-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK10-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end18: -// CHECK10-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK10-NEXT: br label [[FOR_COND19:%.*]] -// CHECK10: for.cond19: -// CHECK10-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK10-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK10-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK10: for.body21: -// CHECK10-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK10-NEXT: br label [[FOR_INC23:%.*]] -// CHECK10: for.inc23: -// CHECK10-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK10-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK10-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK10-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end25: -// CHECK10-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done27: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP18]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK10-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done4: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP10]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK10-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK10-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK10-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK10-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK10-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK10-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK10-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK10-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK10-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK10-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK10-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK10-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK10-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK10-NEXT: br label [[FOR_COND14:%.*]] -// CHECK10: for.cond14: -// CHECK10-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK10-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK10-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK10: for.body17: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK10-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK10-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK10-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK10-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK10-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK10-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK10-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK10-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK10-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK10-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK10-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK10-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK10-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK10-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK10-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK10-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK10-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK10-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK10-NEXT: br label [[FOR_INC26:%.*]] -// CHECK10: for.inc26: -// CHECK10-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK10-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK10-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK10-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK10: for.end29: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK10-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK10-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK10-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK10-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK10-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK10-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK10-NEXT: br label [[FOR_COND8:%.*]] -// CHECK10: for.cond8: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK10-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK10-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK10: for.body10: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK10-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC12:%.*]] -// CHECK10: for.inc12: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK10-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK10-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK10: for.end14: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK11-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK11-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK11-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK11-NEXT: [[A10:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[REF_TMP17:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK11-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK11-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK11-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK11-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK11-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK11-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK11-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK11-NEXT: store i32* [[B5]], i32** [[TMP9]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK11-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: [[A11:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32* [[A11]], i32** [[A10]], align 8 -// CHECK11-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: store i32 0, i32* [[A12]], align 8 -// CHECK11-NEXT: br label [[FOR_COND13:%.*]] -// CHECK11: for.cond13: -// CHECK11-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[A14]], align 8 -// CHECK11-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK11-NEXT: br i1 [[CMP15]], label [[FOR_BODY16:%.*]], label [[FOR_END21:%.*]] -// CHECK11: for.body16: -// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 0 -// CHECK11-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP14]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A10]], align 8 -// CHECK11-NEXT: store i32* [[TMP16]], i32** [[TMP15]], align 8 -// CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP17]]) -// CHECK11-NEXT: br label [[FOR_INC18:%.*]] -// CHECK11: for.inc18: -// CHECK11-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[A19]], align 8 -// CHECK11-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: store i32 [[INC20]], i32* [[A19]], align 8 -// CHECK11-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end21: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK11-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK11-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK11-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK11-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP19]], 2 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[INC5]], i32* [[TMP20]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP22]], -1 -// CHECK11-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP24]], 1 -// CHECK11-NEXT: store i32 [[DIV7]], i32* [[TMP23]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK11-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE0_clEv -// CHECK11-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK11-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP4]], -1 -// CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP3]], align 4 -// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 2 -// CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK11-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK11-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[BF_CAST]], 1 -// CHECK11-NEXT: [[TMP5:%.*]] = trunc i32 [[INC]] to i8 -// CHECK11-NEXT: [[BF_LOAD2:%.*]] = load i8, i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 -// CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD2]], -16 -// CHECK11-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK11-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK11-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK11-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK11-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 -// CHECK11-NEXT: store i32 [[MUL]], i32* [[TMP6]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK11-NEXT: store i32* [[TMP9]], i32** [[TMP]], align 8 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK11-NEXT: store i32* [[TMP10]], i32** [[_TMP4]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[B3]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: store i32 [[INC5]], i32* [[TMP12]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK11-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP14]], -1 -// CHECK11-NEXT: store i32 [[DEC6]], i32* [[B3]], align 4 -// CHECK11-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP16]], 1 -// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP15]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK11-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK11-NEXT: store i32 [[INC8]], i32* [[B3]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK12-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, align 128 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK12-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: store i32 1, i32* @g, align 128 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store volatile i32 1, i32* [[TMP2]], align 4 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: store i32 1, i32* @g, align 128 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store volatile i32 1, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK12-NEXT: store volatile i32 [[TMP4]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED2]], align 32 -// CHECK12-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED3]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP11]](i8* [[TMP9]]) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK12-NEXT: store i32 1, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK12-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK12-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK12-NEXT: [[A12:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[BLOCK19:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, align 8 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK12-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK12-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK12-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK12-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK12-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK12-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK12-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK12-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK12-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED10:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK12-NEXT: store i32 [[TMP7]], i32* [[BLOCK_CAPTURED10]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED11:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK12-NEXT: store i32* [[TMP8]], i32** [[BLOCK_CAPTURED11]], align 8 -// CHECK12-NEXT: [[TMP9:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP9]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP13]](i8* [[TMP11]]) -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32* [[A13]], i32** [[A12]], align 8 -// CHECK12-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: store i32 0, i32* [[A14]], align 8 -// CHECK12-NEXT: br label [[FOR_COND15:%.*]] -// CHECK12: for.cond15: -// CHECK12-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[A16]], align 8 -// CHECK12-NEXT: [[CMP17:%.*]] = icmp slt i32 [[TMP15]], 2 -// CHECK12-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END31:%.*]] -// CHECK12: for.body18: -// CHECK12-NEXT: [[BLOCK_ISA20:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA20]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS21:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS21]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED22:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED22]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE23:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE23]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR24:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR24]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR25:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 5 -// CHECK12-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR25]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED26:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A12]], align 8 -// CHECK12-NEXT: store i32* [[TMP16]], i32** [[BLOCK_CAPTURED26]], align 8 -// CHECK12-NEXT: [[TMP17:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL27:%.*]] = bitcast void ()* [[TMP17]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC]], %struct.__block_literal_generic* [[BLOCK_LITERAL27]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL27]] to i8* -// CHECK12-NEXT: [[TMP20:%.*]] = load i8*, i8** [[TMP18]], align 8 -// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP21]](i8* [[TMP19]]) -// CHECK12-NEXT: br label [[FOR_INC28:%.*]] -// CHECK12: for.inc28: -// CHECK12-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[A29]], align 8 -// CHECK12-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[INC30]], i32* [[A29]], align 8 -// CHECK12-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end31: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK12-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP7]], i32** [[_TMP7]], align 8 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK12-NEXT: store i32* [[TMP8]], i32** [[_TMP8]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP9]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[INC9]], i32* [[TMP10]], align 4 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK12-NEXT: [[DEC10:%.*]] = add nsw i32 [[TMP12]], -1 -// CHECK12-NEXT: store i32 [[DEC10]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK12-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[DIV11]], i32* [[TMP13]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[INC12]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>*, align 8 -// CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: [[C4:%.*]] = alloca i32*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK12-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK12-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK12-NEXT: [[TMP2:%.*]] = trunc i32 [[DEC]] to i8 -// CHECK12-NEXT: [[BF_LOAD1:%.*]] = load i8, i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP2]], 15 -// CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD1]], -16 -// CHECK12-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK12-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK12-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK12-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK12-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK12-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK12-NEXT: store i32* [[TMP6]], i32** [[_TMP3]], align 8 -// CHECK12-NEXT: [[C5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK12-NEXT: store i32* [[TMP7]], i32** [[C4]], align 8 -// CHECK12-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[TMP8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK12-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[INC8]], i32* [[TMP11]], align 4 -// CHECK12-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK12-NEXT: [[BF_LOAD10:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK12-NEXT: [[BF_SHL11:%.*]] = shl i8 [[BF_LOAD10]], 4 -// CHECK12-NEXT: [[BF_ASHR12:%.*]] = ashr i8 [[BF_SHL11]], 4 -// CHECK12-NEXT: [[BF_CAST13:%.*]] = sext i8 [[BF_ASHR12]] to i32 -// CHECK12-NEXT: [[DEC14:%.*]] = add nsw i32 [[BF_CAST13]], -1 -// CHECK12-NEXT: [[TMP13:%.*]] = trunc i32 [[DEC14]] to i8 -// CHECK12-NEXT: [[BF_LOAD15:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK12-NEXT: [[BF_VALUE16:%.*]] = and i8 [[TMP13]], 15 -// CHECK12-NEXT: [[BF_CLEAR17:%.*]] = and i8 [[BF_LOAD15]], -16 -// CHECK12-NEXT: [[BF_SET18:%.*]] = or i8 [[BF_CLEAR17]], [[BF_VALUE16]] -// CHECK12-NEXT: store i8 [[BF_SET18]], i8* [[B9]], align 8 -// CHECK12-NEXT: [[BF_RESULT_SHL19:%.*]] = shl i8 [[BF_VALUE16]], 4 -// CHECK12-NEXT: [[BF_RESULT_ASHR20:%.*]] = ashr i8 [[BF_RESULT_SHL19]], 4 -// CHECK12-NEXT: [[BF_RESULT_CAST21:%.*]] = sext i8 [[BF_RESULT_ASHR20]] to i32 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[C4]], align 8 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK12-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[DIV22]], i32* [[TMP14]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[C23:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C23]], align 8 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK12-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK12-NEXT: store i32 [[INC24]], i32* [[TMP16]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK13-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4:%.*]] -// CHECK13: for.cond4: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK13-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK13: for.body6: -// CHECK13-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: br label [[FOR_INC8:%.*]] -// CHECK13: for.inc8: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end10: -// CHECK13-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK13-NEXT: br label [[FOR_COND12:%.*]] -// CHECK13: for.cond12: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK13-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK13-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body14: -// CHECK13-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK13-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK13-NEXT: br label [[FOR_COND19:%.*]] -// CHECK13: for.cond19: -// CHECK13-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK13-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK13-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK13: for.body21: -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK13-NEXT: br label [[FOR_INC23:%.*]] -// CHECK13: for.inc23: -// CHECK13-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK13-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK13-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK13-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end25: -// CHECK13-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done27: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK13-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP10]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK13-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK13-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK13-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK13-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK13-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK13-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK13-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK13-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK13-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK13-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK13-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK13-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK13-NEXT: br label [[FOR_COND14:%.*]] -// CHECK13: for.cond14: -// CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK13-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK13-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK13: for.body17: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK13-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK13-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK13-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK13-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK13-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK13-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK13-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK13-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK13-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK13-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK13-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK13-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK13-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK13-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK13-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK13-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK13-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK13-NEXT: br label [[FOR_INC26:%.*]] -// CHECK13: for.inc26: -// CHECK13-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK13-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK13-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK13-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end29: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK13-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK13-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK13-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK13-NEXT: br label [[FOR_COND8:%.*]] -// CHECK13: for.cond8: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK13-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK13: for.body10: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK13-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK13-NEXT: br label [[FOR_INC12:%.*]] -// CHECK13: for.inc12: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK13-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK13-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK13: for.end14: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX2]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK14-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4:%.*]] -// CHECK14: for.cond4: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 2 -// CHECK14-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END10:%.*]] -// CHECK14: for.body6: -// CHECK14-NEXT: [[TMP9:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC7:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC7]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: br label [[FOR_INC8:%.*]] -// CHECK14: for.inc8: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC9]], i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end10: -// CHECK14-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK14-NEXT: br label [[FOR_COND12:%.*]] -// CHECK14: for.cond12: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK14-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK14-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body14: -// CHECK14-NEXT: [[TMP12:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC15:%.*]] = fadd double [[TMP12]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC15]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I11]], align 4 -// CHECK14-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i8 0, i8* @cnt, align 1 -// CHECK14-NEXT: br label [[FOR_COND19:%.*]] -// CHECK14: for.cond19: -// CHECK14-NEXT: [[TMP14:%.*]] = load i8, i8* @cnt, align 1 -// CHECK14-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK14-NEXT: [[CMP20:%.*]] = icmp slt i32 [[CONV]], 2 -// CHECK14-NEXT: br i1 [[CMP20]], label [[FOR_BODY21:%.*]], label [[FOR_END25:%.*]] -// CHECK14: for.body21: -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC22]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: store float 0.000000e+00, float* @f, align 4 -// CHECK14-NEXT: br label [[FOR_INC23:%.*]] -// CHECK14: for.inc23: -// CHECK14-NEXT: [[TMP16:%.*]] = load i8, i8* @cnt, align 1 -// CHECK14-NEXT: [[INC24:%.*]] = add i8 [[TMP16]], 1 -// CHECK14-NEXT: store i8 [[INC24]], i8* @cnt, align 1 -// CHECK14-NEXT: br label [[FOR_COND19]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end25: -// CHECK14-NEXT: [[CALL26:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL26]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done27: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK14-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP6]]) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP10]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK14-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK14-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A11:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK14-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK14-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK14-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK14-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK14-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK14-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK14-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK14-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK14-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK14-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP6]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[B5]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC10]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A12]], i32** [[A11]], align 8 -// CHECK14-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A13]], align 8 -// CHECK14-NEXT: br label [[FOR_COND14:%.*]] -// CHECK14: for.cond14: -// CHECK14-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[A15]], align 8 -// CHECK14-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP12]], 2 -// CHECK14-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END29:%.*]] -// CHECK14: for.body17: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A11]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK14-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC18]], i32* [[TMP13]], align 4 -// CHECK14-NEXT: [[B19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[BF_LOAD20:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK14-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD20]], 4 -// CHECK14-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK14-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK14-NEXT: [[DEC21:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK14-NEXT: [[TMP15:%.*]] = trunc i32 [[DEC21]] to i8 -// CHECK14-NEXT: [[BF_LOAD22:%.*]] = load i8, i8* [[B19]], align 8 -// CHECK14-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP15]], 15 -// CHECK14-NEXT: [[BF_CLEAR23:%.*]] = and i8 [[BF_LOAD22]], -16 -// CHECK14-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR23]], [[BF_VALUE]] -// CHECK14-NEXT: store i8 [[BF_SET]], i8* [[B19]], align 8 -// CHECK14-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK14-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK14-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK14-NEXT: [[C24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C24]], align 8 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK14-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP17]], 1 -// CHECK14-NEXT: store i32 [[DIV25]], i32* [[TMP16]], align 4 -// CHECK14-NEXT: br label [[FOR_INC26:%.*]] -// CHECK14: for.inc26: -// CHECK14-NEXT: [[A27:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A27]], align 8 -// CHECK14-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK14-NEXT: store i32 [[INC28]], i32* [[A27]], align 8 -// CHECK14-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end29: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK14-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK14-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A5:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A6]], i32** [[A5]], align 8 -// CHECK14-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A7]], align 4 -// CHECK14-NEXT: br label [[FOR_COND8:%.*]] -// CHECK14: for.cond8: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK14-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP6]], 2 -// CHECK14-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END14:%.*]] -// CHECK14: for.body10: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK14-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC11]], i32* [[TMP7]], align 4 -// CHECK14-NEXT: br label [[FOR_INC12:%.*]] -// CHECK14: for.inc12: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[A5]], align 8 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK14-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC13]], i32* [[TMP9]], align 4 -// CHECK14-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK14: for.end14: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK15-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK15-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK15-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK15-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK15-NEXT: [[A10:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[REF_TMP17:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK15-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK15-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK15-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK15-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK15-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK15-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK15-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK15-NEXT: store i32* [[B5]], i32** [[TMP9]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK15-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK15-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[A11:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32* [[A11]], i32** [[A10]], align 8 -// CHECK15-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A12]], align 8 -// CHECK15-NEXT: br label [[FOR_COND13:%.*]] -// CHECK15: for.cond13: -// CHECK15-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[A14]], align 8 -// CHECK15-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK15-NEXT: br i1 [[CMP15]], label [[FOR_BODY16:%.*]], label [[FOR_END21:%.*]] -// CHECK15: for.body16: -// CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 0 -// CHECK15-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP14]], align 8 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP17]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A10]], align 8 -// CHECK15-NEXT: store i32* [[TMP16]], i32** [[TMP15]], align 8 -// CHECK15-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP17]]) -// CHECK15-NEXT: br label [[FOR_INC18:%.*]] -// CHECK15: for.inc18: -// CHECK15-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[A19]], align 8 -// CHECK15-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[INC20]], i32* [[A19]], align 8 -// CHECK15-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end21: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK15-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK15-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK15-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK15-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP19]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK15-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[INC5]], i32* [[TMP20]], align 4 -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP22]], -1 -// CHECK15-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK15-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP24]], 1 -// CHECK15-NEXT: store i32 [[DIV7]], i32* [[TMP23]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE0_clEv -// CHECK15-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP4]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 2 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK15-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK15-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[BF_CAST]], 1 -// CHECK15-NEXT: [[TMP5:%.*]] = trunc i32 [[INC]] to i8 -// CHECK15-NEXT: [[BF_LOAD2:%.*]] = load i8, i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP5]], 15 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD2]], -16 -// CHECK15-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK15-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK15-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK15-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK15-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 -// CHECK15-NEXT: store i32 [[MUL]], i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK15-NEXT: store i32* [[TMP9]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP10]], i32** [[_TMP4]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[B3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP11]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 -// CHECK15-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK15-NEXT: store i32 [[INC5]], i32* [[TMP12]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP14]], -1 -// CHECK15-NEXT: store i32 [[DEC6]], i32* [[B3]], align 4 -// CHECK15-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP16]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP15]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[B3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK16-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, align 128 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 1, i32* @g, align 128 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store volatile i32 1, i32* [[TMP2]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 1, i32* @g, align 128 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store volatile i32 1, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: store volatile i32 [[TMP4]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED2]], align 32 -// CHECK16-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED3]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP11]](i8* [[TMP9]]) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK16-NEXT: store i32 1, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK16-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[E:%.*]] = alloca [4 x i8]*, align 8 -// CHECK16-NEXT: [[A3:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[B5:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C6:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP9:%.*]] = alloca [4 x i8]*, align 8 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK16-NEXT: [[A12:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[BLOCK19:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK16-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 8 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK16-NEXT: [[E2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: store [4 x i8]* [[E2]], [4 x i8]** [[E]], align 8 -// CHECK16-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32* [[A4]], i32** [[A3]], align 8 -// CHECK16-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK16-NEXT: store i32* [[TMP1]], i32** [[C6]], align 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A3]], align 8 -// CHECK16-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK16-NEXT: store i32* [[TMP3]], i32** [[_TMP8]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load [4 x i8]*, [4 x i8]** [[E]], align 8 -// CHECK16-NEXT: store [4 x i8]* [[TMP4]], [4 x i8]** [[_TMP9]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED10:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[B5]], align 4 -// CHECK16-NEXT: store i32 [[TMP7]], i32* [[BLOCK_CAPTURED10]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED11:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK16-NEXT: store i32* [[TMP8]], i32** [[BLOCK_CAPTURED11]], align 8 -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP9]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 -// CHECK16-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP13]](i8* [[TMP11]]) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32* [[A13]], i32** [[A12]], align 8 -// CHECK16-NEXT: [[A14:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A14]], align 8 -// CHECK16-NEXT: br label [[FOR_COND15:%.*]] -// CHECK16: for.cond15: -// CHECK16-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[A16]], align 8 -// CHECK16-NEXT: [[CMP17:%.*]] = icmp slt i32 [[TMP15]], 2 -// CHECK16-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END31:%.*]] -// CHECK16: for.body18: -// CHECK16-NEXT: [[BLOCK_ISA20:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA20]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS21:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS21]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED22:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED22]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE23:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE23]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR24:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR24]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS_ADDR25:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 5 -// CHECK16-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR25]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED26:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32*, i32** [[A12]], align 8 -// CHECK16-NEXT: store i32* [[TMP16]], i32** [[BLOCK_CAPTURED26]], align 8 -// CHECK16-NEXT: [[TMP17:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK19]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL27:%.*]] = bitcast void ()* [[TMP17]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC]], %struct.__block_literal_generic* [[BLOCK_LITERAL27]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP19:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL27]] to i8* -// CHECK16-NEXT: [[TMP20:%.*]] = load i8*, i8** [[TMP18]], align 8 -// CHECK16-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP21]](i8* [[TMP19]]) -// CHECK16-NEXT: br label [[FOR_INC28:%.*]] -// CHECK16: for.inc28: -// CHECK16-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[A29]], align 8 -// CHECK16-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK16-NEXT: store i32 [[INC30]], i32* [[A29]], align 8 -// CHECK16-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end31: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP7]], i32** [[_TMP7]], align 8 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK16-NEXT: store i32* [[TMP8]], i32** [[_TMP8]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP9]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK16-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC9]], i32* [[TMP10]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[DEC10:%.*]] = add nsw i32 [[TMP12]], -1 -// CHECK16-NEXT: store i32 [[DEC10]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK16-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[DIV11]], i32* [[TMP13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[INC12]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[C4:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 4 -// CHECK16-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK16-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[BF_CAST]], -1 -// CHECK16-NEXT: [[TMP2:%.*]] = trunc i32 [[DEC]] to i8 -// CHECK16-NEXT: [[BF_LOAD1:%.*]] = load i8, i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_VALUE:%.*]] = and i8 [[TMP2]], 15 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD1]], -16 -// CHECK16-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], [[BF_VALUE]] -// CHECK16-NEXT: store i8 [[BF_SET]], i8* [[B]], align 8 -// CHECK16-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 -// CHECK16-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 -// CHECK16-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[_TMP3]], align 8 -// CHECK16-NEXT: [[C5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK16-NEXT: store i32* [[TMP7]], i32** [[C4]], align 8 -// CHECK16-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK16-NEXT: store i32 0, i32* [[TMP8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[C7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK16-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC8]], i32* [[TMP11]], align 4 -// CHECK16-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 2 -// CHECK16-NEXT: [[BF_LOAD10:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK16-NEXT: [[BF_SHL11:%.*]] = shl i8 [[BF_LOAD10]], 4 -// CHECK16-NEXT: [[BF_ASHR12:%.*]] = ashr i8 [[BF_SHL11]], 4 -// CHECK16-NEXT: [[BF_CAST13:%.*]] = sext i8 [[BF_ASHR12]] to i32 -// CHECK16-NEXT: [[DEC14:%.*]] = add nsw i32 [[BF_CAST13]], -1 -// CHECK16-NEXT: [[TMP13:%.*]] = trunc i32 [[DEC14]] to i8 -// CHECK16-NEXT: [[BF_LOAD15:%.*]] = load i8, i8* [[B9]], align 8 -// CHECK16-NEXT: [[BF_VALUE16:%.*]] = and i8 [[TMP13]], 15 -// CHECK16-NEXT: [[BF_CLEAR17:%.*]] = and i8 [[BF_LOAD15]], -16 -// CHECK16-NEXT: [[BF_SET18:%.*]] = or i8 [[BF_CLEAR17]], [[BF_VALUE16]] -// CHECK16-NEXT: store i8 [[BF_SET18]], i8* [[B9]], align 8 -// CHECK16-NEXT: [[BF_RESULT_SHL19:%.*]] = shl i8 [[BF_VALUE16]], 4 -// CHECK16-NEXT: [[BF_RESULT_ASHR20:%.*]] = ashr i8 [[BF_RESULT_SHL19]], 4 -// CHECK16-NEXT: [[BF_RESULT_CAST21:%.*]] = sext i8 [[BF_RESULT_ASHR20]] to i32 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32*, i32** [[C4]], align 8 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK16-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[DIV22]], i32* [[TMP14]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[C23:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32*, i32** [[C23]], align 8 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 -// CHECK16-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: store i32 [[INC24]], i32* [[TMP16]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_linear_codegen.cpp b/clang/test/OpenMP/for_linear_codegen.cpp --- a/clang/test/OpenMP/for_linear_codegen.cpp +++ b/clang/test/OpenMP/for_linear_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -2570,980 +2570,4 @@ // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK5-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK5-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK5-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK5-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[F1]], i32** [[LVAR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[LVAR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[_TMP2]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 1 -// CHECK5-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[INC3]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK6-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK6-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK6-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK6-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[F1]], i32** [[LVAR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[LVAR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[_TMP2]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 1 -// CHECK6-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC3]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP2]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC4]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK7-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK7-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP19]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK7-NEXT: store i32 [[INC5]], i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP22]], -1 -// CHECK7-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP23:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 -// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP24]], 1 -// CHECK7-NEXT: store i32 [[DIV7]], i32* [[TMP23]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK2:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** @g1, align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5 -// CHECK8-NEXT: store i32 [[ADD]], i32* @g, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load volatile i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 5 -// CHECK8-NEXT: store volatile i32 [[ADD1]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store volatile i32 5, i32* [[TMP5]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP6:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP6]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED3]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK2]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store i32 2, i32* [[TMP0]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK8-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED8]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED9:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED9]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP8:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[_TMP7]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK8-NEXT: store i32* [[TMP8]], i32** [[_TMP8]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP9]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[DEC10:%.*]] = add nsw i32 [[TMP12]], -1 -// CHECK8-NEXT: store i32 [[DEC10]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP8]], align 8 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 -// CHECK8-NEXT: [[DIV11:%.*]] = sdiv i32 [[TMP14]], 1 -// CHECK8-NEXT: store i32 [[DIV11]], i32* [[TMP13]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK8-NEXT: store i32 [[INC12]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_private_codegen.cpp b/clang/test/OpenMP/for_private_codegen.cpp --- a/clang/test/OpenMP/for_private_codegen.cpp +++ b/clang/test/OpenMP/for_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1326,773 +1326,4 @@ // CHECK4-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11:%.*]] -// CHECK5: for.cond11: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK5-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK5: for.body13: -// CHECK5-NEXT: br label [[FOR_INC14:%.*]] -// CHECK5: for.inc14: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end16: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK5: arraydestroy.body18: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK5: arraydestroy.done22: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S* [[VAR4]], %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11:%.*]] -// CHECK6: for.cond11: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP10]], 2 -// CHECK6-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END16:%.*]] -// CHECK6: for.body13: -// CHECK6-NEXT: br label [[FOR_INC14:%.*]] -// CHECK6: for.inc14: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[INC15]], i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end16: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] -// CHECK6: arraydestroy.body18: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END16]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] -// CHECK6: arraydestroy.done22: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[SVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SFVAR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double* [[G1]], double** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store double 1.000000e+00, double* [[G]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store volatile double 1.000000e+00, double* [[TMP1]], align 8 -// CHECK8-NEXT: store i32 2, i32* [[SVAR]], align 4 -// CHECK8-NEXT: store float 3.000000e+00, float* [[SFVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP2:%.*]] = load volatile double, double* [[G]], align 8 -// CHECK8-NEXT: store volatile double [[TMP2]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP3]], double** [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[SVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[BLOCK_CAPTURED3]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* [[SFVAR]], align 4 -// CHECK8-NEXT: store float [[TMP5]], float* [[BLOCK_CAPTURED4]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP6]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP10]](i8* [[TMP8]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store double 2.000000e+00, double* [[TMP0]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp --- a/clang/test/OpenMP/for_reduction_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -8832,1436 +8832,4 @@ // CHECK4-NEXT: store double [[ADD2]], double* [[TMP17]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [4 x %struct.S], align 16 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[ARRS:%.*]] = alloca [10 x [4 x %struct.S]], align 16 -// CHECK5-NEXT: [[VAR2:%.*]] = alloca %struct.S**, align 8 -// CHECK5-NEXT: [[VVAR2:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK5-NEXT: [[VAR3:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[_TMP10:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I54:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I68:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I75:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP82:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP83:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I84:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP91:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP92:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I93:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP100:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP101:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I102:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP109:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[_TMP110:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK5-NEXT: [[I111:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) -// CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 40 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call %struct.S** @_Z3foov() -// CHECK5-NEXT: store %struct.S** [[CALL]], %struct.S*** [[VAR2]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 5 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] -// CHECK5: arrayctor.loop5: -// CHECK5-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR6]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR6]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] -// CHECK5: arrayctor.cont9: -// CHECK5-NEXT: store [4 x %struct.S]* [[S_ARR]], [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[_TMP10]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP10]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM11]] -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX13]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[TMP13:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP13]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP14:%.*]] = mul nuw i64 10, [[TMP12]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP14]], align 16 -// CHECK5-NEXT: store i64 [[TMP12]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK5-NEXT: br label [[FOR_COND15:%.*]] -// CHECK5: for.cond15: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK5-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP15]], 10 -// CHECK5-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK5: for.body17: -// CHECK5-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP16]] -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK5-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX18]], i64 [[IDXPROM19]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4 -// CHECK5-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK5-NEXT: store i32 [[INC21]], i32* [[ARRAYIDX20]], align 4 -// CHECK5-NEXT: br label [[FOR_INC22:%.*]] -// CHECK5: for.inc22: -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK5-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK5-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK5-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end24: -// CHECK5-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK5-NEXT: br label [[FOR_COND26:%.*]] -// CHECK5: for.cond26: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK5-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP20]], 10 -// CHECK5-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK5: for.body28: -// CHECK5-NEXT: [[TMP21:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK5-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP21]] -// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK5-NEXT: [[IDXPROM30:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK5-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX29]], i64 [[IDXPROM30]] -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX31]], align 4 -// CHECK5-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK5-NEXT: store i32 [[INC32]], i32* [[ARRAYIDX31]], align 4 -// CHECK5-NEXT: br label [[FOR_INC33:%.*]] -// CHECK5: for.inc33: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK5-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK5-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK5-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end35: -// CHECK5-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK5-NEXT: br label [[FOR_COND37:%.*]] -// CHECK5: for.cond37: -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK5-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP25]], 10 -// CHECK5-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK5: for.body39: -// CHECK5-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK5-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP26]] -// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK5-NEXT: [[IDXPROM41:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK5-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX40]], i64 [[IDXPROM41]] -// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX42]], align 4 -// CHECK5-NEXT: [[INC43:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK5-NEXT: store i32 [[INC43]], i32* [[ARRAYIDX42]], align 4 -// CHECK5-NEXT: br label [[FOR_INC44:%.*]] -// CHECK5: for.inc44: -// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK5-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK5-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK5-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end46: -// CHECK5-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK5-NEXT: br label [[FOR_COND48:%.*]] -// CHECK5: for.cond48: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK5-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP30]], 10 -// CHECK5-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END53:%.*]] -// CHECK5: for.body50: -// CHECK5-NEXT: br label [[FOR_INC51:%.*]] -// CHECK5: for.inc51: -// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK5-NEXT: [[INC52:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK5-NEXT: store i32 [[INC52]], i32* [[I47]], align 4 -// CHECK5-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK5: for.end53: -// CHECK5-NEXT: store i32 0, i32* [[I54]], align 4 -// CHECK5-NEXT: br label [[FOR_COND55:%.*]] -// CHECK5: for.cond55: -// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK5-NEXT: [[CMP56:%.*]] = icmp slt i32 [[TMP32]], 10 -// CHECK5-NEXT: br i1 [[CMP56]], label [[FOR_BODY57:%.*]], label [[FOR_END60:%.*]] -// CHECK5: for.body57: -// CHECK5-NEXT: br label [[FOR_INC58:%.*]] -// CHECK5: for.inc58: -// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK5-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP33]], 1 -// CHECK5-NEXT: store i32 [[INC59]], i32* [[I54]], align 4 -// CHECK5-NEXT: br label [[FOR_COND55]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK5: for.end60: -// CHECK5-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK5-NEXT: br label [[FOR_COND62:%.*]] -// CHECK5: for.cond62: -// CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK5-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP34]], 10 -// CHECK5-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END67:%.*]] -// CHECK5: for.body64: -// CHECK5-NEXT: br label [[FOR_INC65:%.*]] -// CHECK5: for.inc65: -// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK5-NEXT: [[INC66:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK5-NEXT: store i32 [[INC66]], i32* [[I61]], align 4 -// CHECK5-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK5: for.end67: -// CHECK5-NEXT: store i32 0, i32* [[I68]], align 4 -// CHECK5-NEXT: br label [[FOR_COND69:%.*]] -// CHECK5: for.cond69: -// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK5-NEXT: [[CMP70:%.*]] = icmp slt i32 [[TMP36]], 10 -// CHECK5-NEXT: br i1 [[CMP70]], label [[FOR_BODY71:%.*]], label [[FOR_END74:%.*]] -// CHECK5: for.body71: -// CHECK5-NEXT: br label [[FOR_INC72:%.*]] -// CHECK5: for.inc72: -// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK5-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP37]], 1 -// CHECK5-NEXT: store i32 [[INC73]], i32* [[I68]], align 4 -// CHECK5-NEXT: br label [[FOR_COND69]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK5: for.end74: -// CHECK5-NEXT: store i32 0, i32* [[I75]], align 4 -// CHECK5-NEXT: br label [[FOR_COND76:%.*]] -// CHECK5: for.cond76: -// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK5-NEXT: [[CMP77:%.*]] = icmp slt i32 [[TMP38]], 10 -// CHECK5-NEXT: br i1 [[CMP77]], label [[FOR_BODY78:%.*]], label [[FOR_END81:%.*]] -// CHECK5: for.body78: -// CHECK5-NEXT: br label [[FOR_INC79:%.*]] -// CHECK5: for.inc79: -// CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK5-NEXT: [[INC80:%.*]] = add nsw i32 [[TMP39]], 1 -// CHECK5-NEXT: store i32 [[INC80]], i32* [[I75]], align 4 -// CHECK5-NEXT: br label [[FOR_COND76]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK5: for.end81: -// CHECK5-NEXT: [[TMP40:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP40]], [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK5-NEXT: [[TMP41:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP41]], [4 x %struct.S]** [[_TMP83]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I84]], align 4 -// CHECK5-NEXT: br label [[FOR_COND85:%.*]] -// CHECK5: for.cond85: -// CHECK5-NEXT: [[TMP42:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK5-NEXT: [[CMP86:%.*]] = icmp slt i32 [[TMP42]], 10 -// CHECK5-NEXT: br i1 [[CMP86]], label [[FOR_BODY87:%.*]], label [[FOR_END90:%.*]] -// CHECK5: for.body87: -// CHECK5-NEXT: br label [[FOR_INC88:%.*]] -// CHECK5: for.inc88: -// CHECK5-NEXT: [[TMP43:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK5-NEXT: [[INC89:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK5-NEXT: store i32 [[INC89]], i32* [[I84]], align 4 -// CHECK5-NEXT: br label [[FOR_COND85]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK5: for.end90: -// CHECK5-NEXT: [[TMP44:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP44]], [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK5-NEXT: [[TMP45:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP45]], [4 x %struct.S]** [[_TMP92]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I93]], align 4 -// CHECK5-NEXT: br label [[FOR_COND94:%.*]] -// CHECK5: for.cond94: -// CHECK5-NEXT: [[TMP46:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK5-NEXT: [[CMP95:%.*]] = icmp slt i32 [[TMP46]], 10 -// CHECK5-NEXT: br i1 [[CMP95]], label [[FOR_BODY96:%.*]], label [[FOR_END99:%.*]] -// CHECK5: for.body96: -// CHECK5-NEXT: br label [[FOR_INC97:%.*]] -// CHECK5: for.inc97: -// CHECK5-NEXT: [[TMP47:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK5-NEXT: [[INC98:%.*]] = add nsw i32 [[TMP47]], 1 -// CHECK5-NEXT: store i32 [[INC98]], i32* [[I93]], align 4 -// CHECK5-NEXT: br label [[FOR_COND94]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK5: for.end99: -// CHECK5-NEXT: [[TMP48:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP48]], [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK5-NEXT: [[TMP49:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP49]], [4 x %struct.S]** [[_TMP101]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I102]], align 4 -// CHECK5-NEXT: br label [[FOR_COND103:%.*]] -// CHECK5: for.cond103: -// CHECK5-NEXT: [[TMP50:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK5-NEXT: [[CMP104:%.*]] = icmp slt i32 [[TMP50]], 10 -// CHECK5-NEXT: br i1 [[CMP104]], label [[FOR_BODY105:%.*]], label [[FOR_END108:%.*]] -// CHECK5: for.body105: -// CHECK5-NEXT: br label [[FOR_INC106:%.*]] -// CHECK5: for.inc106: -// CHECK5-NEXT: [[TMP51:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK5-NEXT: [[INC107:%.*]] = add nsw i32 [[TMP51]], 1 -// CHECK5-NEXT: store i32 [[INC107]], i32* [[I102]], align 4 -// CHECK5-NEXT: br label [[FOR_COND103]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK5: for.end108: -// CHECK5-NEXT: [[TMP52:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP52]], [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK5-NEXT: [[TMP53:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK5-NEXT: store [4 x %struct.S]* [[TMP53]], [4 x %struct.S]** [[_TMP110]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I111]], align 4 -// CHECK5-NEXT: br label [[FOR_COND112:%.*]] -// CHECK5: for.cond112: -// CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK5-NEXT: [[CMP113:%.*]] = icmp slt i32 [[TMP54]], 10 -// CHECK5-NEXT: br i1 [[CMP113]], label [[FOR_BODY114:%.*]], label [[FOR_END117:%.*]] -// CHECK5: for.body114: -// CHECK5-NEXT: br label [[FOR_INC115:%.*]] -// CHECK5: for.inc115: -// CHECK5-NEXT: [[TMP55:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK5-NEXT: [[INC116:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK5-NEXT: store i32 [[INC116]], i32* [[I111]], align 4 -// CHECK5-NEXT: br label [[FOR_COND112]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK5: for.end117: -// CHECK5-NEXT: [[CALL118:%.*]] = call i32 @_Z5tmainIiLi42EET_v() -// CHECK5-NEXT: store i32 [[CALL118]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP56:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP56]]) -// CHECK5-NEXT: [[ARRAY_BEGIN119:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN119]], i64 5 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP57]], [[FOR_END117]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN119]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE120:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done120: -// CHECK5-NEXT: [[ARRAY_BEGIN121:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN121]], i64 40 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY122:%.*]] -// CHECK5: arraydestroy.body122: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST123:%.*]] = phi %struct.S* [ [[TMP58]], [[ARRAYDESTROY_DONE120]] ], [ [[ARRAYDESTROY_ELEMENT124:%.*]], [[ARRAYDESTROY_BODY122]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT124]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST123]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT124]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE125:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT124]], [[ARRAY_BEGIN121]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE125]], label [[ARRAYDESTROY_DONE126:%.*]], label [[ARRAYDESTROY_BODY122]] -// CHECK5: arraydestroy.done126: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAY_BEGIN127:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN127]], i64 4 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY128:%.*]] -// CHECK5: arraydestroy.body128: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST129:%.*]] = phi %struct.S* [ [[TMP59]], [[ARRAYDESTROY_DONE126]] ], [ [[ARRAYDESTROY_ELEMENT130:%.*]], [[ARRAYDESTROY_BODY128]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT130]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST129]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT130]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE131:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT130]], [[ARRAY_BEGIN127]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE131]], label [[ARRAYDESTROY_DONE132:%.*]], label [[ARRAYDESTROY_BODY128]] -// CHECK5: arraydestroy.done132: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP60]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP4:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP17:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP18:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 42 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP11]], %struct.S.0** [[_TMP4]], align 8 -// CHECK5-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP4]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[_TMP5]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7:%.*]] -// CHECK5: for.cond7: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK5-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END16:%.*]] -// CHECK5: for.body9: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM10]] -// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX11]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM12]] -// CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX13]] to i8* -// CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC14:%.*]] -// CHECK5: for.inc14: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK5-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[INC15]], i32* [[I6]], align 4 -// CHECK5-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK5: for.end16: -// CHECK5-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP21]], %struct.S.0** [[_TMP17]], align 8 -// CHECK5-NEXT: [[TMP22:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP17]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP22]], %struct.S.0** [[_TMP18]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20:%.*]] -// CHECK5: for.cond20: -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP23]], 2 -// CHECK5-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK5: for.body22: -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK5-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM23]] -// CHECK5-NEXT: store i32 [[TMP24]], i32* [[ARRAYIDX24]], align 4 -// CHECK5-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP18]], align 8 -// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK5-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM25]] -// CHECK5-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[ARRAYIDX26]] to i8* -// CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP26]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC27:%.*]] -// CHECK5: for.inc27: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK5-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK5: for.end29: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN30]], i64 42 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[FOR_END29]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN30]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done31: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN32]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY33:%.*]] -// CHECK5: arraydestroy.body33: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST34:%.*]] = phi %struct.S.0* [ [[TMP32]], [[ARRAYDESTROY_DONE31]] ], [ [[ARRAYDESTROY_ELEMENT35:%.*]], [[ARRAYDESTROY_BODY33]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT35]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST34]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT35]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE36:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT35]], [[ARRAY_BEGIN32]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE36]], label [[ARRAYDESTROY_DONE37:%.*]], label [[ARRAYDESTROY_BODY33]] -// CHECK5: arraydestroy.done37: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP33]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK5-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [4 x %struct.S], align 16 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[ARRS:%.*]] = alloca [10 x [4 x %struct.S]], align 16 -// CHECK6-NEXT: [[VAR2:%.*]] = alloca %struct.S**, align 8 -// CHECK6-NEXT: [[VVAR2:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK6-NEXT: [[VAR3:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[_TMP10:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I14:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I25:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I36:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I47:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I54:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I61:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I68:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I75:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP82:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP83:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I84:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP91:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP92:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I93:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP100:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP101:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I102:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP109:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[_TMP110:%.*]] = alloca [4 x %struct.S]*, align 8 -// CHECK6-NEXT: [[I111:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) -// CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 40 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call %struct.S** @_Z3foov() -// CHECK6-NEXT: store %struct.S** [[CALL]], %struct.S*** [[VAR2]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 5 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] -// CHECK6: arrayctor.loop5: -// CHECK6-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR6]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR6]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] -// CHECK6: arrayctor.cont9: -// CHECK6-NEXT: store [4 x %struct.S]* [[S_ARR]], [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[_TMP10]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP10]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM11]] -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[TMP6]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX13]], align 4 -// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: [[TMP13:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP13]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP14:%.*]] = mul nuw i64 10, [[TMP12]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP14]], align 16 -// CHECK6-NEXT: store i64 [[TMP12]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I14]], align 4 -// CHECK6-NEXT: br label [[FOR_COND15:%.*]] -// CHECK6: for.cond15: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK6-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP15]], 10 -// CHECK6-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END24:%.*]] -// CHECK6: for.body17: -// CHECK6-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP16]] -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK6-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX18]], i64 [[IDXPROM19]] -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4 -// CHECK6-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK6-NEXT: store i32 [[INC21]], i32* [[ARRAYIDX20]], align 4 -// CHECK6-NEXT: br label [[FOR_INC22:%.*]] -// CHECK6: for.inc22: -// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I14]], align 4 -// CHECK6-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK6-NEXT: store i32 [[INC23]], i32* [[I14]], align 4 -// CHECK6-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end24: -// CHECK6-NEXT: store i32 0, i32* [[I25]], align 4 -// CHECK6-NEXT: br label [[FOR_COND26:%.*]] -// CHECK6: for.cond26: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK6-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP20]], 10 -// CHECK6-NEXT: br i1 [[CMP27]], label [[FOR_BODY28:%.*]], label [[FOR_END35:%.*]] -// CHECK6: for.body28: -// CHECK6-NEXT: [[TMP21:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK6-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP21]] -// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK6-NEXT: [[IDXPROM30:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK6-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX29]], i64 [[IDXPROM30]] -// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX31]], align 4 -// CHECK6-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK6-NEXT: store i32 [[INC32]], i32* [[ARRAYIDX31]], align 4 -// CHECK6-NEXT: br label [[FOR_INC33:%.*]] -// CHECK6: for.inc33: -// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I25]], align 4 -// CHECK6-NEXT: [[INC34:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK6-NEXT: store i32 [[INC34]], i32* [[I25]], align 4 -// CHECK6-NEXT: br label [[FOR_COND26]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end35: -// CHECK6-NEXT: store i32 0, i32* [[I36]], align 4 -// CHECK6-NEXT: br label [[FOR_COND37:%.*]] -// CHECK6: for.cond37: -// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK6-NEXT: [[CMP38:%.*]] = icmp slt i32 [[TMP25]], 10 -// CHECK6-NEXT: br i1 [[CMP38]], label [[FOR_BODY39:%.*]], label [[FOR_END46:%.*]] -// CHECK6: for.body39: -// CHECK6-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP12]] -// CHECK6-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP26]] -// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK6-NEXT: [[IDXPROM41:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK6-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX40]], i64 [[IDXPROM41]] -// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX42]], align 4 -// CHECK6-NEXT: [[INC43:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK6-NEXT: store i32 [[INC43]], i32* [[ARRAYIDX42]], align 4 -// CHECK6-NEXT: br label [[FOR_INC44:%.*]] -// CHECK6: for.inc44: -// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[I36]], align 4 -// CHECK6-NEXT: [[INC45:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK6-NEXT: store i32 [[INC45]], i32* [[I36]], align 4 -// CHECK6-NEXT: br label [[FOR_COND37]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end46: -// CHECK6-NEXT: store i32 0, i32* [[I47]], align 4 -// CHECK6-NEXT: br label [[FOR_COND48:%.*]] -// CHECK6: for.cond48: -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK6-NEXT: [[CMP49:%.*]] = icmp slt i32 [[TMP30]], 10 -// CHECK6-NEXT: br i1 [[CMP49]], label [[FOR_BODY50:%.*]], label [[FOR_END53:%.*]] -// CHECK6: for.body50: -// CHECK6-NEXT: br label [[FOR_INC51:%.*]] -// CHECK6: for.inc51: -// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[I47]], align 4 -// CHECK6-NEXT: [[INC52:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK6-NEXT: store i32 [[INC52]], i32* [[I47]], align 4 -// CHECK6-NEXT: br label [[FOR_COND48]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK6: for.end53: -// CHECK6-NEXT: store i32 0, i32* [[I54]], align 4 -// CHECK6-NEXT: br label [[FOR_COND55:%.*]] -// CHECK6: for.cond55: -// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK6-NEXT: [[CMP56:%.*]] = icmp slt i32 [[TMP32]], 10 -// CHECK6-NEXT: br i1 [[CMP56]], label [[FOR_BODY57:%.*]], label [[FOR_END60:%.*]] -// CHECK6: for.body57: -// CHECK6-NEXT: br label [[FOR_INC58:%.*]] -// CHECK6: for.inc58: -// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[I54]], align 4 -// CHECK6-NEXT: [[INC59:%.*]] = add nsw i32 [[TMP33]], 1 -// CHECK6-NEXT: store i32 [[INC59]], i32* [[I54]], align 4 -// CHECK6-NEXT: br label [[FOR_COND55]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK6: for.end60: -// CHECK6-NEXT: store i32 0, i32* [[I61]], align 4 -// CHECK6-NEXT: br label [[FOR_COND62:%.*]] -// CHECK6: for.cond62: -// CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK6-NEXT: [[CMP63:%.*]] = icmp slt i32 [[TMP34]], 10 -// CHECK6-NEXT: br i1 [[CMP63]], label [[FOR_BODY64:%.*]], label [[FOR_END67:%.*]] -// CHECK6: for.body64: -// CHECK6-NEXT: br label [[FOR_INC65:%.*]] -// CHECK6: for.inc65: -// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[I61]], align 4 -// CHECK6-NEXT: [[INC66:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK6-NEXT: store i32 [[INC66]], i32* [[I61]], align 4 -// CHECK6-NEXT: br label [[FOR_COND62]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK6: for.end67: -// CHECK6-NEXT: store i32 0, i32* [[I68]], align 4 -// CHECK6-NEXT: br label [[FOR_COND69:%.*]] -// CHECK6: for.cond69: -// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK6-NEXT: [[CMP70:%.*]] = icmp slt i32 [[TMP36]], 10 -// CHECK6-NEXT: br i1 [[CMP70]], label [[FOR_BODY71:%.*]], label [[FOR_END74:%.*]] -// CHECK6: for.body71: -// CHECK6-NEXT: br label [[FOR_INC72:%.*]] -// CHECK6: for.inc72: -// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[I68]], align 4 -// CHECK6-NEXT: [[INC73:%.*]] = add nsw i32 [[TMP37]], 1 -// CHECK6-NEXT: store i32 [[INC73]], i32* [[I68]], align 4 -// CHECK6-NEXT: br label [[FOR_COND69]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK6: for.end74: -// CHECK6-NEXT: store i32 0, i32* [[I75]], align 4 -// CHECK6-NEXT: br label [[FOR_COND76:%.*]] -// CHECK6: for.cond76: -// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK6-NEXT: [[CMP77:%.*]] = icmp slt i32 [[TMP38]], 10 -// CHECK6-NEXT: br i1 [[CMP77]], label [[FOR_BODY78:%.*]], label [[FOR_END81:%.*]] -// CHECK6: for.body78: -// CHECK6-NEXT: br label [[FOR_INC79:%.*]] -// CHECK6: for.inc79: -// CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[I75]], align 4 -// CHECK6-NEXT: [[INC80:%.*]] = add nsw i32 [[TMP39]], 1 -// CHECK6-NEXT: store i32 [[INC80]], i32* [[I75]], align 4 -// CHECK6-NEXT: br label [[FOR_COND76]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK6: for.end81: -// CHECK6-NEXT: [[TMP40:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP40]], [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK6-NEXT: [[TMP41:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP82]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP41]], [4 x %struct.S]** [[_TMP83]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I84]], align 4 -// CHECK6-NEXT: br label [[FOR_COND85:%.*]] -// CHECK6: for.cond85: -// CHECK6-NEXT: [[TMP42:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK6-NEXT: [[CMP86:%.*]] = icmp slt i32 [[TMP42]], 10 -// CHECK6-NEXT: br i1 [[CMP86]], label [[FOR_BODY87:%.*]], label [[FOR_END90:%.*]] -// CHECK6: for.body87: -// CHECK6-NEXT: br label [[FOR_INC88:%.*]] -// CHECK6: for.inc88: -// CHECK6-NEXT: [[TMP43:%.*]] = load i32, i32* [[I84]], align 4 -// CHECK6-NEXT: [[INC89:%.*]] = add nsw i32 [[TMP43]], 1 -// CHECK6-NEXT: store i32 [[INC89]], i32* [[I84]], align 4 -// CHECK6-NEXT: br label [[FOR_COND85]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK6: for.end90: -// CHECK6-NEXT: [[TMP44:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP44]], [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK6-NEXT: [[TMP45:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP91]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP45]], [4 x %struct.S]** [[_TMP92]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I93]], align 4 -// CHECK6-NEXT: br label [[FOR_COND94:%.*]] -// CHECK6: for.cond94: -// CHECK6-NEXT: [[TMP46:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK6-NEXT: [[CMP95:%.*]] = icmp slt i32 [[TMP46]], 10 -// CHECK6-NEXT: br i1 [[CMP95]], label [[FOR_BODY96:%.*]], label [[FOR_END99:%.*]] -// CHECK6: for.body96: -// CHECK6-NEXT: br label [[FOR_INC97:%.*]] -// CHECK6: for.inc97: -// CHECK6-NEXT: [[TMP47:%.*]] = load i32, i32* [[I93]], align 4 -// CHECK6-NEXT: [[INC98:%.*]] = add nsw i32 [[TMP47]], 1 -// CHECK6-NEXT: store i32 [[INC98]], i32* [[I93]], align 4 -// CHECK6-NEXT: br label [[FOR_COND94]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK6: for.end99: -// CHECK6-NEXT: [[TMP48:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP48]], [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK6-NEXT: [[TMP49:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP100]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP49]], [4 x %struct.S]** [[_TMP101]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I102]], align 4 -// CHECK6-NEXT: br label [[FOR_COND103:%.*]] -// CHECK6: for.cond103: -// CHECK6-NEXT: [[TMP50:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK6-NEXT: [[CMP104:%.*]] = icmp slt i32 [[TMP50]], 10 -// CHECK6-NEXT: br i1 [[CMP104]], label [[FOR_BODY105:%.*]], label [[FOR_END108:%.*]] -// CHECK6: for.body105: -// CHECK6-NEXT: br label [[FOR_INC106:%.*]] -// CHECK6: for.inc106: -// CHECK6-NEXT: [[TMP51:%.*]] = load i32, i32* [[I102]], align 4 -// CHECK6-NEXT: [[INC107:%.*]] = add nsw i32 [[TMP51]], 1 -// CHECK6-NEXT: store i32 [[INC107]], i32* [[I102]], align 4 -// CHECK6-NEXT: br label [[FOR_COND103]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK6: for.end108: -// CHECK6-NEXT: [[TMP52:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP52]], [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK6-NEXT: [[TMP53:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[_TMP109]], align 8 -// CHECK6-NEXT: store [4 x %struct.S]* [[TMP53]], [4 x %struct.S]** [[_TMP110]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I111]], align 4 -// CHECK6-NEXT: br label [[FOR_COND112:%.*]] -// CHECK6: for.cond112: -// CHECK6-NEXT: [[TMP54:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK6-NEXT: [[CMP113:%.*]] = icmp slt i32 [[TMP54]], 10 -// CHECK6-NEXT: br i1 [[CMP113]], label [[FOR_BODY114:%.*]], label [[FOR_END117:%.*]] -// CHECK6: for.body114: -// CHECK6-NEXT: br label [[FOR_INC115:%.*]] -// CHECK6: for.inc115: -// CHECK6-NEXT: [[TMP55:%.*]] = load i32, i32* [[I111]], align 4 -// CHECK6-NEXT: [[INC116:%.*]] = add nsw i32 [[TMP55]], 1 -// CHECK6-NEXT: store i32 [[INC116]], i32* [[I111]], align 4 -// CHECK6-NEXT: br label [[FOR_COND112]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK6: for.end117: -// CHECK6-NEXT: [[CALL118:%.*]] = call i32 @_Z5tmainIiLi42EET_v() -// CHECK6-NEXT: store i32 [[CALL118]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP56:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP56]]) -// CHECK6-NEXT: [[ARRAY_BEGIN119:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN119]], i64 5 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP57]], [[FOR_END117]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN119]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE120:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done120: -// CHECK6-NEXT: [[ARRAY_BEGIN121:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 -// CHECK6-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN121]], i64 40 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY122:%.*]] -// CHECK6: arraydestroy.body122: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST123:%.*]] = phi %struct.S* [ [[TMP58]], [[ARRAYDESTROY_DONE120]] ], [ [[ARRAYDESTROY_ELEMENT124:%.*]], [[ARRAYDESTROY_BODY122]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT124]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST123]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT124]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE125:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT124]], [[ARRAY_BEGIN121]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE125]], label [[ARRAYDESTROY_DONE126:%.*]], label [[ARRAYDESTROY_BODY122]] -// CHECK6: arraydestroy.done126: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAY_BEGIN127:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN127]], i64 4 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY128:%.*]] -// CHECK6: arraydestroy.body128: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST129:%.*]] = phi %struct.S* [ [[TMP59]], [[ARRAYDESTROY_DONE126]] ], [ [[ARRAYDESTROY_ELEMENT130:%.*]], [[ARRAYDESTROY_BODY128]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT130]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST129]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT130]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE131:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT130]], [[ARRAY_BEGIN127]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE131]], label [[ARRAYDESTROY_DONE132:%.*]], label [[ARRAYDESTROY_BODY128]] -// CHECK6: arraydestroy.done132: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP60:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP60]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP4:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP17:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP18:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 42 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP11]], %struct.S.0** [[_TMP4]], align 8 -// CHECK6-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP4]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[_TMP5]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7:%.*]] -// CHECK6: for.cond7: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP13]], 2 -// CHECK6-NEXT: br i1 [[CMP8]], label [[FOR_BODY9:%.*]], label [[FOR_END16:%.*]] -// CHECK6: for.body9: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM10]] -// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX11]], align 4 -// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM12]] -// CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX13]] to i8* -// CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC14:%.*]] -// CHECK6: for.inc14: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK6-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK6-NEXT: store i32 [[INC15]], i32* [[I6]], align 4 -// CHECK6-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK6: for.end16: -// CHECK6-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP21]], %struct.S.0** [[_TMP17]], align 8 -// CHECK6-NEXT: [[TMP22:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP17]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP22]], %struct.S.0** [[_TMP18]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20:%.*]] -// CHECK6: for.cond20: -// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP23]], 2 -// CHECK6-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK6: for.body22: -// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK6-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM23]] -// CHECK6-NEXT: store i32 [[TMP24]], i32* [[ARRAYIDX24]], align 4 -// CHECK6-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP18]], align 8 -// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK6-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM25]] -// CHECK6-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[ARRAYIDX26]] to i8* -// CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[TMP26]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC27:%.*]] -// CHECK6: for.inc27: -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK6-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK6: for.end29: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN30]], i64 42 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[FOR_END29]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN30]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done31: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN32]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY33:%.*]] -// CHECK6: arraydestroy.body33: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST34:%.*]] = phi %struct.S.0* [ [[TMP32]], [[ARRAYDESTROY_DONE31]] ], [ [[ARRAYDESTROY_ELEMENT35:%.*]], [[ARRAYDESTROY_BODY33]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT35]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST34]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT35]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE36:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT35]], [[ARRAY_BEGIN32]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE36]], label [[ARRAYDESTROY_DONE37:%.*]], label [[ARRAYDESTROY_BODY33]] -// CHECK6: arraydestroy.done37: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP33]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK6-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** @g1, align 8 -// CHECK8-NEXT: store double* [[TMP0]], double** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store double 1.000000e+00, double* @g, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store volatile double 1.000000e+00, double* [[TMP2]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP3:%.*]] = load volatile double, double* @g, align 8 -// CHECK8-NEXT: store volatile double [[TMP3]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP4]], double** [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP5]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP8:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP8]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP9]](i8* [[TMP7]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: store double 2.000000e+00, double* [[TMP0]], align 8 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_reduction_task_codegen.cpp b/clang/test/OpenMP/for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1091,62 +1091,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG23]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG25:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG27:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG31:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG31]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG31]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG32:![0-9]+]], !llvm.loop [[LOOP33:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG36]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp --- a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1393,227 +1393,4 @@ // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP10]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK4-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK4: arrayctor.loop: -// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK4: arraydestroy.body: -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK4: arraydestroy.done3: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP10]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/openmp_win_codegen.cpp b/clang/test/OpenMP/openmp_win_codegen.cpp --- a/clang/test/OpenMP/openmp_win_codegen.cpp +++ b/clang/test/OpenMP/openmp_win_codegen.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-windows-msvc18.0.0 -std=c++11 -fms-compatibility-version=18 -fms-extensions -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-windows-msvc18.0.0 -std=c++11 -fms-compatibility-version=18 -fms-extensions -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-windows-msvc18.0.0 -std=c++11 -fms-compatibility-version=18 -fms-extensions -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics @@ -155,32 +155,4 @@ // CHECK1-NEXT: store i32 [[TMP12]], i32* [[TMP8]], align 4 // CHECK1-NEXT: ret void // -// -// CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @"?main@Test@@SAXXZ"() -// CHECK2-NEXT: invoke void @"?foo@@YAXXZ"() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[CATCH_DISPATCH:%.*]] -// CHECK2: catch.dispatch: -// CHECK2-NEXT: [[TMP0:%.*]] = catchswitch within none [label %catch] unwind label [[TERMINATE:%.*]] -// CHECK2: catch: -// CHECK2-NEXT: [[TMP1:%.*]] = catchpad within [[TMP0]] [%rtti.TypeDescriptor2* @"??_R0H@8", i32 0, i32* %t] -// CHECK2-NEXT: invoke void @"?bar@@YAXXZ"() [ "funclet"(token [[TMP1]]) ] -// CHECK2-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE]] -// CHECK2: invoke.cont1: -// CHECK2-NEXT: catchret from [[TMP1]] to label [[CATCHRET_DEST:%.*]] -// CHECK2: catchret.dest: -// CHECK2-NEXT: br label [[TRY_CONT:%.*]] -// CHECK2: try.cont: -// CHECK2-NEXT: ret i32 0 -// CHECK2: invoke.cont: -// CHECK2-NEXT: br label [[TRY_CONT]] -// CHECK2: terminate: -// CHECK2-NEXT: [[TMP2:%.*]] = cleanuppad within none [] -// CHECK2-NEXT: call void @"?terminate@@YAXXZ"() #[[ATTR3:[0-9]+]] [ "funclet"(token [[TMP2]]) ] -// CHECK2-NEXT: unreachable -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_codegen.cpp b/clang/test/OpenMP/parallel_codegen.cpp --- a/clang/test/OpenMP/parallel_codegen.cpp +++ b/clang/test/OpenMP/parallel_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -DIRBUILDER -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -gno-column-info -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -958,493 +958,4 @@ // CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71:![0-9]+]] // CHECK4-NEXT: ret void, !dbg [[DBG71]] // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8 -// CHECK5-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 -// CHECK5-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK5: invoke.cont5: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK5-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK5-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK5: invoke.cont8: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4 -// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK5-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]) -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK5-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK5-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1 -// CHECK5-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 -// CHECK5-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]] -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]] -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0 -// CHECK5-NEXT: ret i32 0 -// CHECK5: terminate.lpad: -// CHECK5-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: catch i8* null -// CHECK5-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR4]] -// CHECK5-NEXT: unreachable -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK5-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK5-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18:![0-9]+]] -// CHECK6-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META19:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]] -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]] -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG22:![0-9]+]] -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG22]] -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG22]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG22]] -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG22]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG30:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG31:![0-9]+]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG31]] -// CHECK6-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG33:![0-9]+]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG34:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG35:![0-9]+]] -// CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[GLOBAL]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39:![0-9]+]] -// CHECK6-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG40:![0-9]+]] -// CHECK6-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8, !dbg [[DBG40]] -// CHECK6-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG40]] -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG40]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR1]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA3]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG43:![0-9]+]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4, !dbg [[DBG43]] -// CHECK6-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]] -// CHECK6: invoke.cont5: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4, !dbg [[DBG46:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG47:![0-9]+]] -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8, !dbg [[DBG49:![0-9]+]] -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]), !dbg [[DBG49]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG50:![0-9]+]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !dbg [[DBG50]] -// CHECK6-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK6-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG53:![0-9]+]] -// CHECK6: invoke.cont8: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG54:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG55:![0-9]+]] -// CHECK6-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4, !dbg [[DBG56:![0-9]+]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8, !dbg [[DBG57:![0-9]+]] -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]), !dbg [[DBG58:![0-9]+]] -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG59:![0-9]+]] -// CHECK6-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG60:![0-9]+]] -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG60]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG60]] -// CHECK6-NEXT: ret i32 [[TMP13]], !dbg [[DBG60]] -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null, !dbg [[DBG33]] -// CHECK6-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG33]] -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG33]] -// CHECK6-NEXT: unreachable, !dbg [[DBG33]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK6-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat !dbg [[DBG61:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] -// CHECK6-NEXT: ret void, !dbg [[DBG68:![0-9]+]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK6-NEXT: unreachable -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK6-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG69:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]] -// CHECK6-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG76:![0-9]+]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0, !dbg [[DBG76]] -// CHECK6-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8, !dbg [[DBG76]] -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0, !dbg [[DBG76]] -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1, !dbg [[DBG76]] -// CHECK6-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG77:![0-9]+]] -// CHECK6-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG78:![0-9]+]] -// CHECK6-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG81:![0-9]+]] -// CHECK6: invoke.cont: -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG89:![0-9]+]] -// CHECK6-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK6-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]], !dbg [[DBG90]] -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]], !dbg [[DBG90]] -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0, !dbg [[DBG90]] -// CHECK6-NEXT: ret i32 0, !dbg [[DBG91:![0-9]+]] -// CHECK6: terminate.lpad: -// CHECK6-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK6-NEXT: catch i8* null, !dbg [[DBG81]] -// CHECK6-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0, !dbg [[DBG81]] -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR5]], !dbg [[DBG81]] -// CHECK6-NEXT: unreachable, !dbg [[DBG81]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK6-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat !dbg [[DBG92:![0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK6-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK6-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]] -// CHECK6-NEXT: ret void, !dbg [[DBG97:![0-9]+]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8 -// CHECK7-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1 -// CHECK7-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK7-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont8: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4 -// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 -// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]) -// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR4:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK7-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK7-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1 -// CHECK7-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 -// CHECK7-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]] -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]] -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0 -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR4]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK7-SAME: (i8** [[ARGC:%.*]]) #[[ATTR2]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK7-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK2:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18:![0-9]+]] -// CHECK8-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META19:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]] -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]] -// CHECK8-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG22:![0-9]+]] -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG22]] -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG22]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG22]] -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG22]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG30:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG31:![0-9]+]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG31]] -// CHECK8-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG33:![0-9]+]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG34:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG35:![0-9]+]] -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[GLOBAL]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39:![0-9]+]] -// CHECK8-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG40:![0-9]+]] -// CHECK8-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK2]], align 8, !dbg [[DBG40]] -// CHECK8-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG40]] -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG40]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR1]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA3]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG39]] -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG43:![0-9]+]] -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4, !dbg [[DBG43]] -// CHECK8-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP6]]) -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[GLOBAL]], align 4, !dbg [[DBG46:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA3]], i64 1, !dbg [[DBG47:![0-9]+]] -// CHECK8-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX6]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK2]], align 8, !dbg [[DBG49:![0-9]+]] -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]), !dbg [[DBG49]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG50:![0-9]+]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX7]], align 4, !dbg [[DBG50]] -// CHECK8-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP9]]) -// CHECK8-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG53:![0-9]+]] -// CHECK8: invoke.cont8: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG54:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG55:![0-9]+]] -// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX9]], align 4, !dbg [[DBG56:![0-9]+]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8, !dbg [[DBG57:![0-9]+]] -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP11]]), !dbg [[DBG58:![0-9]+]] -// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG59:![0-9]+]] -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG60:![0-9]+]] -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG60]] -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG60]] -// CHECK8-NEXT: ret i32 [[TMP13]], !dbg [[DBG60]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null, !dbg [[DBG33]] -// CHECK8-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG33]] -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG33]] -// CHECK8-NEXT: unreachable, !dbg [[DBG33]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK8-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat !dbg [[DBG61:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]] -// CHECK8-NEXT: ret void, !dbg [[DBG68:![0-9]+]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK8-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG69:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: [[VAR:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]] -// CHECK8-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG76:![0-9]+]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP0]], i64 0, !dbg [[DBG76]] -// CHECK8-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8, !dbg [[DBG76]] -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 0, !dbg [[DBG76]] -// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1, !dbg [[DBG76]] -// CHECK8-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG77:![0-9]+]] -// CHECK8-NEXT: [[TMP4:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG78:![0-9]+]] -// CHECK8-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP4]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG81:![0-9]+]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG89:![0-9]+]] -// CHECK8-NEXT: [[TMP5:%.*]] = load double*, double** [[VAR]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i64 0, [[TMP3]], !dbg [[DBG90]] -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 [[TMP6]], !dbg [[DBG90]] -// CHECK8-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX2]], i64 0, !dbg [[DBG90]] -// CHECK8-NEXT: ret i32 0, !dbg [[DBG91:![0-9]+]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP7:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null, !dbg [[DBG81]] -// CHECK8-NEXT: [[TMP8:%.*]] = extractvalue { i8*, i32 } [[TMP7]], 0, !dbg [[DBG81]] -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP8]]) #[[ATTR5]], !dbg [[DBG81]] -// CHECK8-NEXT: unreachable, !dbg [[DBG81]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK8-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat !dbg [[DBG92:![0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK8-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK8-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]] -// CHECK8-NEXT: ret void, !dbg [[DBG97:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_copyin_codegen.cpp b/clang/test/OpenMP/parallel_copyin_codegen.cpp --- a/clang/test/OpenMP/parallel_copyin_codegen.cpp +++ b/clang/test/OpenMP/parallel_copyin_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s @@ -21,12 +21,12 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 // RUN: %clang_cc1 -verify -fopenmp -x c++ -DNESTED -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #if !defined(ARRAY) && !defined(NESTED) #ifndef HEADER @@ -1662,718 +1662,6 @@ // CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 -// CHECK6-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK6: init.check: -// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK6: init: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK6-NEXT: br label [[INIT_END]] -// CHECK6: init.end: -// CHECK6-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK6-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK6: init.check2: -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK6: init4: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK6-NEXT: br label [[INIT_END5]] -// CHECK6: init.end5: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK6-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK6-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR2]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK6-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 -// CHECK6-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK6: init.check: -// CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK6: init: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK6-NEXT: br label [[INIT_END]] -// CHECK6: init.end: -// CHECK6-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK6-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK6-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK6: init.check2: -// CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK6-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK6-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK6: init4: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK6-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK6-NEXT: br label [[INIT_END5]] -// CHECK6: init.end5: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK6-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK6-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK7-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 -// CHECK7-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK7: init.check: -// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK7: init: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK7-NEXT: br label [[INIT_END]] -// CHECK7: init.end: -// CHECK7-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK7-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK7: init.check2: -// CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK7: init4: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK7-NEXT: br label [[INIT_END5]] -// CHECK7: init.end5: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK7-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK7-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK7-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR2]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK7-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 -// CHECK7-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK7: init.check: -// CHECK7-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK7: init: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK7-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK7-NEXT: br label [[INIT_END]] -// CHECK7: init.end: -// CHECK7-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK7-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK7-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK7: init.check2: -// CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK7-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK7: init4: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK7-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK7-NEXT: br label [[INIT_END5]] -// CHECK7: init.end5: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK7-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK7-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK9-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK9-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK9-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK9-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK9-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK9-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK9-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK9-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK9-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK9-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK9-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK9-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK9-NEXT: store volatile i32 2, i32* @g, align 128 -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z10array_funcv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8 -// CHECK10-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK10-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK10: init.check: -// CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]] -// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK10-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK10: init: -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]] -// CHECK10-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]] -// CHECK10-NEXT: br label [[INIT_END]] -// CHECK10: init.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK10-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// // CHECK11-LABEL: define {{[^@]+}}@main // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: @@ -3540,715 +2828,4 @@ // CHECK16: exit: // CHECK16-NEXT: ret void // -// -// CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK17-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK17-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK17: init.check: -// CHECK17-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK17: init: -// CHECK17-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK17-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK17-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END]] -// CHECK17: init.end: -// CHECK17-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK17: init.check2: -// CHECK17-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK17: init4: -// CHECK17-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END5]] -// CHECK17: init.end5: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK17-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK17-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK17-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK17-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK17-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK17-NEXT: ret i32 [[TMP8]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK17-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK17-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK17-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK17: arraydestroy.body: -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK17-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK17-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK17-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK17: arraydestroy.done1: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK17-SAME: () #[[ATTR2]] comdat { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK17-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK17-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK17-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK17-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK17: init.check: -// CHECK17-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK17: init: -// CHECK17-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK17-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK17-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END]] -// CHECK17: init.end: -// CHECK17-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK17-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK17-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK17: init.check2: -// CHECK17-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK17-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK17-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK17: init4: -// CHECK17-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK17-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK17-NEXT: br label [[INIT_END5]] -// CHECK17: init.end5: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK17-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK17-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK17-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK17-NEXT: ret i32 0 -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK17-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK17-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK17-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK17-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK17-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK17-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK17-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK17: arraydestroy.body: -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK17-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK17-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK17-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK17-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK17: arraydestroy.done1: -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK17-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK18-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] -// CHECK18-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK18: init.check: -// CHECK18-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK18: init: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK18-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END]] -// CHECK18: init.end: -// CHECK18-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK18: init.check2: -// CHECK18-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK18: init4: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) -// CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END5]] -// CHECK18: init.end5: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK18-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK18-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4 -// CHECK18-NEXT: [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK18-NEXT: store i32 [[CALL7]], i32* [[RETVAL]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP8]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret %struct.S* [[THIS1]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK18-SAME: () #[[ATTR2]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK18-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] -// CHECK18-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] -// CHECK18: init.check: -// CHECK18-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK18: init: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) -// CHECK18-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END]] -// CHECK18: init.end: -// CHECK18-NEXT: [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 -// CHECK18-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK18-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] -// CHECK18: init.check2: -// CHECK18-NEXT: [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK18-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK18-NEXT: br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]] -// CHECK18: init4: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) -// CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] -// CHECK18-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] -// CHECK18-NEXT: br label [[INIT_END5]] -// CHECK18: init.end5: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 -// CHECK18-NEXT: store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK18-NEXT: [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK18-NEXT: ret i32 0 -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK18-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK18-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK18-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret %struct.S.0* [[THIS1]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1 -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK19-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK20-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK20-NEXT: ret i32 0 -// -// -// CHECK20-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK20-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK20-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK20-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK20-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK20-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK20-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK20-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK20-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK20-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK20-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK20-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK20-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK20-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK20-NEXT: store volatile i32 2, i32* @g, align 128 -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z10array_funcv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8 -// CHECK21-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK21-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] -// CHECK21: init.check: -// CHECK21-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]] -// CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 -// CHECK21-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] -// CHECK21: init: -// CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK21: arrayctor.loop: -// CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]]) -// CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 -// CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) -// CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK21: arrayctor.cont: -// CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]] -// CHECK21-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]] -// CHECK21-NEXT: br label [[INIT_END]] -// CHECK21: init.end: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK21-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done1: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp --- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s @@ -17,15 +17,15 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER @@ -2157,1037 +2157,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK5-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK5-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK5-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK5-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK5-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK5-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 -// CHECK5-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK5-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK5-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2 -// CHECK5-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK6-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK6-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK6-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK6-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK6-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK6-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 -// CHECK6-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK6-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK6-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2 -// CHECK6-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK7-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK7-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK7-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK7-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK7-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK7-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 -// CHECK7-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK7-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP5]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP8]], align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP10]], align 4 -// CHECK7-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 4 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 4 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 4 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 4 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 4 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 -// CHECK7-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 4 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 -// CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, align 128 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 1, i32* @g, align 128 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 8 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 4 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 16 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>*, align 4 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>** [[BLOCK_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C7:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 4 -// CHECK8-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK8-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK8-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK8-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK8-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK8-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 -// CHECK8-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 4 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 -// CHECK8-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED12:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED12]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED13:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP10]], align 4 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED13]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 4 -// CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>** [[BLOCK_ADDR]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 4 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 4 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 4 -// CHECK8-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 -// CHECK8-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 4 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 4 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -5160,1037 +4129,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK13-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK13-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK13-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK13-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK13-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK13-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK13-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK13-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK13-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK13-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK13-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK13-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK13-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK13-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK13-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK13-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK13-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 8 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 -// CHECK13-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK13-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK13-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK13-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK14-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK14-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK14-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK14-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK14-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK14-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK14-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK14-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK14-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK14-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK14-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK14-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK14-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK14-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK14-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK14-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK14-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 -// CHECK14-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP11]], align 8 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 -// CHECK14-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK14-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK14-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK15-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK15-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK15-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK15-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK15-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK15-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK15-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK15-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK15-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK15-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK15-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK15-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK15-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK15-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK15-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK15-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP5]], align 8 -// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK15-NEXT: store i32* [[B4]], i32** [[TMP8]], align 8 -// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK15-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 -// CHECK15-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK15-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK15-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK15-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK15-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK15-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 -// CHECK15-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 -// CHECK15-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 -// CHECK15-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK16-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK16-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 1, i32* @g, align 128 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 32 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK16-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP11:%.*]] = alloca [4 x i32]*, align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK16-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK16-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK16-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK16-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK16-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK16-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK16-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK16-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK16-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 -// CHECK16-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK16-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK16-NEXT: store i32* [[TMP3]], i32** [[_TMP10]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 -// CHECK16-NEXT: store [4 x i32]* [[TMP4]], [4 x i32]** [[_TMP11]], align 8 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED12:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED12]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED13:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK16-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED13]], align 8 -// CHECK16-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK16-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP12]](i8* [[TMP10]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK16-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK16-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 -// CHECK16-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK16-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 -// CHECK16-NEXT: ret void -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -6384,95 +4322,4 @@ // CHECK17-NEXT: call void @__kmpc_free(i32 [[TMP12]], i8* [[TMP22]], i8* inttoptr (i64 8 to i8*)) // CHECK17-NEXT: ret void // -// -// CHECK18-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 -// CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP11:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 [[TMP10]], x86_fp80* [[TMP11]]) -// CHECK18-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 -// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK18-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double -// CHECK18-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK18-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK18-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK18-NEXT: [[TMP12:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 -// CHECK18-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK18-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP12]], i64 [[IDXPROM7]] -// CHECK18-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX8]], align 16 -// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK18-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_for_codegen.cpp b/clang/test/OpenMP/parallel_for_codegen.cpp --- a/clang/test/OpenMP/parallel_for_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_codegen.cpp @@ -11,19 +11,19 @@ // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifndef HEADER #define HEADER @@ -6909,1991 +6909,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z17with_var_schedulev -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store double 5.000000e+00, double* [[A]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 -// CHECK7-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 -// CHECK7-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i64 1, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double -// CHECK7-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 -// CHECK7-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] -// CHECK7-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 -// CHECK7-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK7-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK7-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[Y]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK7-NEXT: store i8 [[CONV]], i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 11, i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] -// CHECK7-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK7-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] -// CHECK7-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 -// CHECK7-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end13: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK7-NEXT: store i8 48, i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 -10, i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND1:%.*]] -// CHECK7: for.cond1: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK7-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body3: -// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] -// CHECK7-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] -// CHECK7-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] -// CHECK7-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[X]], align 4 -// CHECK7-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC11:%.*]] -// CHECK7: for.inc11: -// CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 -// CHECK7-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 -// CHECK7-NEXT: store i8 [[INC12]], i8* [[I]], align 1 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK7: for.end13: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3foov -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_Z8mayThrowv() -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK7-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 -// CHECK7-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK7-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] -// CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float -// CHECK7-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] -// CHECK7-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] -// CHECK7-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 -// CHECK7-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK7-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z17with_var_schedulev -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store double 5.000000e+00, double* [[A]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 -// CHECK8-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i64 1, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double -// CHECK8-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 -// CHECK8-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] -// CHECK8-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 -// CHECK8-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK8-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK8-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[Y]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK8-NEXT: store i8 [[CONV]], i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 11, i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] -// CHECK8-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 -// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK8-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] -// CHECK8-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 -// CHECK8-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end13: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK8-NEXT: store i8 48, i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 -10, i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND1:%.*]] -// CHECK8: for.cond1: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK8-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body3: -// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] -// CHECK8-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] -// CHECK8-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] -// CHECK8-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[X]], align 4 -// CHECK8-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC11:%.*]] -// CHECK8: for.inc11: -// CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 -// CHECK8-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 -// CHECK8-NEXT: store i8 [[INC12]], i8* [[I]], align 1 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK8: for.end13: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3foov -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z8mayThrowv() -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK8-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 -// CHECK8-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK8-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] -// CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float -// CHECK8-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] -// CHECK8-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] -// CHECK8-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 -// CHECK8-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK8-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK8-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z17with_var_schedulev -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG9:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG10]] -// CHECK9-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11:![0-9]+]] -// CHECK9-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG12:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG13:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG14:![0-9]+]] -// CHECK9-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double, !dbg [[DBG14]] -// CHECK9-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8, !dbg [[DBG15:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]], !dbg [[DBG16:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]], !dbg [[DBG17:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG18:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG19:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG20:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1, !dbg [[DBG20]] -// CHECK9-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG20]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG18]], !llvm.loop [[LOOP21:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG23:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG24:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 33, i32* [[I]], align 4, !dbg [[DBG25:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG26:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000, !dbg [[DBG28:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG31:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64, !dbg [[DBG30]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG30]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG30]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG32:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG33:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64, !dbg [[DBG32]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG32]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG32]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG34:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG35:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG35]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG35]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG35]] -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG37:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG38:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG39:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG38]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG38]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG40:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG41:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG42:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7, !dbg [[DBG42]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG42]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG29]], !llvm.loop [[LOOP43:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG44:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG45:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 32000000, i32* [[I]], align 4, !dbg [[DBG46:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG48:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33, !dbg [[DBG49:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG50:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG51:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG52:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64, !dbg [[DBG51]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG51]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG51]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG54:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64, !dbg [[DBG53]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG53]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG53]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG55:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG56:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG57:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG56]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG56]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG56]] -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG58:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG59:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG60:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG59]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG59]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG61:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG62:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG63:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7, !dbg [[DBG63]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG63]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG50]], !llvm.loop [[LOOP64:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG65:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG66:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 131071, i32* [[I]], align 4, !dbg [[DBG67:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG68:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG69:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647, !dbg [[DBG70:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG71:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG72:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG73:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64, !dbg [[DBG72]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG72]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG72]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG74:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG75:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64, !dbg [[DBG74]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG74]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG74]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG76:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG77:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG78:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64, !dbg [[DBG77]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG77]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG77]] -// CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG79:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG80:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG81:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64, !dbg [[DBG80]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG80]] -// CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG82:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG83:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG84:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127, !dbg [[DBG84]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG84]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG71]], !llvm.loop [[LOOP85:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG86:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG87:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i64 131071, i64* [[I]], align 8, !dbg [[DBG88:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG89:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647, !dbg [[DBG91:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG92:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG93:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG94:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]], !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG93]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG95:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG96:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]], !dbg [[DBG95]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !dbg [[DBG95]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG97:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG98:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG99:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]], !dbg [[DBG98]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG98]] -// CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG100:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG101:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG102:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]], !dbg [[DBG101]] -// CHECK9-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !dbg [[DBG103:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG104:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG105:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127, !dbg [[DBG105]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !dbg [[DBG105]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP106:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG107:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i64 131071, i64* [[I]], align 8, !dbg [[DBG109:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG110:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG111:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647, !dbg [[DBG112:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG113:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG114:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG115:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]], !dbg [[DBG114]] -// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG114]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG116:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG117:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]], !dbg [[DBG116]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !dbg [[DBG116]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG118:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG119:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG120:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]], !dbg [[DBG119]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG119]] -// CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG121:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG122:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG123:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]], !dbg [[DBG122]] -// CHECK9-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !dbg [[DBG124:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG125:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG126:![0-9]+]] -// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127, !dbg [[DBG126]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !dbg [[DBG126]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG113]], !llvm.loop [[LOOP127:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret void, !dbg [[DBG128:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG129:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG130:![0-9]+]] -// CHECK9-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG131:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4, !dbg [[DBG132:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8, !dbg [[DBG132]] -// CHECK9-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG133:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG134:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG135:![0-9]+]] -// CHECK9-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG135]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57, !dbg [[DBG136:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]], !dbg [[DBG137:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG138:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND2:%.*]], !dbg [[DBG139:![0-9]+]] -// CHECK9: for.cond2: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG140:![0-9]+]] -// CHECK9-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0, !dbg [[DBG141:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]], !dbg [[DBG142:![0-9]+]] -// CHECK9: for.body4: -// CHECK9-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG143:![0-9]+]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG144:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG143]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]], !dbg [[DBG143]] -// CHECK9-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG143]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG145:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG146:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64, !dbg [[DBG145]] -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]], !dbg [[DBG145]] -// CHECK9-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG145]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]], !dbg [[DBG147:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG148:![0-9]+]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG149:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64, !dbg [[DBG148]] -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]], !dbg [[DBG148]] -// CHECK9-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4, !dbg [[DBG148]] -// CHECK9-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]], !dbg [[DBG150:![0-9]+]] -// CHECK9-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG151:![0-9]+]] -// CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG152:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64, !dbg [[DBG151]] -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]], !dbg [[DBG151]] -// CHECK9-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4, !dbg [[DBG153:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG154:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG155:![0-9]+]] -// CHECK9-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1, !dbg [[DBG155]] -// CHECK9-NEXT: store i32 [[DEC]], i32* [[X]], align 4, !dbg [[DBG155]] -// CHECK9-NEXT: br label [[FOR_COND2]], !dbg [[DBG142]], !llvm.loop [[LOOP156:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: br label [[FOR_INC12:%.*]], !dbg [[DBG154]] -// CHECK9: for.inc12: -// CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG157:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1, !dbg [[DBG157]] -// CHECK9-NEXT: store i8 [[INC]], i8* [[I]], align 1, !dbg [[DBG157]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG137]], !llvm.loop [[LOOP158:![0-9]+]] -// CHECK9: for.end13: -// CHECK9-NEXT: ret void, !dbg [[DBG159:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG160:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG161:![0-9]+]] -// CHECK9-NEXT: store i8 48, i8* [[I]], align 1, !dbg [[DBG162:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG163:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG164:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32, !dbg [[DBG164]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57, !dbg [[DBG165:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]], !dbg [[DBG166:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: store i32 -10, i32* [[X]], align 4, !dbg [[DBG167:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND1:%.*]], !dbg [[DBG168:![0-9]+]] -// CHECK9: for.cond1: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG169:![0-9]+]] -// CHECK9-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10, !dbg [[DBG170:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]], !dbg [[DBG171:![0-9]+]] -// CHECK9: for.body3: -// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG172:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG173:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64, !dbg [[DBG172]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]], !dbg [[DBG172]] -// CHECK9-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG172]] -// CHECK9-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG175:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64, !dbg [[DBG174]] -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]], !dbg [[DBG174]] -// CHECK9-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !dbg [[DBG174]] -// CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]], !dbg [[DBG176:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG177:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG178:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64, !dbg [[DBG177]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]], !dbg [[DBG177]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG177]] -// CHECK9-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]], !dbg [[DBG179:![0-9]+]] -// CHECK9-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG180:![0-9]+]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG181:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64, !dbg [[DBG180]] -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]], !dbg [[DBG180]] -// CHECK9-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG182:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG183:![0-9]+]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG184:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1, !dbg [[DBG184]] -// CHECK9-NEXT: store i32 [[INC]], i32* [[X]], align 4, !dbg [[DBG184]] -// CHECK9-NEXT: br label [[FOR_COND1]], !dbg [[DBG171]], !llvm.loop [[LOOP185:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: br label [[FOR_INC11:%.*]], !dbg [[DBG183]] -// CHECK9: for.inc11: -// CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG186:![0-9]+]] -// CHECK9-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1, !dbg [[DBG186]] -// CHECK9-NEXT: store i8 [[INC12]], i8* [[I]], align 1, !dbg [[DBG186]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG166]], !llvm.loop [[LOOP187:![0-9]+]] -// CHECK9: for.end13: -// CHECK9-NEXT: ret void, !dbg [[DBG188:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z3foov -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] !dbg [[DBG189:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG190:![0-9]+]] -// CHECK9-NEXT: ret i32 0, !dbg [[DBG191:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK9-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG192:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG193:![0-9]+]] -// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG194:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG194]] -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG194]] -// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG194]] -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG194]] -// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG195:![0-9]+]] -// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8, !dbg [[DBG195]] -// CHECK9-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG195]] -// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG195]] -// CHECK9-NEXT: store i32 131071, i32* [[I]], align 4, !dbg [[DBG196:![0-9]+]] -// CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG197:![0-9]+]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG198:![0-9]+]] -// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647, !dbg [[DBG199:![0-9]+]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG200:![0-9]+]] -// CHECK9: for.body: -// CHECK9-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG201:![0-9]+]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG201]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG202:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64, !dbg [[DBG203:![0-9]+]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]], !dbg [[DBG203]] -// CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG203]] -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]], !dbg [[DBG204:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float, !dbg [[DBG205]] -// CHECK9-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]], !dbg [[DBG206:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG207:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG208:![0-9]+]] -// CHECK9-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64, !dbg [[DBG207]] -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]], !dbg [[DBG207]] -// CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG209:![0-9]+]] -// CHECK9-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]], !dbg [[DBG209]] -// CHECK9-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG209]] -// CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG207]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG210:![0-9]+]] -// CHECK9-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127, !dbg [[DBG210]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[I]], align 4, !dbg [[DBG210]] -// CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG200]], !llvm.loop [[LOOP211:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8, !dbg [[DBG205]] -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG205]] -// CHECK9-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG212:![0-9]+]] -// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]), !dbg [[DBG212]] -// CHECK9-NEXT: ret void, !dbg [[DBG212]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG201]] -// CHECK9-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG201]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG201]] -// CHECK9-NEXT: unreachable, !dbg [[DBG201]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK9-NEXT: unreachable -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z17with_var_schedulev -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: [[A1:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store double 5.000000e+00, double* [[A]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 -// CHECK10-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 -// CHECK10-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK10-NEXT: store i64 1, i64* [[I]], align 8 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double -// CHECK10-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] -// CHECK10-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 -// CHECK10-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 32000000, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] -// CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK10-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i64 131071, i64* [[I]], align 8 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] -// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 -// CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] -// CHECK10-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 -// CHECK10-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 -// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[Y:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[Y]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 -// CHECK10-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 -// CHECK10-NEXT: store i8 [[CONV]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: store i32 11, i32* [[X]], align 4 -// CHECK10-NEXT: br label [[FOR_COND2:%.*]] -// CHECK10: for.cond2: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 -// CHECK10-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 -// CHECK10-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body4: -// CHECK10-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] -// CHECK10-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] -// CHECK10-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] -// CHECK10-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] -// CHECK10-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] -// CHECK10-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 -// CHECK10-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 -// CHECK10-NEXT: store i32 [[DEC]], i32* [[X]], align 4 -// CHECK10-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: br label [[FOR_INC12:%.*]] -// CHECK10: for.inc12: -// CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 -// CHECK10-NEXT: store i8 [[INC]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK10: for.end13: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[X:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i8, align 1 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[X]], align 4 -// CHECK10-NEXT: store i8 48, i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: store i32 -10, i32* [[X]], align 4 -// CHECK10-NEXT: br label [[FOR_COND1:%.*]] -// CHECK10: for.cond1: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 -// CHECK10-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK10-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body3: -// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK10-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] -// CHECK10-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 -// CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] -// CHECK10-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 -// CHECK10-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] -// CHECK10-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 -// CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] -// CHECK10-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[X]], align 4 -// CHECK10-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: br label [[FOR_INC11:%.*]] -// CHECK10: for.inc11: -// CHECK10-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 -// CHECK10-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 -// CHECK10-NEXT: store i8 [[INC12]], i8* [[I]], align 1 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK10: for.end13: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z3foov -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_Z8mayThrowv() -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK10-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 -// CHECK10-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 -// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 -// CHECK10-NEXT: store i32 131071, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z3foov() -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float -// CHECK10-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] -// CHECK10-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] -// CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 -// CHECK10-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] -// CHECK10-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK10-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK10-NEXT: ret void -// -// // CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: @@ -9751,301 +7766,4 @@ // CHECK12: omp.precond.end: // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9incrementv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 5 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 5, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP1]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z16range_for_singlev -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK13-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK13-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK13-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK13-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK13-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK13-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 1 -// CHECK13-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]] -// CHECK13: for.end: -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv -// CHECK13-SAME: () #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK13-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK13-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 -// CHECK13-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[__END2:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK13-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK13-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK13-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK13-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END10:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE2]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP6]], i64 0, i64 0 -// CHECK13-NEXT: store i32* [[ARRAYDECAY2]], i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK13-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 -// CHECK13-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY3]], i64 10 -// CHECK13-NEXT: store i32* [[ADD_PTR4]], i32** [[__END2]], align 8 -// CHECK13-NEXT: br label [[FOR_COND5:%.*]] -// CHECK13: for.cond5: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[__END2]], align 8 -// CHECK13-NEXT: [[CMP6:%.*]] = icmp ne i32* [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK13-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 1 -// CHECK13-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN2]], align 8 -// CHECK13-NEXT: br label [[FOR_COND5]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC8:%.*]] -// CHECK13: for.inc8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: [[INCDEC_PTR9:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 1 -// CHECK13-NEXT: store i32* [[INCDEC_PTR9]], i32** [[__BEGIN1]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]] -// CHECK13: for.end10: -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9incrementv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 5 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 5, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP1]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z16range_for_singlev -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK14-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK14-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK14-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK14-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK14-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK14-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 1 -// CHECK14-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]] -// CHECK14: for.end: -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv -// CHECK14-SAME: () #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 -// CHECK14-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 -// CHECK14-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__END1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 -// CHECK14-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[__END2:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* -// CHECK14-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) -// CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 -// CHECK14-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 -// CHECK14-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 -// CHECK14-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END10:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 -// CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE2]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP6]], i64 0, i64 0 -// CHECK14-NEXT: store i32* [[ARRAYDECAY2]], i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 -// CHECK14-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 -// CHECK14-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY3]], i64 10 -// CHECK14-NEXT: store i32* [[ADD_PTR4]], i32** [[__END2]], align 8 -// CHECK14-NEXT: br label [[FOR_COND5:%.*]] -// CHECK14: for.cond5: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[__END2]], align 8 -// CHECK14-NEXT: [[CMP6:%.*]] = icmp ne i32* [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A]], align 8 -// CHECK14-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 1 -// CHECK14-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN2]], align 8 -// CHECK14-NEXT: br label [[FOR_COND5]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC8:%.*]] -// CHECK14: for.inc8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: [[INCDEC_PTR9:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 1 -// CHECK14-NEXT: store i32* [[INCDEC_PTR9]], i32** [[__BEGIN1]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]] -// CHECK14: for.end10: -// CHECK14-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp b/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp --- a/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp +++ b/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -528,91 +528,4 @@ // CHECK2-NEXT: store atomic volatile i8 1, i8* [[TMP5]] unordered, align 1 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP1]], 5 -// CHECK3-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK3: if.then: -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A]], align 4 -// CHECK3-NEXT: br label [[IF_END]] -// CHECK3: if.end: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP1]], 5 -// CHECK4-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK4: if.then: -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A]], align 4 -// CHECK4-NEXT: br label [[IF_END]] -// CHECK4: if.end: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_for_linear_codegen.cpp b/clang/test/OpenMP/parallel_for_linear_codegen.cpp --- a/clang/test/OpenMP/parallel_for_linear_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_linear_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -975,398 +975,4 @@ // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK5-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK5-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK5-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK5-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[LVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[LVAR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 1 -// CHECK5-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[LVAR]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[LVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC1]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca float*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store float* [[F]], float** [[PVAR]], align 8 -// CHECK6-NEXT: store i64 0, i64* [[LVAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[PVAR]], align 8 -// CHECK6-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3 -// CHECK6-NEXT: store float* [[ADD_PTR]], float** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[LVAR]], align 8 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP2]], 3 -// CHECK6-NEXT: store i64 [[ADD]], i64* [[LVAR]], align 8 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3:[0-9]+]] -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[LVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[LVAR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 1 -// CHECK6-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[LVAR]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[LVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC1]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 5 -// CHECK8-NEXT: store i32 [[ADD]], i32* @g, align 4 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP2:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP3]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP6:%.*]] = load i8*, i8** [[TMP4]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP7]](i8* [[TMP5]]) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1082,62 +1082,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG22]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG26:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG27:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG30]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG30]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG31:![0-9]+]], !llvm.loop [[LOOP32:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG35:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG35]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_if_codegen.cpp b/clang/test/OpenMP/parallel_if_codegen.cpp --- a/clang/test/OpenMP/parallel_if_codegen.cpp +++ b/clang/test/OpenMP/parallel_if_codegen.cpp @@ -3,18 +3,18 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -disable-O0-optnone -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -407,68 +407,6 @@ // CHECK2-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: ret i32 0 -// -// // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: @@ -978,65 +916,4 @@ // CHECK7-NEXT: call void @_Z3fn3v() // CHECK7-NEXT: ret void // -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_Z9gtid_testv() -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_Z3fn4v() -// CHECK9-NEXT: call void @_Z3fn5v() -// CHECK9-NEXT: call void @_Z3fn6v() -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK9-NEXT: call void @_Z3fn1v() -// CHECK9-NEXT: call void @_Z3fn2v() -// CHECK9-NEXT: call void @_Z3fn3v() -// CHECK9-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_master_codegen.cpp b/clang/test/OpenMP/parallel_master_codegen.cpp --- a/clang/test/OpenMP/parallel_master_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_codegen.cpp @@ -9,9 +9,9 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void foo() { extern void mayThrow(); mayThrow(); } @@ -31,9 +31,9 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_private() { @@ -52,9 +52,9 @@ // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_private() { @@ -73,9 +73,9 @@ // RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK31 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_default_firstprivate() { @@ -96,9 +96,9 @@ // RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCK32 -fopenmp-version=51 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" struct St { @@ -136,9 +136,9 @@ // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" void parallel_master_firstprivate() { @@ -157,17 +157,14 @@ // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK27 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple x86_64-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 int a; @@ -189,13 +186,9 @@ #endif #ifdef CK6 ///==========================================================================/// -// RUN: %clang_cc1 -DCK6 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK33 // RUN: %clang_cc1 -DCK6 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK34 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK35 // RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK36 void parallel_master_reduction() { @@ -217,13 +210,9 @@ #endif #ifdef CK7 ///==========================================================================/// -// RUN: %clang_cc1 -DCK7 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK37 // RUN: %clang_cc1 -DCK7 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK7 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 -// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK39 // RUN: %clang_cc1 -DCK7 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK7 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK40 void parallel_master_if() { @@ -236,13 +225,9 @@ #endif #ifdef CK8 ///==========================================================================/// -// RUN: %clang_cc1 -DCK8 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK41 // RUN: %clang_cc1 -DCK8 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK8 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK42 -// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK43 // RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK8 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK44 typedef __INTPTR_TYPE__ intptr_t; @@ -277,13 +262,9 @@ #endif #ifdef CK9 ///==========================================================================/// -// RUN: %clang_cc1 -DCK9 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK45 // RUN: %clang_cc1 -DCK9 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK9 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK46 -// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK47 // RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK9 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK48 typedef void **omp_allocator_handle_t; extern const omp_allocator_handle_t omp_null_allocator; extern const omp_allocator_handle_t omp_default_mem_alloc; @@ -421,64 +402,6 @@ // CHECK2-NEXT: unreachable // // -// CHECK3-LABEL: define {{[^@]+}}@_Z3foov -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z8mayThrowv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z15parallel_masterv -// CHECK3-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: ret void -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK3-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z3foov -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z8mayThrowv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z15parallel_masterv -// CHECK4-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: ret void -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK4-NEXT: unreachable -// -// // CHECK5-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: @@ -541,28 +464,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[A1]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[A1]], align 4 -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -629,26 +530,6 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z23parallel_master_privatev -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK12-NEXT: ret void -// -// // CHECK13-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -725,26 +606,6 @@ // CHECK14-NEXT: ret void // // -// CHECK15-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK16-NEXT: ret void -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -937,136 +798,6 @@ // CHECK18-NEXT: ret void // // -// CHECK19-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK19-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) -// CHECK19-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK19-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 1 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK19-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZN2St1yE, align 4 -// CHECK19-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK19-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 -// CHECK19-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK19-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK20-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) -// CHECK20-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A1]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK20-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[A]], i32 0, i32 1 -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK20-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZN2St1yE, align 4 -// CHECK20-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK20-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 -// CHECK20-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK20-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK20-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK20-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK20-NEXT: store i32 0, i32* [[B]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK20-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK20-NEXT: ret void -// -// // CHECK21-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: @@ -1143,26 +874,6 @@ // CHECK22-NEXT: ret void // // -// CHECK23-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK23-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK24-NEXT: ret void -// -// // CHECK25-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -1247,24 +958,6 @@ // CHECK26-NEXT: ret void // // -// CHECK27-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK27-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK27-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK27-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK27-NEXT: ret void -// -// -// CHECK28-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK28-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK28-NEXT: entry: -// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK28-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK28-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK28-NEXT: ret void -// -// // CHECK29-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK29-SAME: () #[[ATTR0:[0-9]+]] { // CHECK29-NEXT: entry: @@ -1312,901 +1005,4 @@ // CHECK29-SAME: () #[[ATTR4:[0-9]+]] comdat { // CHECK29-NEXT: ret i32* @a // -// -// CHECK30-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK30-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @a) -// CHECK30-NEXT: ret void -// -// -// CHECK30-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK30-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK30-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK30-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK30-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @a to i64) -// CHECK30-NEXT: br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]] -// CHECK30: copyin.not.master: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK30-NEXT: store i32 [[TMP3]], i32* @a, align 4 -// CHECK30-NEXT: br label [[COPYIN_NOT_MASTER_END]] -// CHECK30: copyin.not.master.end: -// CHECK30-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK30-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) -// CHECK30-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) -// CHECK30-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 -// CHECK30-NEXT: br i1 [[TMP9]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK30: omp_if.then: -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* @a, align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK30-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]]) -// CHECK30-NEXT: br label [[OMP_IF_END]] -// CHECK30: omp_if.end: -// CHECK30-NEXT: ret void -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZTW1a -// CHECK30-SAME: () #[[ATTR4:[0-9]+]] comdat { -// CHECK30-NEXT: ret i32* @a -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK31-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK31-NEXT: ret void -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv -// CHECK32-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* @a, align 4 -// CHECK32-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK33-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G]]) -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK33-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK33-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK33-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK33-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK33-NEXT: store i32 0, i32* [[G1]], align 4 -// CHECK33-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK33-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK33-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK33-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK33: omp_if.then: -// CHECK33-NEXT: store i32 1, i32* [[G1]], align 4 -// CHECK33-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK33-NEXT: br label [[OMP_IF_END]] -// CHECK33: omp_if.end: -// CHECK33-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK33-NEXT: [[TMP6:%.*]] = bitcast i32* [[G1]] to i8* -// CHECK33-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 -// CHECK33-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK33-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK33-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK33-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK33-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK33-NEXT: ] -// CHECK33: .omp.reduction.case1: -// CHECK33-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK33-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK33-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 -// CHECK33-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK33-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK33: .omp.reduction.case2: -// CHECK33-NEXT: [[TMP11:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK33-NEXT: [[TMP12:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP11]] monotonic, align 4 -// CHECK33-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK33: .omp.reduction.default: -// CHECK33-NEXT: ret void -// -// -// CHECK33-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK33-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK33-NEXT: entry: -// CHECK33-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK33-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK33-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK33-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK33-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK33-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK33-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK33-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK33-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK33-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK33-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK33-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK33-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK33-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK33-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK33-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK33-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK34-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G]]) -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK34-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK34-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 -// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK34-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK34-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK34-NEXT: store i32 0, i32* [[G1]], align 4 -// CHECK34-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK34-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK34-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 -// CHECK34-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK34: omp_if.then: -// CHECK34-NEXT: store i32 1, i32* [[G1]], align 4 -// CHECK34-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK34-NEXT: br label [[OMP_IF_END]] -// CHECK34: omp_if.end: -// CHECK34-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK34-NEXT: [[TMP6:%.*]] = bitcast i32* [[G1]] to i8* -// CHECK34-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8 -// CHECK34-NEXT: [[TMP7:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* -// CHECK34-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_reduce_nowait(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP7]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK34-NEXT: switch i32 [[TMP8]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK34-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK34-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK34-NEXT: ] -// CHECK34: .omp.reduction.case1: -// CHECK34-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK34-NEXT: [[TMP10:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK34-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 -// CHECK34-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) -// CHECK34-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK34: .omp.reduction.case2: -// CHECK34-NEXT: [[TMP11:%.*]] = load i32, i32* [[G1]], align 4 -// CHECK34-NEXT: [[TMP12:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP11]] monotonic, align 4 -// CHECK34-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK34: .omp.reduction.default: -// CHECK34-NEXT: ret void -// -// -// CHECK34-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK34-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK34-NEXT: entry: -// CHECK34-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK34-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 -// CHECK34-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK34-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 -// CHECK34-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 -// CHECK34-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* -// CHECK34-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 -// CHECK34-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* -// CHECK34-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 -// CHECK34-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK34-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* -// CHECK34-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 -// CHECK34-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// CHECK34-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK34-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK34-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK34-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK34-NEXT: ret void -// -// -// CHECK35-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK35-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK35-NEXT: entry: -// CHECK35-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK35-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK35-NEXT: ret void -// -// -// CHECK36-LABEL: define {{[^@]+}}@_Z25parallel_master_reductionv -// CHECK36-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK36-NEXT: entry: -// CHECK36-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK36-NEXT: store i32 1, i32* [[G]], align 4 -// CHECK36-NEXT: ret void -// -// -// CHECK37-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK37-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK37-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK37-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK37-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK37-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] -// CHECK37-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK37-NEXT: ret void -// -// -// CHECK37-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK37-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK37-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK37-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK37-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK37-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK37-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK37-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK37-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK37-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK37-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK37: omp_if.then: -// CHECK37-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK37-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK37: invoke.cont: -// CHECK37-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK37-NEXT: br label [[OMP_IF_END]] -// CHECK37: lpad: -// CHECK37-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK37-NEXT: catch i8* null -// CHECK37-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK37-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK37-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK37-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK37-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK37-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK37: omp_if.end: -// CHECK37-NEXT: ret void -// CHECK37: terminate.handler: -// CHECK37-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK37-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR4:[0-9]+]] -// CHECK37-NEXT: unreachable -// -// -// CHECK37-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK37-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK37-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2]] -// CHECK37-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK37-NEXT: unreachable -// -// -// CHECK38-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK38-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK38-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK38-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK38-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 -// CHECK38-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] -// CHECK38-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK38-NEXT: ret void -// -// -// CHECK38-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK38-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK38-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK38-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK38-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK38-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK38-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK38-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK38-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK38-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK38-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK38: omp_if.then: -// CHECK38-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK38-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK38: invoke.cont: -// CHECK38-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK38-NEXT: br label [[OMP_IF_END]] -// CHECK38: lpad: -// CHECK38-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK38-NEXT: catch i8* null -// CHECK38-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK38-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK38-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK38-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK38-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK38-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK38: omp_if.end: -// CHECK38-NEXT: ret void -// CHECK38: terminate.handler: -// CHECK38-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK38-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR4:[0-9]+]] -// CHECK38-NEXT: unreachable -// -// -// CHECK38-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK38-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK38-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2]] -// CHECK38-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK38-NEXT: unreachable -// -// -// CHECK39-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK39-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK39-NEXT: entry: -// CHECK39-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK39-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK39: invoke.cont: -// CHECK39-NEXT: ret void -// CHECK39: terminate.lpad: -// CHECK39-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK39-NEXT: catch i8* null -// CHECK39-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK39-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK39-NEXT: unreachable -// -// -// CHECK39-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK39-SAME: (i8* [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK39-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]] -// CHECK39-NEXT: call void @_ZSt9terminatev() #[[ATTR2]] -// CHECK39-NEXT: unreachable -// -// -// CHECK40-LABEL: define {{[^@]+}}@_Z18parallel_master_ifv -// CHECK40-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK40-NEXT: entry: -// CHECK40-NEXT: invoke void @_Z18parallel_master_ifv() -// CHECK40-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK40: invoke.cont: -// CHECK40-NEXT: ret void -// CHECK40: terminate.lpad: -// CHECK40-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK40-NEXT: catch i8* null -// CHECK40-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK40-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR2:[0-9]+]] -// CHECK40-NEXT: unreachable -// -// -// CHECK40-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK40-SAME: (i8* [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK40-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]] -// CHECK40-NEXT: call void @_ZSt9terminatev() #[[ATTR2]] -// CHECK40-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@main -// CHECK41-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK41-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK41-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 4) -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK41-NEXT: ret i32 [[CALL]] -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK41-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK41-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK41-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK41: omp_if.then: -// CHECK41-NEXT: invoke void @_Z3foov() -// CHECK41-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK41: invoke.cont: -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[OMP_IF_END]] -// CHECK41: lpad: -// CHECK41-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK41-NEXT: catch i8* null -// CHECK41-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK41-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK41-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK41: omp_if.end: -// CHECK41-NEXT: ret void -// CHECK41: terminate.handler: -// CHECK41-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]] -// CHECK41-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK41-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK41-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] -// CHECK41-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] -// CHECK41-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK41-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK41-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK41-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK41: omp_if.then: -// CHECK41-NEXT: invoke void @_Z3foov() -// CHECK41-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK41: invoke.cont: -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[OMP_IF_END]] -// CHECK41: lpad: -// CHECK41-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK41-NEXT: catch i8* null -// CHECK41-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK41-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK41-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK41: omp_if.end: -// CHECK41-NEXT: ret void -// CHECK41: terminate.handler: -// CHECK41-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK41-NEXT: unreachable -// -// -// CHECK41-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK41-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK41-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) -// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK41-NEXT: ret i32 0 -// -// -// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK41-NEXT: entry: -// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK41-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK41-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK41-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK41-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK41-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK41: omp_if.then: -// CHECK41-NEXT: invoke void @_Z3foov() -// CHECK41-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK41: invoke.cont: -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[OMP_IF_END]] -// CHECK41: lpad: -// CHECK41-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK41-NEXT: catch i8* null -// CHECK41-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK41-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK41-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK41-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK41-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK41: omp_if.end: -// CHECK41-NEXT: ret void -// CHECK41: terminate.handler: -// CHECK41-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK41-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK41-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@main -// CHECK42-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) -// CHECK42-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK42-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 4) -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 3) -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK42-NEXT: ret i32 [[CALL]] -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK42-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK42-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK42-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK42: omp_if.then: -// CHECK42-NEXT: invoke void @_Z3foov() -// CHECK42-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK42: invoke.cont: -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[OMP_IF_END]] -// CHECK42: lpad: -// CHECK42-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK42-NEXT: catch i8* null -// CHECK42-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK42-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK42-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK42: omp_if.end: -// CHECK42-NEXT: ret void -// CHECK42: terminate.handler: -// CHECK42-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6:[0-9]+]] -// CHECK42-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK42-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK42-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] -// CHECK42-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] -// CHECK42-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK42-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK42-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK42-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK42: omp_if.then: -// CHECK42-NEXT: invoke void @_Z3foov() -// CHECK42-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK42: invoke.cont: -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[OMP_IF_END]] -// CHECK42: lpad: -// CHECK42-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK42-NEXT: catch i8* null -// CHECK42-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK42-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK42-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK42: omp_if.end: -// CHECK42-NEXT: ret void -// CHECK42: terminate.handler: -// CHECK42-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK42-NEXT: unreachable -// -// -// CHECK42-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK42-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK42-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 2) -// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) -// CHECK42-NEXT: ret i32 0 -// -// -// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK42-NEXT: entry: -// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK42-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK42-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK42-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK42-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 -// CHECK42-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK42: omp_if.then: -// CHECK42-NEXT: invoke void @_Z3foov() -// CHECK42-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK42: invoke.cont: -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[OMP_IF_END]] -// CHECK42: lpad: -// CHECK42-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK42-NEXT: catch i8* null -// CHECK42-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK42-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1 -// CHECK42-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK42-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// CHECK42-NEXT: br label [[TERMINATE_HANDLER:%.*]] -// CHECK42: omp_if.end: -// CHECK42-NEXT: ret void -// CHECK42: terminate.handler: -// CHECK42-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK42-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR6]] -// CHECK42-NEXT: unreachable -// -// -// CHECK43-LABEL: define {{[^@]+}}@main -// CHECK43-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK43-NEXT: entry: -// CHECK43-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK43-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK43-NEXT: invoke void @_Z3foov() -// CHECK43-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK43: invoke.cont: -// CHECK43-NEXT: invoke void @_Z3foov() -// CHECK43-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK43: invoke.cont1: -// CHECK43-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK43-NEXT: ret i32 [[CALL]] -// CHECK43: terminate.lpad: -// CHECK43-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK43-NEXT: catch i8* null -// CHECK43-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK43-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK43-NEXT: unreachable -// -// -// CHECK43-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK43-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK43-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK43-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK43-NEXT: unreachable -// -// -// CHECK43-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK43-SAME: () #[[ATTR3:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK43-NEXT: entry: -// CHECK43-NEXT: invoke void @_Z3foov() -// CHECK43-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK43: invoke.cont: -// CHECK43-NEXT: ret i32 0 -// CHECK43: terminate.lpad: -// CHECK43-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK43-NEXT: catch i8* null -// CHECK43-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK43-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4]] -// CHECK43-NEXT: unreachable -// -// -// CHECK44-LABEL: define {{[^@]+}}@main -// CHECK44-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK44-NEXT: entry: -// CHECK44-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK44-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK44-NEXT: invoke void @_Z3foov() -// CHECK44-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK44: invoke.cont: -// CHECK44-NEXT: invoke void @_Z3foov() -// CHECK44-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK44: invoke.cont1: -// CHECK44-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK44-NEXT: ret i32 [[CALL]] -// CHECK44: terminate.lpad: -// CHECK44-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK44-NEXT: catch i8* null -// CHECK44-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK44-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK44-NEXT: unreachable -// -// -// CHECK44-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK44-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK44-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR5:[0-9]+]] -// CHECK44-NEXT: call void @_ZSt9terminatev() #[[ATTR4]] -// CHECK44-NEXT: unreachable -// -// -// CHECK44-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK44-SAME: () #[[ATTR3:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK44-NEXT: entry: -// CHECK44-NEXT: invoke void @_Z3foov() -// CHECK44-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK44: invoke.cont: -// CHECK44-NEXT: ret i32 0 -// CHECK44: terminate.lpad: -// CHECK44-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK44-NEXT: catch i8* null -// CHECK44-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK44-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR4]] -// CHECK44-NEXT: unreachable -// -// -// CHECK45-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK45-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK45-NEXT: entry: -// CHECK45-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK45-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK45-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK45-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK45-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK45-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK45-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK45-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK45-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8***)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8*** [[MYALLOC]]) -// CHECK45-NEXT: ret void -// -// -// CHECK45-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK45-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i8*** nonnull align 8 dereferenceable(8) [[MYALLOC:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK45-NEXT: entry: -// CHECK45-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK45-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK45-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK45-NEXT: [[MYALLOC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK45-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK45-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK45-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK45-NEXT: store i8*** [[MYALLOC]], i8**** [[MYALLOC_ADDR]], align 8 -// CHECK45-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK45-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[MYALLOC_ADDR]], align 8 -// CHECK45-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK45-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK45-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK45-NEXT: [[CONV1:%.*]] = bitcast i8** [[TMP3]] to i8* -// CHECK45-NEXT: [[DOTA__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP2]], i64 4, i8* [[CONV1]]) -// CHECK45-NEXT: [[DOTA__ADDR:%.*]] = bitcast i8* [[DOTA__VOID_ADDR]] to i32* -// CHECK45-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK45-NEXT: store i32 [[TMP4]], i32* [[DOTA__ADDR]], align 4 -// CHECK45-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK45-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK45-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK45: omp_if.then: -// CHECK45-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTA__ADDR]], align 4 -// CHECK45-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK45-NEXT: store i32 [[INC]], i32* [[DOTA__ADDR]], align 4 -// CHECK45-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK45-NEXT: br label [[OMP_IF_END]] -// CHECK45: omp_if.end: -// CHECK45-NEXT: [[TMP8:%.*]] = bitcast i32* [[DOTA__ADDR]] to i8* -// CHECK45-NEXT: [[TMP9:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK45-NEXT: [[CONV2:%.*]] = bitcast i8** [[TMP9]] to i8* -// CHECK45-NEXT: call void @__kmpc_free(i32 [[TMP2]], i8* [[TMP8]], i8* [[CONV2]]) -// CHECK45-NEXT: ret void -// -// -// CHECK46-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK46-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK46-NEXT: entry: -// CHECK46-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK46-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK46-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK46-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK46-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK46-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK46-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK46-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK46-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8***)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8*** [[MYALLOC]]) -// CHECK46-NEXT: ret void -// -// -// CHECK46-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK46-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i8*** nonnull align 8 dereferenceable(8) [[MYALLOC:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK46-NEXT: entry: -// CHECK46-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK46-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK46-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK46-NEXT: [[MYALLOC_ADDR:%.*]] = alloca i8***, align 8 -// CHECK46-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK46-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK46-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK46-NEXT: store i8*** [[MYALLOC]], i8**** [[MYALLOC_ADDR]], align 8 -// CHECK46-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK46-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[MYALLOC_ADDR]], align 8 -// CHECK46-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK46-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK46-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK46-NEXT: [[CONV1:%.*]] = bitcast i8** [[TMP3]] to i8* -// CHECK46-NEXT: [[DOTA__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP2]], i64 4, i8* [[CONV1]]) -// CHECK46-NEXT: [[DOTA__ADDR:%.*]] = bitcast i8* [[DOTA__VOID_ADDR]] to i32* -// CHECK46-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK46-NEXT: store i32 [[TMP4]], i32* [[DOTA__ADDR]], align 4 -// CHECK46-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK46-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 -// CHECK46-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] -// CHECK46: omp_if.then: -// CHECK46-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTA__ADDR]], align 4 -// CHECK46-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK46-NEXT: store i32 [[INC]], i32* [[DOTA__ADDR]], align 4 -// CHECK46-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// CHECK46-NEXT: br label [[OMP_IF_END]] -// CHECK46: omp_if.end: -// CHECK46-NEXT: [[TMP8:%.*]] = bitcast i32* [[DOTA__ADDR]] to i8* -// CHECK46-NEXT: [[TMP9:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK46-NEXT: [[CONV2:%.*]] = bitcast i8** [[TMP9]] to i8* -// CHECK46-NEXT: call void @__kmpc_free(i32 [[TMP2]], i8* [[TMP8]], i8* [[CONV2]]) -// CHECK46-NEXT: ret void -// -// -// CHECK47-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK47-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK47-NEXT: entry: -// CHECK47-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK47-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK47-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK47-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK47-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK47-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK47-NEXT: ret void -// -// -// CHECK48-LABEL: define {{[^@]+}}@_Z24parallel_master_allocatev -// CHECK48-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK48-NEXT: entry: -// CHECK48-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK48-NEXT: [[MYALLOC:%.*]] = alloca i8**, align 8 -// CHECK48-NEXT: store i8** null, i8*** [[MYALLOC]], align 8 -// CHECK48-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK48-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK48-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK48-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -992,25 +992,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp --- a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1901,359 +1901,4 @@ // CHECK2-NEXT: call void @__cxx_global_var_init() // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_10]], align 1 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK3-NEXT: br label [[FOR_COND12:%.*]] -// CHECK3: for.cond12: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END25:%.*]] -// CHECK3: for.body14: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[J]], align 4 -// CHECK3-NEXT: br label [[FOR_COND15:%.*]] -// CHECK3: for.cond15: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP12]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i8, i8* [[TMP14]], i64 [[IDXPROM16]] -// CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[ARRAYIDX17]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK3-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP11]], [[CONV]] -// CHECK3-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END22:%.*]] -// CHECK3: for.body19: -// CHECK3-NEXT: br label [[FOR_INC20:%.*]] -// CHECK3: for.inc20: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[J]], align 4 -// CHECK3-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK3-NEXT: store i32 [[INC21]], i32* [[J]], align 4 -// CHECK3-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end22: -// CHECK3-NEXT: br label [[FOR_INC23:%.*]] -// CHECK3: for.inc23: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK3-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK3-NEXT: store i32 [[INC24]], i32* [[I9]], align 4 -// CHECK3-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end25: -// CHECK3-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK3-NEXT: br label [[FOR_COND27:%.*]] -// CHECK3: for.cond27: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK3-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK3-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END32:%.*]] -// CHECK3: for.body29: -// CHECK3-NEXT: br label [[FOR_INC30:%.*]] -// CHECK3: for.inc30: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK3-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK3-NEXT: store i32 [[INC31]], i32* [[I26]], align 4 -// CHECK3-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end32: -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP21]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32* [[A2]], i32** [[A]], align 8 -// CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A4]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A5]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[A5]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp -// CHECK3-SAME: () #[[ATTR1]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @__cxx_global_var_init() -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_10]], align 1 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK4-NEXT: br label [[FOR_COND12:%.*]] -// CHECK4: for.cond12: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK4-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END25:%.*]] -// CHECK4: for.body14: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i32 [[TMP10]], i32* [[J]], align 4 -// CHECK4-NEXT: br label [[FOR_COND15:%.*]] -// CHECK4: for.cond15: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK4-NEXT: [[TMP12:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8*, i8** [[TMP12]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK4-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i8, i8* [[TMP14]], i64 [[IDXPROM16]] -// CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[ARRAYIDX17]], align 1 -// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK4-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP11]], [[CONV]] -// CHECK4-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END22:%.*]] -// CHECK4: for.body19: -// CHECK4-NEXT: br label [[FOR_INC20:%.*]] -// CHECK4: for.inc20: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[J]], align 4 -// CHECK4-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK4-NEXT: store i32 [[INC21]], i32* [[J]], align 4 -// CHECK4-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end22: -// CHECK4-NEXT: br label [[FOR_INC23:%.*]] -// CHECK4: for.inc23: -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK4-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK4-NEXT: store i32 [[INC24]], i32* [[I9]], align 4 -// CHECK4-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end25: -// CHECK4-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK4-NEXT: br label [[FOR_COND27:%.*]] -// CHECK4: for.cond27: -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK4-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK4-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END32:%.*]] -// CHECK4: for.body29: -// CHECK4-NEXT: br label [[FOR_INC30:%.*]] -// CHECK4: for.inc30: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK4-NEXT: [[INC31:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK4-NEXT: store i32 [[INC31]], i32* [[I26]], align 4 -// CHECK4-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end32: -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP21]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[A:%.*]] = alloca i32*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32* [[A2]], i32** [[A]], align 8 -// CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A4]], align 4 -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A5]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[A5]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp -// CHECK4-SAME: () #[[ATTR1]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @__cxx_global_var_init() -// CHECK4-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp --- a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp @@ -7,13 +7,13 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #if !defined(ARRAY) && !defined(LOOP) @@ -2705,655 +2705,4 @@ // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) -// CHECK7-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP7]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP7]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 0.000000e+00, double* [[F]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK7-NEXT: store double [[TMP0]], double* [[F]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) -// CHECK8-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP7]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP7]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 0.000000e+00, double* [[F]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK8-NEXT: store double [[TMP0]], double* [[F]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK10-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK10-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// CHECK10-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK10-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: store double 1.000000e+00, double* @g, align 8 -// CHECK10-NEXT: store i32 11, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK10-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK10-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK10-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK10-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK10-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK10-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK10-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK10-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK10-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK10-NEXT: store volatile double [[TMP1]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[BLOCK_CAPTURED2]], align 8 -// CHECK10-NEXT: [[TMP3:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// CHECK10-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP3]] to %struct.__block_literal_generic* -// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK10-NEXT: [[TMP6:%.*]] = load i8*, i8** [[TMP4]], align 8 -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// CHECK10-NEXT: call void [[TMP7]](i8* [[TMP5]]) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK10-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// CHECK10-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// CHECK10-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK10-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK10-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK10-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// CHECK11-SAME: (i32 [[N:%.*]], float* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK11-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z4loopv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_private_codegen.cpp b/clang/test/OpenMP/parallel_private_codegen.cpp --- a/clang/test/OpenMP/parallel_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1366,1006 +1366,4 @@ // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B3]], i32** [[TMP4]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[C]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP11]], align 4 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP13]], -1 -// CHECK7-NEXT: store i32 [[DEC4]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP15]], 1 -// CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca i32, align 128 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store i32 1, i32* [[G]], align 128 -// CHECK8-NEXT: store i32 20, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[G]], align 128 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 32 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 40, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[BLOCK_CAPTURED6]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[BLOCK_CAPTURED7]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP8]](i8* [[TMP6]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: store i32* [[A]], i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[C]], i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 -// CHECK8-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC4]], i32* [[TMP5]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[DEC5:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK8-NEXT: store i32 [[DEC5]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 -// CHECK8-NEXT: [[DIV6:%.*]] = sdiv i32 [[TMP9]], 1 -// CHECK8-NEXT: store i32 [[DIV6]], i32* [[TMP8]], align 4 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_reduction_codegen.cpp b/clang/test/OpenMP/parallel_reduction_codegen.cpp --- a/clang/test/OpenMP/parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -80,9 +80,6 @@ }; -//CHECK: foo_array_sect -//CHECK: call void {{.+}}@__kmpc_fork_call( -//CHECK: ret void void foo_array_sect(short x[1]) { #pragma omp parallel reduction(default, + : x[:]) {} @@ -4402,1053 +4399,4 @@ // CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK5-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK5-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 -// CHECK5-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK5: if.then: -// CHECK5-NEXT: br label [[WHILE_COND:%.*]] -// CHECK5: while.cond: -// CHECK5-NEXT: br label [[WHILE_BODY:%.*]] -// CHECK5: while.body: -// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK5-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: if.end: -// CHECK5-NEXT: [[CALL5:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL5]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done6: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret float 0.000000e+00 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK5-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP6]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP7]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK6-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK6-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 -// CHECK6-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK6: if.then: -// CHECK6-NEXT: br label [[WHILE_COND:%.*]] -// CHECK6: while.cond: -// CHECK6-NEXT: br label [[WHILE_BODY:%.*]] -// CHECK6: while.body: -// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK6-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: if.end: -// CHECK6-NEXT: [[CALL5:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL5]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done6: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret float 0.000000e+00 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK6-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP4]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP6]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[B4]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP7]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK7-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK7-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK7-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP4]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP7]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK7-NEXT: store i32* [[TMP9]], i32** [[TMP8]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR0]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[TMP17]], align 4 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC4:%.*]] = add nsw i32 [[TMP19]], -1 -// CHECK7-NEXT: store i32 [[DEC4]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 -// CHECK7-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP21]], 1 -// CHECK7-NEXT: store i32 [[DIV5]], i32* [[TMP20]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK8-SAME: (i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 -// CHECK8-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, align 128 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store i32 1, i32* @g, align 128 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 16 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 128 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR3]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C5:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK8-NEXT: [[C6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C6]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C5]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C5]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP7]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @___ZN2SSC2ERi_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP4]], i32** [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED8]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED9:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP7]], align 8 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[BLOCK_CAPTURED9]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP7]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP8]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP11]](i8* [[TMP9]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR3]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP6:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 8 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[_TMP6]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[TMP7]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[DEC8:%.*]] = add nsw i32 [[TMP9]], -1 -// CHECK8-NEXT: store i32 [[DEC8]], i32* [[BLOCK_CAPTURE_ADDR4]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP6]], align 8 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 -// CHECK8-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[DIV9]], i32* [[TMP10]], align 4 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -974,25 +974,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_sections_codegen.cpp b/clang/test/OpenMP/parallel_sections_codegen.cpp --- a/clang/test/OpenMP/parallel_sections_codegen.cpp +++ b/clang/test/OpenMP/parallel_sections_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -fexceptions -fcxx-exceptions -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -o - %s | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -emit-llvm -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -o - %s | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -fexceptions -fcxx-exceptions -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -include-pch %t -fsyntax-only -verify %s -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -362,117 +362,4 @@ // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]] // CHECK2-NEXT: unreachable // -// -// CHECK3-LABEL: define {{[^@]+}}@_Z3foov -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z8mayThrowv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z3barv -// CHECK3-SAME: () #[[ATTR0]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z8mayThrowv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: invoke void @_Z3barv() -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5:[0-9]+]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR4:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: ret i32 0 -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5]] -// CHECK3-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z3foov -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z8mayThrowv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z3barv -// CHECK4-SAME: () #[[ATTR0]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z8mayThrowv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: invoke void @_Z3barv() -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5:[0-9]+]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR4:[0-9]+]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: ret i32 0 -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR5]] -// CHECK4-NEXT: unreachable -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp --- a/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1058,25 +1058,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_firstprivate_codegen.cpp b/clang/test/OpenMP/sections_firstprivate_codegen.cpp --- a/clang/test/OpenMP/sections_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1720,835 +1720,4 @@ // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: store i32 10, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 20, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_lastprivate_codegen.cpp b/clang/test/OpenMP/sections_lastprivate_codegen.cpp --- a/clang/test/OpenMP/sections_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_lastprivate_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -2835,1071 +2835,4 @@ // CHECK8-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK9-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK9-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP4]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP3]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK10-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK10-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP4]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP3]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK12-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store i32 1, i32* @g, align 4 -// CHECK12-NEXT: store i32 17, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK12-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK12-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK12-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK12-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK12-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK13-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK13-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK14-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load double, double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP2]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* @_ZN1A1xE, align 8 -// CHECK14-NEXT: [[CALL2:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL2]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK15-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK15-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK16-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK16-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK16-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 1, i32* @g, align 4 -// CHECK16-NEXT: store i32 17, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK16-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK16-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK16-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK16-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK16-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK16-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK16-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK16-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK16-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK16-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK16-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK16-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK16-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK16-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK16-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK16-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK16-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK16-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK16-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK16-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK16-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK16-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK16-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_private_codegen.cpp b/clang/test/OpenMP/sections_private_codegen.cpp --- a/clang/test/OpenMP/sections_private_codegen.cpp +++ b/clang/test/OpenMP/sections_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1075,626 +1075,4 @@ // CHECK4-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double 1.000000e+00, double* [[G]], align 8 -// CHECK8-NEXT: store i32 111, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile double, double* [[G]], align 8 -// CHECK8-NEXT: store volatile double [[TMP0]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_reduction_codegen.cpp b/clang/test/OpenMP/sections_reduction_codegen.cpp --- a/clang/test/OpenMP/sections_reduction_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -2159,570 +2159,4 @@ // CHECK4-NEXT: store double [[ADD]], double* [[TMP11]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 1 -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR1]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done5: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK5-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK5-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK5-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load float, float* [[T_VAR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi float [[TMP1]] to i32 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi float [[TMP4]] to i32 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 1 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX3]], align 4 -// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 1 -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR1]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done5: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float -// CHECK6-NEXT: store float [[CONV2]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32 -// CHECK6-NEXT: store i32 [[CONV]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]] -// CHECK6-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32 -// CHECK6-NEXT: store i32 [[CONV2]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double 1.000000e+00, double* @g, align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile double, double* @g, align 8 -// CHECK8-NEXT: store volatile double [[TMP0]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_reduction_task_codegen.cpp b/clang/test/OpenMP/sections_reduction_task_codegen.cpp --- a/clang/test/OpenMP/sections_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1067,25 +1067,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp --- a/clang/test/OpenMP/single_codegen.cpp +++ b/clang/test/OpenMP/single_codegen.cpp @@ -11,11 +11,11 @@ // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -std=c++11 -fopenmp-simd -fnoopenmp-use-tls -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER @@ -5238,1202 +5238,4 @@ // CHECK6-NEXT: store %struct.St* [[TMP19]], %struct.St** [[TMP15]], align 8 // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK7-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK7-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK7-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2) -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK7-NEXT: ret void -// CHECK7: lpad: -// CHECK7-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: cleanup -// CHECK7-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ARRAYCTOR_CUR]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: br label [[EH_RESUME:%.*]] -// CHECK7: eh.resume: -// CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK7-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL2]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3foov -// CHECK7-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_Z8mayThrowv() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR6:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 -// CHECK7-NEXT: [[C:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK7-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]) -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) -// CHECK7-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK7-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32 -// CHECK7-NEXT: ret i32 [[CONV]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP2]]) #[[ATTR9:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK7-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK7-SAME: () #[[ATTR8:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK7-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK7-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK7-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP11:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK7-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK7-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK7-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK7-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK7-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK7-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK7-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK7-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[_TMP9]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP4]], i32** [[_TMP10]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP9]], align 8 -// CHECK7-NEXT: store i32* [[TMP5]], i32** [[_TMP11]], align 8 -// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK7-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK7-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP12:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP12]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP13]]) #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon*, %class.anon** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], %class.anon* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK7-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK7-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK7-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK7-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK7-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[INC5]], i32* [[TMP19]], align 4 -// CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP21]], -1 -// CHECK7-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK7-NEXT: [[TMP22:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK7-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP23]], 1 -// CHECK7-NEXT: store i32 [[DIV7]], i32* [[TMP22]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK7-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK7-NEXT: [[A2:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[_TMP4:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK7-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 0.000000e+00, double* [[A]], align 8 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[A3]], double** [[A2]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load double*, double** [[A2]], align 8 -// CHECK7-NEXT: store double* [[TMP0]], double** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK7-NEXT: store double* [[TMP1]], double** [[_TMP4]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP4:%.*]] = load double*, double** [[_TMP4]], align 8 -// CHECK7-NEXT: store double* [[TMP4]], double** [[TMP3]], align 8 -// CHECK7-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: ret void -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR9]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SST* [[TMP1]], %struct.SST** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 -// CHECK7-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK7-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK7-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: [[_TMP2:%.*]] = alloca double*, align 8 -// CHECK7-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[TMP3]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[TMP5]], align 8 -// CHECK7-NEXT: store double* [[TMP6]], double** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP7:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK7-NEXT: store double* [[TMP7]], double** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load double, double* [[TMP8]], align 8 -// CHECK7-NEXT: [[INC3:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC3]], double* [[TMP8]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK8-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK8-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK8-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2) -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] -// CHECK8-NEXT: ret void -// CHECK8: lpad: -// CHECK8-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: cleanup -// CHECK8-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ARRAYCTOR_CUR]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: br label [[EH_RESUME:%.*]] -// CHECK8: eh.resume: -// CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK8-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL2]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3foov -// CHECK8-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z8mayThrowv() -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR6:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 -// CHECK8-NEXT: [[C:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK8-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]) -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) -// CHECK8-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK8-NEXT: store i8 2, i8* [[A]], align 1 -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32 -// CHECK8-NEXT: ret i32 [[CONV]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP2]]) #[[ATTR9:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK8-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK8-SAME: () #[[ATTR8:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK8-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK8-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK8-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP11:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32* [[A3]], i32** [[A2]], align 8 -// CHECK8-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 -// CHECK8-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 -// CHECK8-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 -// CHECK8-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 -// CHECK8-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 -// CHECK8-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 -// CHECK8-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 -// CHECK8-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[_TMP9]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP4]], i32** [[_TMP10]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP9]], align 8 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[_TMP11]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8 -// CHECK8-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK8-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP11]], align 8 -// CHECK8-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK8-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP12:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP12]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP13]]) #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK8-SAME: (%class.anon* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK8-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon*, %class.anon** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], %class.anon* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 -// CHECK8-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8 -// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 -// CHECK8-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK8-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8 -// CHECK8-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8 -// CHECK8-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP3]], align 8 -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 -// CHECK8-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK8-NEXT: store i32 [[INC5]], i32* [[TMP19]], align 4 -// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4 -// CHECK8-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP21]], -1 -// CHECK8-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4 -// CHECK8-NEXT: [[TMP22:%.*]] = load i32*, i32** [[_TMP4]], align 8 -// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 -// CHECK8-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP23]], 1 -// CHECK8-NEXT: store i32 [[DIV7]], i32* [[TMP22]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK8-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK8-NEXT: [[A2:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[_TMP4:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK8-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 0.000000e+00, double* [[A]], align 8 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[A3]], double** [[A2]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load double*, double** [[A2]], align 8 -// CHECK8-NEXT: store double* [[TMP0]], double** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP1]], double** [[_TMP4]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP4:%.*]] = load double*, double** [[_TMP4]], align 8 -// CHECK8-NEXT: store double* [[TMP4]], double** [[TMP3]], align 8 -// CHECK8-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: ret void -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR9]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK8-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK8-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SST* [[TMP1]], %struct.SST** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 -// CHECK8-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK8-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK8-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR8]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: [[_TMP2:%.*]] = alloca double*, align 8 -// CHECK8-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[TMP5]], align 8 -// CHECK8-NEXT: store double* [[TMP6]], double** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load double*, double** [[TMP]], align 8 -// CHECK8-NEXT: store double* [[TMP7]], double** [[_TMP2]], align 8 -// CHECK8-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load double, double* [[TMP8]], align 8 -// CHECK8-NEXT: [[INC3:%.*]] = fadd double [[TMP9]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC3]], double* [[TMP8]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG6:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG9:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG12:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG9]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK9-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG13:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]), !dbg [[DBG14:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG15:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK9-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG16:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG17:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG18:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG19:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG20:![0-9]+]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG20]] -// CHECK9-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG20]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG20]] -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[CLASS_TESTCLASS]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), !dbg [[DBG20]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG20]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG22:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG22]] -// CHECK9: lpad: -// CHECK9-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: cleanup, !dbg [[DBG23:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG23]] -// CHECK9-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG23]] -// CHECK9-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1, !dbg [[DBG23]] -// CHECK9-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG23]] -// CHECK9-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ARRAYCTOR_CUR]], !dbg [[DBG20]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG20]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG20]] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG20]] -// CHECK9-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG20]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), !dbg [[DBG20]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG20]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG20]] -// CHECK9: eh.resume: -// CHECK9-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG20]] -// CHECK9-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG20]] -// CHECK9-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG20]] -// CHECK9-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG20]] -// CHECK9-NEXT: resume { i8*, i32 } [[LPAD_VAL2]], !dbg [[DBG20]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG24:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG25:![0-9]+]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]] -// CHECK9-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), !dbg [[DBG25]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void, !dbg [[DBG25]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z3foov -// CHECK9-SAME: () #[[ATTR4:[0-9]+]] !dbg [[DBG26:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG27:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG28:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG29:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK9-NEXT: [[A2:%.*]] = alloca [2 x i8], align 1 -// CHECK9-NEXT: [[C:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 8 -// CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK9-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]), !dbg [[DBG31:![0-9]+]] -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)), !dbg [[DBG32:![0-9]+]] -// CHECK9-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG33:![0-9]+]] -// CHECK9-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG34:![0-9]+]] -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG35:![0-9]+]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1, !dbg [[DBG36:![0-9]+]] -// CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32, !dbg [[DBG36]] -// CHECK9-NEXT: ret i32 [[CONV]], !dbg [[DBG37:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG35]] -// CHECK9-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG35]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP2]]) #[[ATTR9:[0-9]+]], !dbg [[DBG35]] -// CHECK9-NEXT: unreachable, !dbg [[DBG35]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK9-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG38:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]), !dbg [[DBG39:![0-9]+]] -// CHECK9-NEXT: ret void, !dbg [[DBG40:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG41:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8, !dbg [[DBG42:![0-9]+]] -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG42]] -// CHECK9-NEXT: ret void, !dbg [[DBG43:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] { -// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3]] -// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] -// CHECK9-NEXT: unreachable -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK9-SAME: () #[[ATTR8:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG44:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG45:![0-9]+]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: ret void, !dbg [[DBG46:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG45]] -// CHECK9-NEXT: [[TMP1:%.*]] = extractvalue { i8*, i32 } [[TMP0]], 0, !dbg [[DBG45]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP1]]) #[[ATTR9]], !dbg [[DBG45]] -// CHECK9-NEXT: unreachable, !dbg [[DBG45]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK9-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG47:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[THIS1]], i32 0, i32 0, !dbg [[DBG48:![0-9]+]] -// CHECK9-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG48]] -// CHECK9-NEXT: ret void, !dbg [[DBG49:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK9-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG50:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 -// CHECK9-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: ret void, !dbg [[DBG51:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG52:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[B4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[C7:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP11:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0, !dbg [[DBG53:![0-9]+]] -// CHECK9-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG53]] -// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1, !dbg [[DBG54:![0-9]+]] -// CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4, !dbg [[DBG54]] -// CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG54]] -// CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4, !dbg [[DBG54]] -// CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2, !dbg [[DBG55:![0-9]+]] -// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8, !dbg [[DBG56:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8, !dbg [[DBG55]] -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0, !dbg [[DBG57:![0-9]+]] -// CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8, !dbg [[DBG57]] -// CHECK9-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1, !dbg [[DBG58:![0-9]+]] -// CHECK9-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4, !dbg [[DBG58]] -// CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4, !dbg [[DBG58]] -// CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4, !dbg [[DBG58]] -// CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32, !dbg [[DBG58]] -// CHECK9-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4, !dbg [[DBG58]] -// CHECK9-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2, !dbg [[DBG59:![0-9]+]] -// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8, !dbg [[DBG59]] -// CHECK9-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8, !dbg [[DBG59]] -// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8, !dbg [[DBG60:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP2]], i32** [[TMP]], align 8, !dbg [[DBG61:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[C7]], align 8, !dbg [[DBG62:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP3]], i32** [[_TMP9]], align 8, !dbg [[DBG61]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP]], align 8, !dbg [[DBG63:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP4]], i32** [[_TMP10]], align 8, !dbg [[DBG64:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP9]], align 8, !dbg [[DBG65:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP5]], i32** [[_TMP11]], align 8, !dbg [[DBG64]] -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0, !dbg [[DBG66:![0-9]+]] -// CHECK9-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP6]], align 8, !dbg [[DBG66]] -// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG66]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP10]], align 8, !dbg [[DBG67:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP8]], i32** [[TMP7]], align 8, !dbg [[DBG66]] -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2, !dbg [[DBG66]] -// CHECK9-NEXT: store i32* [[B4]], i32** [[TMP9]], align 8, !dbg [[DBG66]] -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3, !dbg [[DBG66]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP11]], align 8, !dbg [[DBG67]] -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !dbg [[DBG66]] -// CHECK9-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG66]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: ret void, !dbg [[DBG68:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP12:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG66]] -// CHECK9-NEXT: [[TMP13:%.*]] = extractvalue { i8*, i32 } [[TMP12]], 0, !dbg [[DBG66]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP13]]) #[[ATTR9]], !dbg [[DBG66]] -// CHECK9-NEXT: unreachable, !dbg [[DBG66]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK9-SAME: (%class.anon* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR8]] align 2 !dbg [[DBG69:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32*, align 8 -// CHECK9-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.anon*, %class.anon** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], %class.anon* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1, !dbg [[DBG70:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8, !dbg [[DBG70]] -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4, !dbg [[DBG71:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG71]] -// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4, !dbg [[DBG71]] -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2, !dbg [[DBG72:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8, !dbg [[DBG72]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4, !dbg [[DBG73:![0-9]+]] -// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1, !dbg [[DBG73]] -// CHECK9-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4, !dbg [[DBG73]] -// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3, !dbg [[DBG74:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8, !dbg [[DBG74]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG75:![0-9]+]] -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1, !dbg [[DBG75]] -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4, !dbg [[DBG75]] -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1, !dbg [[DBG76:![0-9]+]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8, !dbg [[DBG76]] -// CHECK9-NEXT: store i32* [[TMP12]], i32** [[TMP]], align 8, !dbg [[DBG77:![0-9]+]] -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 2, !dbg [[DBG78:![0-9]+]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32*, i32** [[TMP13]], align 8, !dbg [[DBG78]] -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 3, !dbg [[DBG79:![0-9]+]] -// CHECK9-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8, !dbg [[DBG79]] -// CHECK9-NEXT: store i32* [[TMP16]], i32** [[_TMP2]], align 8, !dbg [[DBG77]] -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[TMP]], align 8, !dbg [[DBG80:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP17]], i32** [[_TMP3]], align 8, !dbg [[DBG81:![0-9]+]] -// CHECK9-NEXT: [[TMP18:%.*]] = load i32*, i32** [[_TMP2]], align 8, !dbg [[DBG82:![0-9]+]] -// CHECK9-NEXT: store i32* [[TMP18]], i32** [[_TMP4]], align 8, !dbg [[DBG81]] -// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[_TMP3]], align 8, !dbg [[DBG80]] -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4, !dbg [[DBG83:![0-9]+]] -// CHECK9-NEXT: [[INC5:%.*]] = add nsw i32 [[TMP20]], 1, !dbg [[DBG83]] -// CHECK9-NEXT: store i32 [[INC5]], i32* [[TMP19]], align 4, !dbg [[DBG83]] -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP14]], align 4, !dbg [[DBG84:![0-9]+]] -// CHECK9-NEXT: [[DEC6:%.*]] = add nsw i32 [[TMP21]], -1, !dbg [[DBG84]] -// CHECK9-NEXT: store i32 [[DEC6]], i32* [[TMP14]], align 4, !dbg [[DBG84]] -// CHECK9-NEXT: [[TMP22:%.*]] = load i32*, i32** [[_TMP4]], align 8, !dbg [[DBG82]] -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4, !dbg [[DBG85:![0-9]+]] -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP23]], 1, !dbg [[DBG85]] -// CHECK9-NEXT: store i32 [[DIV7]], i32* [[TMP22]], align 4, !dbg [[DBG85]] -// CHECK9-NEXT: ret void, !dbg [[DBG86:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK9-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG87:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK9-NEXT: [[A2:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[_TMP4:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0, !dbg [[DBG88:![0-9]+]] -// CHECK9-NEXT: store double 0.000000e+00, double* [[A]], align 8, !dbg [[DBG88]] -// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0, !dbg [[DBG89:![0-9]+]] -// CHECK9-NEXT: store double* [[A3]], double** [[A2]], align 8, !dbg [[DBG89]] -// CHECK9-NEXT: [[TMP0:%.*]] = load double*, double** [[A2]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP0]], double** [[TMP]], align 8, !dbg [[DBG91:![0-9]+]] -// CHECK9-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP]], align 8, !dbg [[DBG92:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP1]], double** [[_TMP4]], align 8, !dbg [[DBG93:![0-9]+]] -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0, !dbg [[DBG94:![0-9]+]] -// CHECK9-NEXT: store %struct.SST* [[THIS1]], %struct.SST** [[TMP2]], align 8, !dbg [[DBG94]] -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG94]] -// CHECK9-NEXT: [[TMP4:%.*]] = load double*, double** [[_TMP4]], align 8, !dbg [[DBG95:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP4]], double** [[TMP3]], align 8, !dbg [[DBG94]] -// CHECK9-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG94]] -// CHECK9: invoke.cont: -// CHECK9-NEXT: ret void, !dbg [[DBG96:![0-9]+]] -// CHECK9: terminate.lpad: -// CHECK9-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// CHECK9-NEXT: catch i8* null, !dbg [[DBG94]] -// CHECK9-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0, !dbg [[DBG94]] -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR9]], !dbg [[DBG94]] -// CHECK9-NEXT: unreachable, !dbg [[DBG94]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK9-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 !dbg [[DBG97:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK9-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0, !dbg [[DBG98:![0-9]+]] -// CHECK9-NEXT: store %struct.SST* [[TMP1]], %struct.SST** [[TMP2]], align 8, !dbg [[DBG98]] -// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG98]] -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1, !dbg [[DBG99:![0-9]+]] -// CHECK9-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8, !dbg [[DBG99]] -// CHECK9-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8, !dbg [[DBG98]] -// CHECK9-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]), !dbg [[DBG98]] -// CHECK9-NEXT: ret void, !dbg [[DBG100:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK9-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR8]] align 2 !dbg [[DBG101:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[_TMP2:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %class.anon.1*, %class.anon.1** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1:%.*]], %class.anon.1* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SST*, %struct.SST** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1, !dbg [[DBG102:![0-9]+]] -// CHECK9-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP2]], align 8, !dbg [[DBG102]] -// CHECK9-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8, !dbg [[DBG103:![0-9]+]] -// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG103]] -// CHECK9-NEXT: store double [[INC]], double* [[TMP3]], align 8, !dbg [[DBG103]] -// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[THIS1]], i32 0, i32 1, !dbg [[DBG104:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[TMP5]], align 8, !dbg [[DBG104]] -// CHECK9-NEXT: store double* [[TMP6]], double** [[TMP]], align 8, !dbg [[DBG105:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load double*, double** [[TMP]], align 8, !dbg [[DBG106:![0-9]+]] -// CHECK9-NEXT: store double* [[TMP7]], double** [[_TMP2]], align 8, !dbg [[DBG107:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8, !dbg [[DBG106]] -// CHECK9-NEXT: [[TMP9:%.*]] = load double, double* [[TMP8]], align 8, !dbg [[DBG108:![0-9]+]] -// CHECK9-NEXT: [[INC3:%.*]] = fadd double [[TMP9]], 1.000000e+00, !dbg [[DBG108]] -// CHECK9-NEXT: store double [[INC3]], double* [[TMP8]], align 8, !dbg [[DBG108]] -// CHECK9-NEXT: ret void, !dbg [[DBG109:![0-9]+]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG110:![0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG111:![0-9]+]] -// CHECK9-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG111]] -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St -// CHECK10-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK10-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK10-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/single_firstprivate_codegen.cpp b/clang/test/OpenMP/single_firstprivate_codegen.cpp --- a/clang/test/OpenMP/single_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/single_firstprivate_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1500,835 +1500,4 @@ // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: store i32 41, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: store i32 41, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 1, i32* @g, align 4 -// CHECK8-NEXT: store i32 37, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 31, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/single_private_codegen.cpp b/clang/test/OpenMP/single_private_codegen.cpp --- a/clang/test/OpenMP/single_private_codegen.cpp +++ b/clang/test/OpenMP/single_private_codegen.cpp @@ -5,11 +5,11 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -848,626 +848,4 @@ // CHECK4-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: store i32 303, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done7: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK5: arraydestroy.body9: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK5: arraydestroy.done13: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: store i32 303, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done7: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK6: arraydestroy.body9: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK6: arraydestroy.done13: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: store double 1.000000e+00, double* [[G]], align 8 -// CHECK8-NEXT: store i32 101, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile double, double* [[G]], align 8 -// CHECK8-NEXT: store volatile double [[TMP0]], double* [[BLOCK_CAPTURED]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* -// CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// CHECK8-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// CHECK8-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_codegen_global_capture.cpp b/clang/test/OpenMP/target_codegen_global_capture.cpp --- a/clang/test/OpenMP/target_codegen_global_capture.cpp +++ b/clang/test/OpenMP/target_codegen_global_capture.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -3897,835 +3897,4 @@ // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK5-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK5-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK5-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK5-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK5-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK5-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK5-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK5-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK5-NEXT: ret i32 [[ADD27]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK5-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK5-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK5-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK5-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK5-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK5-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK5-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK5-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK5-NEXT: ret i32 [[ADD27]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK5-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK5-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK5-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK5-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK5-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK5-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK5-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK5-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK5-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK5-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK5-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK5-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK5-NEXT: ret i32 [[ADD27]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK6-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK6-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK6-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK6-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK6-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK6-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK6-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK6-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK6-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK6-NEXT: ret i32 [[ADD27]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK6-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK6-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK6-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK6-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK6-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK6-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK6-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK6-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK6-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK6-NEXT: ret i32 [[ADD27]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK6-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK6-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK6-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK6-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK6-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK6-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK6-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK6-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK6-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK6-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK6-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK6-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK6-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK6-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK6-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK6-NEXT: ret i32 [[ADD27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK7-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK7-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK7-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK7-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK7-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK7-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK7-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK7-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK7-NEXT: ret i32 [[ADD27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK7-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK7-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK7-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK7-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK7-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK7-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK7-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK7-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK7-NEXT: ret i32 [[ADD27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK7-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK7-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK7-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK7-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK7-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK7-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK7-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK7-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK7-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK7-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK7-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK7-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK7-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK7-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK7-NEXT: ret i32 [[ADD27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK8-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK8-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK8-NEXT: store float [[CONV5]], float* @_ZZ3foossssE2Sb, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* @_ZZ3foossssE2Sd, align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4 -// CHECK8-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4 -// CHECK8-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK8-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4 -// CHECK8-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK8-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK8-NEXT: ret i32 [[ADD27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK8-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK8-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK8-NEXT: store float [[CONV5]], float* @_ZZ3barssssE2Sb, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* @_ZZ3barssssE2Sd, align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4 -// CHECK8-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4 -// CHECK8-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK8-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4 -// CHECK8-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK8-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK8-NEXT: ret i32 [[ADD27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK8-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK8-NEXT: store i16 [[CONV1]], i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load double, double* @Gb, align 8 -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[TMP1]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD2]], double* @Gb, align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK8-NEXT: [[CONV3:%.*]] = fpext float [[TMP2]] to double -// CHECK8-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00 -// CHECK8-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float -// CHECK8-NEXT: store float [[CONV5]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load double, double* @Gd, align 8 -// CHECK8-NEXT: [[ADD9:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD9]], double* @Gd, align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP5]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i16, i16* [[A_ADDR]], align 2 -// CHECK8-NEXT: [[CONV13:%.*]] = sext i16 [[TMP6]] to i32 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[B_ADDR]], align 2 -// CHECK8-NEXT: [[CONV14:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV13]], [[CONV14]] -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2 -// CHECK8-NEXT: [[CONV16:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]] -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4 -// CHECK8-NEXT: [[CONV20:%.*]] = fptosi float [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]] -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4 -// CHECK8-NEXT: [[CONV22:%.*]] = fptosi float [[TMP11]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]] -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = fptosi float [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]] -// CHECK8-NEXT: [[TMP13:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4 -// CHECK8-NEXT: [[CONV26:%.*]] = fptosi float [[TMP13]] to i32 -// CHECK8-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]] -// CHECK8-NEXT: ret i32 [[ADD27]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_map_codegen_03.cpp b/clang/test/OpenMP/target_map_codegen_03.cpp --- a/clang/test/OpenMP/target_map_codegen_03.cpp +++ b/clang/test/OpenMP/target_map_codegen_03.cpp @@ -25,12 +25,12 @@ // RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -1040,59 +1040,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK13-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK14-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK15-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK16-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp --- a/clang/test/OpenMP/target_parallel_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 @@ -41,12 +41,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -59,13 +59,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -4359,888 +4359,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK5-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK5-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK5-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK5-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK5-NEXT: ret i32 [[TMP18]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK5-NEXT: ret i32 [[ADD9]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK6-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK6-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK6-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK6-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK6-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK6-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK6-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK6-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK6-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK6-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK6-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK6-NEXT: ret i32 [[TMP18]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK6-NEXT: ret i32 [[ADD9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK7-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK7-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK7-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK7-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK7-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK7-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK7-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK7-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK7-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK7-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK7-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK7-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK7-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK7-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK7-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK7-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK7-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK7-NEXT: ret i32 [[TMP16]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK7-NEXT: ret i32 [[ADD9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP4]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK8-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK8-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK8-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK8-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK8-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK8-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK8-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK8-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK8-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK8-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK8-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK8-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK8-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK8-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK8-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK8-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK8-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK8-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK8-NEXT: ret i32 [[TMP16]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK8-NEXT: ret i32 [[ADD9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP4]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -6863,888 +5981,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK13-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK13-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK13-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK13-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK13-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK13-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK13-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK13-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK13-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK13-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK13-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK13-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK13-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK13-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK13-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK13-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK13-NEXT: ret i32 [[ADD9]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK14-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK14-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK14-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK14-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK14-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK14-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK14-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK14-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK14-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK14-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK14-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK14-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK14-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK14-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK14-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK14-NEXT: ret i32 [[ADD9]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK15-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK15-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK15-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK15-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK15-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK15-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK15-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK15-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK15-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK15-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK15-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK15-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK15-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK15-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK15-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK15-NEXT: ret i32 [[TMP16]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK15-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK15-NEXT: ret i32 [[ADD9]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP4]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK16-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK16-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK16-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK16-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK16-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK16-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK16-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK16-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK16-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK16-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK16-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK16-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK16-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK16-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK16-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK16-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK16-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK16-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK16-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK16-NEXT: ret i32 [[TMP16]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK16-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK16-NEXT: ret i32 [[ADD9]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP4]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -11813,888 +10049,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK21-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK21-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK21-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK21-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK21-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK21-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK21-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK21-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK21-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK21-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK21-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK21-NEXT: ret i32 [[TMP18]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK21-NEXT: ret i32 [[ADD9]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK22-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK22-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK22-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK22-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK22-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK22-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK22-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK22-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK22-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK22-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK22-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK22-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK22-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK22-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK22-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK22-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK22-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK22-NEXT: ret i32 [[TMP18]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK22-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK22-NEXT: ret i32 [[ADD9]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK23-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK23-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK23-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK23-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK23-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK23-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK23-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK23-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK23-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK23-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK23-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK23-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK23-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK23-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK23-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK23-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK23-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK23-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK23-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK23-NEXT: ret i32 [[TMP16]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK23-NEXT: ret i32 [[ADD9]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK24-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK24-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK24-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK24-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK24-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK24-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK24-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK24-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK24-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK24-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK24-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK24-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK24-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK24-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK24-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK24-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK24-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK24-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK24-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK24-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK24-NEXT: ret i32 [[TMP16]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK24-NEXT: ret i32 [[ADD9]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -14316,885 +11670,4 @@ // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK29-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK29-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK29-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK29-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK29-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK29-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK29-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK29-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK29-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK29-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK29-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK29-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK29-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK29-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK29-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK29-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK29-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK29-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK29-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK29-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK29-NEXT: ret i32 [[TMP18]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK29-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK29-NEXT: ret i32 [[ADD9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK30-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK30-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK30-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK30-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV9:%.*]] = fpext float [[TMP11]] to double -// CHECK30-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK30-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK30-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK30-NEXT: [[CONV13:%.*]] = fpext float [[TMP12]] to double -// CHECK30-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK30-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK30-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK30-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK30-NEXT: [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK30-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]] -// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 -// CHECK30-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK30-NEXT: [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK30-NEXT: store i64 [[ADD22]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV23:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK30-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK30-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK30-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8 -// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK30-NEXT: ret i32 [[TMP18]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK30-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK30-NEXT: ret i32 [[ADD9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK31-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK31-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK31-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK31-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK31-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK31-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK31-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK31-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK31-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK31-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK31-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK31-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK31-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK31-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK31-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK31-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK31-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK31-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK31-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK31-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK31-NEXT: ret i32 [[TMP16]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK31-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK31-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK31-NEXT: ret i32 [[ADD9]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 -// CHECK32-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV5:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 -// CHECK32-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 -// CHECK32-NEXT: store i16 [[CONV7]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK32-NEXT: store i32 [[ADD8]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV9:%.*]] = fpext float [[TMP9]] to double -// CHECK32-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 -// CHECK32-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float -// CHECK32-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4 -// CHECK32-NEXT: [[CONV13:%.*]] = fpext float [[TMP10]] to double -// CHECK32-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 -// CHECK32-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float -// CHECK32-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4 -// CHECK32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8 -// CHECK32-NEXT: [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8 -// CHECK32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]] -// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3 -// CHECK32-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8 -// CHECK32-NEXT: [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1 -// CHECK32-NEXT: store i64 [[ADD22]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV23:%.*]] = sext i8 [[TMP15]] to i32 -// CHECK32-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 -// CHECK32-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 -// CHECK32-NEXT: store i8 [[CONV25]], i8* [[Y]], align 4 -// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK32-NEXT: ret i32 [[TMP16]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK32-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK32-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK32-NEXT: ret i32 [[ADD9]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 @@ -41,12 +41,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -59,13 +59,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -6824,1448 +6824,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: ret i64 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK5-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK5-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end8: -// CHECK5-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK5-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND9:%.*]] -// CHECK5: for.cond9: -// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK5-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK5: for.body11: -// CHECK5-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK5-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC14:%.*]] -// CHECK5: for.inc14: -// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end15: -// CHECK5-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK5-NEXT: br label [[FOR_COND17:%.*]] -// CHECK5: for.cond17: -// CHECK5-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK5-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK5-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK5-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK5: for.body20: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK5-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK5-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC25:%.*]] -// CHECK5: for.inc25: -// CHECK5-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK5-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK5-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK5-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK5-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK5-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end29: -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK5-NEXT: br label [[FOR_COND31:%.*]] -// CHECK5: for.cond31: -// CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK5-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK5-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK5: for.body34: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK5-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK5-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK5-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK5-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK5-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK5-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK5-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK5-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK5-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK5-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK5-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK5-NEXT: br label [[FOR_INC53:%.*]] -// CHECK5: for.inc53: -// CHECK5-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK5-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK5-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK5-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK5-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK5-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK5: for.end57: -// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK5-NEXT: ret i32 [[TMP29]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK5-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK5-NEXT: ret i32 [[ADD9]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK5-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK5-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: ret i64 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK6-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK6-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end8: -// CHECK6-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK6-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND9:%.*]] -// CHECK6: for.cond9: -// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK6-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK6: for.body11: -// CHECK6-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK6-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC14:%.*]] -// CHECK6: for.inc14: -// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end15: -// CHECK6-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK6-NEXT: br label [[FOR_COND17:%.*]] -// CHECK6: for.cond17: -// CHECK6-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK6-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK6-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK6-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK6: for.body20: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK6-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK6-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC25:%.*]] -// CHECK6: for.inc25: -// CHECK6-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK6-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK6-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK6-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK6-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK6-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end29: -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK6-NEXT: br label [[FOR_COND31:%.*]] -// CHECK6: for.cond31: -// CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK6-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK6-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK6: for.body34: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK6-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK6-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK6-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK6-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK6-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK6-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK6-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK6-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK6-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK6-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK6-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK6-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK6-NEXT: br label [[FOR_INC53:%.*]] -// CHECK6: for.inc53: -// CHECK6-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK6-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK6-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK6-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK6-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK6-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK6: for.end57: -// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK6-NEXT: ret i32 [[TMP29]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK6-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK6-NEXT: ret i32 [[ADD9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK6-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK6-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: ret i64 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK7-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK7-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK7-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK7-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC14:%.*]] -// CHECK7: for.inc14: -// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end15: -// CHECK7-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK7-NEXT: br label [[FOR_COND17:%.*]] -// CHECK7: for.cond17: -// CHECK7-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK7-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK7-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK7-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK7: for.body20: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK7-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK7-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK7-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC25:%.*]] -// CHECK7: for.inc25: -// CHECK7-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK7-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK7-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK7-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK7-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK7-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end29: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK7-NEXT: br label [[FOR_COND31:%.*]] -// CHECK7: for.cond31: -// CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK7-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK7-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK7-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK7: for.body34: -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK7-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK7-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK7-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK7-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK7-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK7-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK7-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK7-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK7-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK7-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK7-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK7-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK7-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK7-NEXT: br label [[FOR_INC53:%.*]] -// CHECK7: for.inc53: -// CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK7-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK7-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK7-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK7-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK7-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end57: -// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK7-NEXT: ret i32 [[TMP27]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK7-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: ret i32 [[ADD9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK7-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK7-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP5]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: ret i64 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK8-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK8-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK8-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK8-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC14:%.*]] -// CHECK8: for.inc14: -// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK8-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end15: -// CHECK8-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK8-NEXT: br label [[FOR_COND17:%.*]] -// CHECK8: for.cond17: -// CHECK8-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK8-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK8-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK8-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK8: for.body20: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK8-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK8-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC25:%.*]] -// CHECK8: for.inc25: -// CHECK8-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK8-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK8-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK8-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK8-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK8-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end29: -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK8-NEXT: br label [[FOR_COND31:%.*]] -// CHECK8: for.cond31: -// CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK8-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK8-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK8-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK8: for.body34: -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK8-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK8-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK8-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK8-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK8-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK8-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK8-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK8-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK8-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK8-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK8-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK8-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK8-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK8-NEXT: br label [[FOR_INC53:%.*]] -// CHECK8: for.inc53: -// CHECK8-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK8-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK8-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK8-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK8-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK8-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end57: -// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK8-NEXT: ret i32 [[TMP27]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK8-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK8-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK8-NEXT: ret i32 [[ADD9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK8-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK8-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP5]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -11474,1448 +10032,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: ret i64 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK13-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK13-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK13-NEXT: br label [[FOR_COND3:%.*]] -// CHECK13: for.cond3: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK13-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body5: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK13-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK13-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND9:%.*]] -// CHECK13: for.cond9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK13-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK13: for.body11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK13-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC14:%.*]] -// CHECK13: for.inc14: -// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end15: -// CHECK13-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK13-NEXT: br label [[FOR_COND17:%.*]] -// CHECK13: for.cond17: -// CHECK13-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK13-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK13-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK13-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK13: for.body20: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK13-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK13-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK13-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC25:%.*]] -// CHECK13: for.inc25: -// CHECK13-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK13-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK13-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK13-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK13-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK13-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end29: -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK13-NEXT: br label [[FOR_COND31:%.*]] -// CHECK13: for.cond31: -// CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK13-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK13-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK13-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK13: for.body34: -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK13-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK13-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK13-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK13-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK13-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK13-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK13-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK13-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK13-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK13-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK13-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK13-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK13-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK13-NEXT: br label [[FOR_INC53:%.*]] -// CHECK13: for.inc53: -// CHECK13-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK13-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK13-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK13-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK13-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK13-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end57: -// CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK13-NEXT: ret i32 [[TMP29]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK13-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK13-NEXT: ret i32 [[ADD9]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK13-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK13-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: ret i64 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK14-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK14-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3:%.*]] -// CHECK14: for.cond3: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK14-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body5: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK14-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND9:%.*]] -// CHECK14: for.cond9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK14-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK14: for.body11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK14-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC14:%.*]] -// CHECK14: for.inc14: -// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK14-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end15: -// CHECK14-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK14-NEXT: br label [[FOR_COND17:%.*]] -// CHECK14: for.cond17: -// CHECK14-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK14-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK14-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK14-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK14: for.body20: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK14-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK14-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK14-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC25:%.*]] -// CHECK14: for.inc25: -// CHECK14-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK14-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK14-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK14-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK14-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK14-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end29: -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK14-NEXT: br label [[FOR_COND31:%.*]] -// CHECK14: for.cond31: -// CHECK14-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK14-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK14-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK14-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK14: for.body34: -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK14-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK14-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK14-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK14-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK14-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK14-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK14-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK14-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK14-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK14-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK14-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK14-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK14-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK14-NEXT: br label [[FOR_INC53:%.*]] -// CHECK14: for.inc53: -// CHECK14-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK14-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK14-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK14-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK14-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK14-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end57: -// CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK14-NEXT: ret i32 [[TMP29]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK14-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK14-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK14-NEXT: ret i32 [[ADD9]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK14-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK14-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: ret i64 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK15-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK15-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3:%.*]] -// CHECK15: for.cond3: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK15-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body5: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: br label [[FOR_INC7:%.*]] -// CHECK15: for.inc7: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK15-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK15-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK15-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end15: -// CHECK15-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK15-NEXT: br label [[FOR_COND17:%.*]] -// CHECK15: for.cond17: -// CHECK15-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK15-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK15-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK15-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK15: for.body20: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK15-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK15-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK15-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK15-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC25:%.*]] -// CHECK15: for.inc25: -// CHECK15-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK15-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK15-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK15-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK15-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK15-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end29: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK15-NEXT: br label [[FOR_COND31:%.*]] -// CHECK15: for.cond31: -// CHECK15-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK15-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK15-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK15-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK15: for.body34: -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK15-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK15-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK15-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK15-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK15-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK15-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK15-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK15-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK15-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK15-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK15-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK15-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK15-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK15-NEXT: br label [[FOR_INC53:%.*]] -// CHECK15: for.inc53: -// CHECK15-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK15-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK15-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK15-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK15-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK15-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end57: -// CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK15-NEXT: ret i32 [[TMP27]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK15-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK15-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK15-NEXT: ret i32 [[ADD9]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK15-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK15-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: ret i64 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK16-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK16-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3:%.*]] -// CHECK16: for.cond3: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK16-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body5: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: br label [[FOR_INC7:%.*]] -// CHECK16: for.inc7: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK16-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK16-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK16-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK16-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end15: -// CHECK16-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK16-NEXT: br label [[FOR_COND17:%.*]] -// CHECK16: for.cond17: -// CHECK16-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK16-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK16-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK16-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK16: for.body20: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK16-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK16-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK16-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK16-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC25:%.*]] -// CHECK16: for.inc25: -// CHECK16-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK16-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK16-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK16-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK16-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK16-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end29: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK16-NEXT: br label [[FOR_COND31:%.*]] -// CHECK16: for.cond31: -// CHECK16-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK16-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK16-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK16-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK16: for.body34: -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK16-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK16-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK16-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK16-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK16-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK16-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK16-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK16-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK16-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK16-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK16-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK16-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK16-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK16-NEXT: br label [[FOR_INC53:%.*]] -// CHECK16: for.inc53: -// CHECK16-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK16-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK16-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK16-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK16-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK16-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end57: -// CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK16-NEXT: ret i32 [[TMP27]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK16-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK16-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK16-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK16-NEXT: ret i32 [[ADD9]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK16-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK16-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -19424,1448 +16540,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: ret i64 0 -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK21-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK21-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK21-NEXT: br label [[FOR_COND3:%.*]] -// CHECK21: for.cond3: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK21-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK21-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK21: for.body5: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK21-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK21-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK21-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end8: -// CHECK21-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK21-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND9:%.*]] -// CHECK21: for.cond9: -// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK21-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK21: for.body11: -// CHECK21-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK21-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC14:%.*]] -// CHECK21: for.inc14: -// CHECK21-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end15: -// CHECK21-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK21-NEXT: br label [[FOR_COND17:%.*]] -// CHECK21: for.cond17: -// CHECK21-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK21-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK21-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK21-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK21: for.body20: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK21-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK21-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK21-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK21-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK21-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK21-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK21-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end29: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK21-NEXT: br label [[FOR_COND31:%.*]] -// CHECK21: for.cond31: -// CHECK21-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK21-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK21-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK21-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK21: for.body34: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK21-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK21-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK21-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK21-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK21-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK21-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK21-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK21-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK21-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK21-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK21-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK21-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK21-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK21-NEXT: br label [[FOR_INC53:%.*]] -// CHECK21: for.inc53: -// CHECK21-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK21-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK21-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK21-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK21-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK21-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end57: -// CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK21-NEXT: ret i32 [[TMP29]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK21-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK21-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK21-NEXT: ret i32 [[ADD9]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK21-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK21-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP5]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: ret i64 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK22-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK22-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK22-NEXT: br label [[FOR_COND3:%.*]] -// CHECK22: for.cond3: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK22-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK22-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK22: for.body5: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK22-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK22-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK22-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end8: -// CHECK22-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK22-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND9:%.*]] -// CHECK22: for.cond9: -// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK22-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK22: for.body11: -// CHECK22-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK22-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK22-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC14:%.*]] -// CHECK22: for.inc14: -// CHECK22-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end15: -// CHECK22-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK22-NEXT: br label [[FOR_COND17:%.*]] -// CHECK22: for.cond17: -// CHECK22-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK22-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK22-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK22-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK22: for.body20: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK22-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK22-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK22-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK22-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK22-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK22-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK22-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK22-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end29: -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK22-NEXT: br label [[FOR_COND31:%.*]] -// CHECK22: for.cond31: -// CHECK22-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK22-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK22-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK22-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK22: for.body34: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK22-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK22-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK22-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK22-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK22-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK22-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK22-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK22-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK22-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK22-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK22-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK22-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK22-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK22-NEXT: br label [[FOR_INC53:%.*]] -// CHECK22: for.inc53: -// CHECK22-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK22-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK22-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK22-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK22-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK22-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end57: -// CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK22-NEXT: ret i32 [[TMP29]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK22-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK22-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK22-NEXT: ret i32 [[ADD9]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK22-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK22-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP5]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: ret i64 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK23-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK23-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK23-NEXT: br label [[FOR_COND3:%.*]] -// CHECK23: for.cond3: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK23-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK23-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body5: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: br label [[FOR_INC7:%.*]] -// CHECK23: for.inc7: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK23-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK23-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK23-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK23-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND9:%.*]] -// CHECK23: for.cond9: -// CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK23-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK23: for.body11: -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK23-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end15: -// CHECK23-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK23-NEXT: br label [[FOR_COND17:%.*]] -// CHECK23: for.cond17: -// CHECK23-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK23-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK23-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK23-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK23-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC25:%.*]] -// CHECK23: for.inc25: -// CHECK23-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK23-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK23-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK23-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK23-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK23-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end29: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK23-NEXT: br label [[FOR_COND31:%.*]] -// CHECK23: for.cond31: -// CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK23-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK23-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK23-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK23: for.body34: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK23-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK23-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK23-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK23-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK23-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK23-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK23-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK23-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK23-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK23-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK23-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK23-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK23-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK23-NEXT: br label [[FOR_INC53:%.*]] -// CHECK23: for.inc53: -// CHECK23-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK23-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK23-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK23-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK23-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK23-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end57: -// CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK23-NEXT: ret i32 [[TMP27]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK23-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK23-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK23-NEXT: ret i32 [[ADD9]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK23-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK23-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP5]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: ret i64 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK24-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK24-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK24-NEXT: br label [[FOR_COND3:%.*]] -// CHECK24: for.cond3: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK24-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK24-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body5: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: br label [[FOR_INC7:%.*]] -// CHECK24: for.inc7: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK24-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK24-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK24-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK24-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND9:%.*]] -// CHECK24: for.cond9: -// CHECK24-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK24-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK24: for.body11: -// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK24-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK24-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end15: -// CHECK24-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK24-NEXT: br label [[FOR_COND17:%.*]] -// CHECK24: for.cond17: -// CHECK24-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK24-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK24-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK24-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK24-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC25:%.*]] -// CHECK24: for.inc25: -// CHECK24-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK24-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK24-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK24-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK24-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK24-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end29: -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK24-NEXT: br label [[FOR_COND31:%.*]] -// CHECK24: for.cond31: -// CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK24-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK24-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK24-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK24: for.body34: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK24-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK24-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK24-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK24-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK24-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK24-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK24-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK24-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK24-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK24-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK24-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK24-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK24-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK24-NEXT: br label [[FOR_INC53:%.*]] -// CHECK24: for.inc53: -// CHECK24-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK24-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK24-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK24-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK24-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK24-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end57: -// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK24-NEXT: ret i32 [[TMP27]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK24-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK24-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK24-NEXT: ret i32 [[ADD9]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK24-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK24-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP5]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -24073,1445 +19747,4 @@ // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK29-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: ret i64 0 -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK29-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK29-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK29-NEXT: br label [[FOR_COND3:%.*]] -// CHECK29: for.cond3: -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK29-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK29-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK29: for.body5: -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: br label [[FOR_INC7:%.*]] -// CHECK29: for.inc7: -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK29-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK29-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK29-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end8: -// CHECK29-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK29-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND9:%.*]] -// CHECK29: for.cond9: -// CHECK29-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK29-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK29: for.body11: -// CHECK29-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK29-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK29-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC14:%.*]] -// CHECK29: for.inc14: -// CHECK29-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK29-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK29: for.end15: -// CHECK29-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK29-NEXT: br label [[FOR_COND17:%.*]] -// CHECK29: for.cond17: -// CHECK29-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK29-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK29-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK29-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK29: for.body20: -// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK29-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK29-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK29-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK29-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC25:%.*]] -// CHECK29: for.inc25: -// CHECK29-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK29-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK29-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK29-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK29-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK29-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK29: for.end29: -// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK29-NEXT: br label [[FOR_COND31:%.*]] -// CHECK29: for.cond31: -// CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK29-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK29-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK29-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK29: for.body34: -// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK29-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK29-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK29-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK29-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK29-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK29-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK29-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK29-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK29-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK29-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK29-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK29-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK29-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK29-NEXT: br label [[FOR_INC53:%.*]] -// CHECK29: for.inc53: -// CHECK29-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK29-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK29-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK29-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK29-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK29-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK29: for.end57: -// CHECK29-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK29-NEXT: ret i32 [[TMP29]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK29-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK29-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK29-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK29-NEXT: ret i32 [[ADD9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK29-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK29-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP5]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK30-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: ret i64 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 32 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 5 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK30-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK30-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK30-NEXT: br label [[FOR_COND3:%.*]] -// CHECK30: for.cond3: -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK30-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], 1 -// CHECK30-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK30: for.body5: -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: br label [[FOR_INC7:%.*]] -// CHECK30: for.inc7: -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK30-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP10]], -1 -// CHECK30-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK30-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end8: -// CHECK30-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK30-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND9:%.*]] -// CHECK30: for.cond9: -// CHECK30-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP11]], 600 -// CHECK30-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK30: for.body11: -// CHECK30-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK30-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK30-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC14:%.*]] -// CHECK30: for.inc14: -// CHECK30-NEXT: [[TMP13:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[SUB:%.*]] = sub i64 [[TMP13]], 400 -// CHECK30-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK30: for.end15: -// CHECK30-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK30-NEXT: br label [[FOR_COND17:%.*]] -// CHECK30: for.cond17: -// CHECK30-NEXT: [[TMP14:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK30-NEXT: [[CONV18:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK30-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK30-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK30: for.body20: -// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK30-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV22:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK30-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK30-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK30-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC25:%.*]] -// CHECK30: for.inc25: -// CHECK30-NEXT: [[TMP17:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK30-NEXT: [[CONV26:%.*]] = sext i16 [[TMP17]] to i32 -// CHECK30-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK30-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK30-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK30-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK30: for.end29: -// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK30-NEXT: br label [[FOR_COND31:%.*]] -// CHECK30: for.cond31: -// CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK30-NEXT: [[CONV32:%.*]] = zext i8 [[TMP19]] to i32 -// CHECK30-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK30-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK30: for.body34: -// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK30-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK30-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK30-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK30-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK30-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK30-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK30-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP24]] -// CHECK30-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK30-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK30-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK30-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK30-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK30-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK30-NEXT: br label [[FOR_INC53:%.*]] -// CHECK30: for.inc53: -// CHECK30-NEXT: [[TMP28:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK30-NEXT: [[CONV54:%.*]] = zext i8 [[TMP28]] to i32 -// CHECK30-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK30-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK30-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK30-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK30: for.end57: -// CHECK30-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK30-NEXT: ret i32 [[TMP29]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP5:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP5]], 600 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK30-NEXT: [[SUB:%.*]] = sub i64 [[TMP9]], 400 -// CHECK30-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP12]] -// CHECK30-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK30-NEXT: ret i32 [[ADD9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK30-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK30-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP5]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK31-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: ret i64 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK31-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK31-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK31-NEXT: br label [[FOR_COND3:%.*]] -// CHECK31: for.cond3: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK31-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK31-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK31: for.body5: -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: br label [[FOR_INC7:%.*]] -// CHECK31: for.inc7: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK31-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK31-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK31-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end8: -// CHECK31-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK31-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND9:%.*]] -// CHECK31: for.cond9: -// CHECK31-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK31-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK31: for.body11: -// CHECK31-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK31-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK31-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC14:%.*]] -// CHECK31: for.inc14: -// CHECK31-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK31-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK31: for.end15: -// CHECK31-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK31-NEXT: br label [[FOR_COND17:%.*]] -// CHECK31: for.cond17: -// CHECK31-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK31-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK31-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK31-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK31: for.body20: -// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK31-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK31-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK31-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK31-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC25:%.*]] -// CHECK31: for.inc25: -// CHECK31-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK31-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK31-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK31-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK31-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK31-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK31: for.end29: -// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK31-NEXT: br label [[FOR_COND31:%.*]] -// CHECK31: for.cond31: -// CHECK31-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK31-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK31-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK31-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK31: for.body34: -// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK31-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK31-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK31-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK31-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK31-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK31-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK31-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK31-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK31-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK31-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK31-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK31-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK31-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK31-NEXT: br label [[FOR_INC53:%.*]] -// CHECK31: for.inc53: -// CHECK31-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK31-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK31-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK31-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK31-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK31-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK31: for.end57: -// CHECK31-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK31-NEXT: ret i32 [[TMP27]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK31-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK31-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK31-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK31-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK31-NEXT: ret i32 [[ADD9]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK31-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK31-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP5]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z7get_valv -// CHECK32-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: ret i64 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[K:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[LIN:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: [[IT16:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[IT30:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: store i32 3, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 32 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 5 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() -// CHECK32-NEXT: store i64 [[CALL]], i64* [[K]], align 8 -// CHECK32-NEXT: store i32 10, i32* [[I2]], align 4 -// CHECK32-NEXT: br label [[FOR_COND3:%.*]] -// CHECK32: for.cond3: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], 1 -// CHECK32-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END8:%.*]] -// CHECK32: for.body5: -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: br label [[FOR_INC7:%.*]] -// CHECK32: for.inc7: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK32-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 -// CHECK32-NEXT: store i32 [[DEC]], i32* [[I2]], align 4 -// CHECK32-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end8: -// CHECK32-NEXT: store i32 12, i32* [[LIN]], align 4 -// CHECK32-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND9:%.*]] -// CHECK32: for.cond9: -// CHECK32-NEXT: [[TMP9:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[CMP10:%.*]] = icmp uge i64 [[TMP9]], 600 -// CHECK32-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END15:%.*]] -// CHECK32: for.body11: -// CHECK32-NEXT: [[TMP10:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK32-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16 -// CHECK32-NEXT: store i16 [[CONV13]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC14:%.*]] -// CHECK32: for.inc14: -// CHECK32-NEXT: [[TMP11:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[SUB:%.*]] = sub i64 [[TMP11]], 400 -// CHECK32-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK32: for.end15: -// CHECK32-NEXT: store i16 6, i16* [[IT16]], align 2 -// CHECK32-NEXT: br label [[FOR_COND17:%.*]] -// CHECK32: for.cond17: -// CHECK32-NEXT: [[TMP12:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK32-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK32-NEXT: [[CMP19:%.*]] = icmp sle i32 [[CONV18]], 20 -// CHECK32-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END29:%.*]] -// CHECK32: for.body20: -// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK32-NEXT: store i32 [[ADD21]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV22:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK32-NEXT: [[ADD23:%.*]] = add nsw i32 [[CONV22]], 1 -// CHECK32-NEXT: [[CONV24:%.*]] = trunc i32 [[ADD23]] to i16 -// CHECK32-NEXT: store i16 [[CONV24]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC25:%.*]] -// CHECK32: for.inc25: -// CHECK32-NEXT: [[TMP15:%.*]] = load i16, i16* [[IT16]], align 2 -// CHECK32-NEXT: [[CONV26:%.*]] = sext i16 [[TMP15]] to i32 -// CHECK32-NEXT: [[SUB27:%.*]] = sub nsw i32 [[CONV26]], -4 -// CHECK32-NEXT: [[CONV28:%.*]] = trunc i32 [[SUB27]] to i16 -// CHECK32-NEXT: store i16 [[CONV28]], i16* [[IT16]], align 2 -// CHECK32-NEXT: br label [[FOR_COND17]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK32: for.end29: -// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP16]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: store i8 122, i8* [[IT30]], align 1 -// CHECK32-NEXT: br label [[FOR_COND31:%.*]] -// CHECK32: for.cond31: -// CHECK32-NEXT: [[TMP17:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK32-NEXT: [[CONV32:%.*]] = zext i8 [[TMP17]] to i32 -// CHECK32-NEXT: [[CMP33:%.*]] = icmp sge i32 [[CONV32]], 97 -// CHECK32-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END57:%.*]] -// CHECK32: for.body34: -// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK32-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV36:%.*]] = fpext float [[TMP19]] to double -// CHECK32-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK32-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK32-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[CONV40:%.*]] = fpext float [[TMP20]] to double -// CHECK32-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK32-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK32-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[ADD45:%.*]] = fadd double [[TMP21]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP22]] -// CHECK32-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK32-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[ADD48:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP24:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP24]], 1 -// CHECK32-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP25:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32 -// CHECK32-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK32-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK32-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK32-NEXT: br label [[FOR_INC53:%.*]] -// CHECK32: for.inc53: -// CHECK32-NEXT: [[TMP26:%.*]] = load i8, i8* [[IT30]], align 1 -// CHECK32-NEXT: [[CONV54:%.*]] = zext i8 [[TMP26]] to i32 -// CHECK32-NEXT: [[ADD55:%.*]] = add nsw i32 [[CONV54]], -1 -// CHECK32-NEXT: [[CONV56:%.*]] = trunc i32 [[ADD55]] to i8 -// CHECK32-NEXT: store i8 [[CONV56]], i8* [[IT30]], align 1 -// CHECK32-NEXT: br label [[FOR_COND31]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK32: for.end57: -// CHECK32-NEXT: [[TMP27:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP28:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP28]]) -// CHECK32-NEXT: ret i32 [[TMP27]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i64 2000, i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP4:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[CMP:%.*]] = icmp uge i64 [[TMP4]], 600 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP8:%.*]] = load i64, i64* [[IT]], align 8 -// CHECK32-NEXT: [[SUB:%.*]] = sub i64 [[TMP8]], 400 -// CHECK32-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK32-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP11]] -// CHECK32-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK32-NEXT: ret i32 [[ADD9]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ADD7:%.*]] = add i32 [[TMP5]], 10 -// CHECK32-NEXT: store i32 [[ADD7]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i64 -10, i64* [[I]], align 8 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP4:%.*]] = load i64, i64* [[I]], align 8 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i64 [[TMP4]], 3 -// CHECK32-NEXT: store i64 [[ADD4]], i64* [[I]], align 8 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP5]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1108,62 +1108,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG22]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG26:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG27:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG30]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG30]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG31:![0-9]+]], !llvm.loop [[LOOP32:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG35:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG35]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp --- a/clang/test/OpenMP/target_parallel_if_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -40,12 +40,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -58,13 +58,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2334,390 +2334,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK5-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK5-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK5-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK5-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV7]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: ret i32 [[ADD]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK6-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK6-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK6-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK6-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV7]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: ret i32 [[ADD]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK7-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK7-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV7]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: ret i32 [[ADD]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK8-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK8-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK8-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV7]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: ret i32 [[ADD]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3648,390 +3264,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK13-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK13-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK13-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK13-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV7]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: ret i32 [[ADD]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK14-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK14-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK14-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK14-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV7]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: ret i32 [[ADD]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK15-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK15-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK15-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK15-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV7]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: ret i32 [[ADD]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK16-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK16-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK16-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK16-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV7]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: ret i32 [[ADD]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -6184,390 +5416,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK21-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK21-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK21-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV7]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: ret i32 [[ADD]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK22-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK22-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK22-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK22-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK22-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV7]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: ret i32 [[ADD]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK23-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK23-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK23-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV7]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: ret i32 [[ADD]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK24-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK24-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK24-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK24-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK24-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV7]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: ret i32 [[ADD]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -7497,387 +6345,4 @@ // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK29-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK29-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK29-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK29-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK29-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV7]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: ret i32 [[ADD]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK30-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK30-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK30-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A5]], align 8 -// CHECK30-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 8 -// CHECK30-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV7]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: ret i32 [[ADD]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK31-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK31-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK31-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK31-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK31-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV7]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: ret i32 [[ADD]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 -// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5 -// CHECK32-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8 -// CHECK32-NEXT: store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1 -// CHECK32-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A5]], align 4 -// CHECK32-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A6]], align 4 -// CHECK32-NEXT: [[CONV7:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV7]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 -// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 -// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: ret i32 [[ADD]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD1]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp --- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 @@ -41,12 +41,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -59,13 +59,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1989,378 +1989,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: ret i32 [[ADD2]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: ret i32 [[ADD2]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV4]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: ret i32 [[ADD2]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV4]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: ret i32 [[ADD2]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3095,378 +2723,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: ret i32 [[ADD2]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: ret i32 [[ADD2]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV4]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: ret i32 [[ADD2]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV4]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: ret i32 [[ADD2]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -5267,378 +4523,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: ret i32 [[ADD2]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: ret i32 [[ADD2]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: ret i32 [[ADD2]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: ret i32 [[ADD2]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -6372,375 +5256,4 @@ // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: ret i32 [[ADD2]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: ret i32 [[ADD2]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: ret i32 [[ADD2]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: ret i32 [[ADD2]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp b/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp --- a/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1000,25 +1000,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: ret i32 0, !dbg [[DBG18:![0-9]+]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp --- a/clang/test/OpenMP/target_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -40,12 +40,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -58,13 +58,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -5752,970 +5752,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK5-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK5-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK5-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK5-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK5-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK5-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK5-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK5-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK5-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK5-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK5-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK5-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK5-NEXT: ret i32 [[TMP20]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK5-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK5-NEXT: ret i32 [[ADD9]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK6-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK6-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK6-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK6-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK6-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK6-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK6-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK6-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK6-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK6-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK6-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK6-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK6-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK6-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK6-NEXT: ret i32 [[TMP20]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK6-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK6-NEXT: ret i32 [[ADD9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK7-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK7-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK7-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK7-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK7-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK7-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK7-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK7-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK7-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK7-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK7-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK7-NEXT: ret i32 [[TMP18]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK7-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK7-NEXT: ret i32 [[ADD9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP4]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK8-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK8-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK8-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK8-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK8-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK8-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK8-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK8-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK8-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK8-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK8-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK8-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK8-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK8-NEXT: ret i32 [[TMP18]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK8-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK8-NEXT: ret i32 [[ADD9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP4]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -8822,970 +7858,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK13-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK13-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK13-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK13-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK13-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK13-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK13-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK13-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK13-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK13-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK13-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK13-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK13-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK13-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK13-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK13-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK13-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK13-NEXT: ret i32 [[TMP20]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK13-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK13-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK13-NEXT: ret i32 [[ADD9]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK14-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK14-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK14-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK14-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK14-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK14-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK14-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK14-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK14-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK14-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK14-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK14-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK14-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK14-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK14-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK14-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK14-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK14-NEXT: ret i32 [[TMP20]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK14-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK14-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK14-NEXT: ret i32 [[ADD9]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK15-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK15-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK15-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK15-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK15-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK15-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK15-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK15-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK15-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK15-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK15-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK15-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK15-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK15-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK15-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK15-NEXT: ret i32 [[TMP18]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK15-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK15-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK15-NEXT: ret i32 [[ADD9]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP4]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK16-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK16-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK16-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK16-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK16-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK16-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK16-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK16-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK16-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK16-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK16-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK16-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK16-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK16-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK16-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK16-NEXT: ret i32 [[TMP18]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK16-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK16-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK16-NEXT: ret i32 [[ADD9]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP4]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -15236,970 +13308,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK21-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK21-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK21-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK21-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK21-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK21-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK21-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK21-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK21-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK21-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK21-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK21-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK21-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK21-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK21-NEXT: ret i32 [[TMP20]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK21-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK21-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK21-NEXT: ret i32 [[ADD9]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK22-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK22-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK22-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK22-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK22-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK22-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK22-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK22-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK22-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK22-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK22-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK22-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK22-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK22-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK22-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK22-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK22-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK22-NEXT: ret i32 [[TMP20]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK22-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK22-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK22-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK22-NEXT: ret i32 [[ADD9]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK23-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK23-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK23-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK23-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK23-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK23-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK23-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK23-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK23-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK23-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK23-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK23-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK23-NEXT: ret i32 [[TMP18]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK23-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK23-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK23-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK23-NEXT: ret i32 [[ADD9]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK24-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK24-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK24-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK24-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK24-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK24-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK24-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK24-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK24-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK24-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK24-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK24-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK24-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK24-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK24-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK24-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK24-NEXT: ret i32 [[TMP18]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK24-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK24-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK24-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK24-NEXT: ret i32 [[ADD9]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -18305,967 +15413,4 @@ // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK29-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK29-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK29-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK29-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK29-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK29-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK29-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK29-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK29-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK29-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK29-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK29-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK29-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK29-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK29-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK29-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK29-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK29-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK29-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK29-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK29-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK29-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK29-NEXT: ret i32 [[TMP20]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK29-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: ret void -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK29-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK29-NEXT: ret i32 [[ADD9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK30-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK30-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK30-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK30-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK30-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double -// CHECK30-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK30-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK30-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK30-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double -// CHECK30-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK30-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK30-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK30-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK30-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK30-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] -// CHECK30-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 -// CHECK30-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK30-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 -// CHECK30-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK30-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK30-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK30-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) -// CHECK30-NEXT: ret i32 [[TMP20]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK30-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: [[F1:%.*]] = alloca i32*, align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: ret void -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// CHECK30-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK30-NEXT: ret i32 [[ADD9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK31-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK31-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK31-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK31-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK31-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK31-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK31-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK31-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK31-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK31-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK31-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK31-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK31-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK31-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK31-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK31-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK31-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK31-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK31-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK31-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK31-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK31-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK31-NEXT: ret i32 [[TMP18]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK31-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK31-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: ret void -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK31-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK31-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK31-NEXT: ret i32 [[ADD9]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[NN:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK32-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 -// CHECK32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 -// CHECK32-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 -// CHECK32-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK32-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double -// CHECK32-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 -// CHECK32-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float -// CHECK32-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 -// CHECK32-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double -// CHECK32-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 -// CHECK32-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float -// CHECK32-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 -// CHECK32-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 -// CHECK32-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 -// CHECK32-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] -// CHECK32-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 -// CHECK32-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 -// CHECK32-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 -// CHECK32-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 -// CHECK32-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK32-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 -// CHECK32-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[NN]], align 4 -// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) -// CHECK32-NEXT: ret i32 [[TMP18]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK32-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 -// CHECK32-NEXT: [[F1:%.*]] = alloca i32*, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: ret void -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// CHECK32-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 -// CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// CHECK32-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) -// CHECK32-NEXT: ret i32 [[ADD9]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 @@ -41,12 +41,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -59,13 +59,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -7098,1412 +7098,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK5-NEXT: br label [[FOR_COND4:%.*]] -// CHECK5: for.cond4: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK5-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK5-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body6: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK5-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11:%.*]] -// CHECK5: for.cond11: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK5-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK5: for.body13: -// CHECK5-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK5-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC16:%.*]] -// CHECK5: for.inc16: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK5-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK5-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end18: -// CHECK5-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20:%.*]] -// CHECK5: for.cond20: -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK5-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK5: for.body22: -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK5-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK5-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK5-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK5-NEXT: br label [[FOR_INC27:%.*]] -// CHECK5: for.inc27: -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK5-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK5-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK5-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK5: for.end29: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK5-NEXT: br label [[FOR_COND32:%.*]] -// CHECK5: for.cond32: -// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK5-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK5-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK5: for.body34: -// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK5-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK5-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK5-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK5-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK5-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK5-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK5-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK5-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK5-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK5-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK5-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK5-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK5-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK5-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK5-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK5-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK5-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK5-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK5-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK5-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK5-NEXT: br label [[FOR_INC53:%.*]] -// CHECK5: for.inc53: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK5-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK5-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK5-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK5: for.end55: -// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK5-NEXT: ret i32 [[TMP31]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK5-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK5-NEXT: ret i32 [[ADD10]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP8]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP5]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK6-NEXT: br label [[FOR_COND4:%.*]] -// CHECK6: for.cond4: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK6-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK6-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body6: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK6-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11:%.*]] -// CHECK6: for.cond11: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK6-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK6: for.body13: -// CHECK6-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK6-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC16:%.*]] -// CHECK6: for.inc16: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK6-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK6-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end18: -// CHECK6-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20:%.*]] -// CHECK6: for.cond20: -// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK6-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK6: for.body22: -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK6-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK6-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK6-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK6-NEXT: br label [[FOR_INC27:%.*]] -// CHECK6: for.inc27: -// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK6-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK6-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK6-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK6: for.end29: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK6-NEXT: br label [[FOR_COND32:%.*]] -// CHECK6: for.cond32: -// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK6-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK6-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK6: for.body34: -// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK6-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK6-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK6-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK6-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK6-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK6-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK6-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK6-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK6-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK6-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK6-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK6-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK6-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK6-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK6-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK6-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK6-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK6-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK6-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK6-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK6-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK6-NEXT: br label [[FOR_INC53:%.*]] -// CHECK6: for.inc53: -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK6-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK6-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK6-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK6: for.end55: -// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK6-NEXT: ret i32 [[TMP31]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK6-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK6-NEXT: ret i32 [[ADD10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP8]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP5]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK7-NEXT: br label [[FOR_COND4:%.*]] -// CHECK7: for.cond4: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK7-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK7-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body6: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK7-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK7-NEXT: br label [[FOR_COND11:%.*]] -// CHECK7: for.cond11: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK7-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK7-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK7: for.body13: -// CHECK7-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK7-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC16:%.*]] -// CHECK7: for.inc16: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK7-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK7-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK7-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end18: -// CHECK7-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK7-NEXT: br label [[FOR_COND20:%.*]] -// CHECK7: for.cond20: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK7-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK7-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK7: for.body22: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK7-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK7-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK7-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK7-NEXT: br label [[FOR_INC27:%.*]] -// CHECK7: for.inc27: -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK7-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK7-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK7-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end29: -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK7-NEXT: br label [[FOR_COND32:%.*]] -// CHECK7: for.cond32: -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK7-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK7-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK7: for.body34: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK7-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK7-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK7-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK7-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK7-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK7-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK7-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK7-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK7-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK7-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK7-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK7-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK7-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK7-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK7-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK7-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK7-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK7-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK7-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK7-NEXT: br label [[FOR_INC53:%.*]] -// CHECK7: for.inc53: -// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK7-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK7-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK7-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end55: -// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK7-NEXT: ret i32 [[TMP29]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK7-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK7-NEXT: ret i32 [[ADD10]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP8]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP5]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK8-NEXT: br label [[FOR_COND4:%.*]] -// CHECK8: for.cond4: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK8-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK8-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body6: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK8-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK8-NEXT: br label [[FOR_COND11:%.*]] -// CHECK8: for.cond11: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK8-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK8-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK8: for.body13: -// CHECK8-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK8-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC16:%.*]] -// CHECK8: for.inc16: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK8-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK8-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK8-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end18: -// CHECK8-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK8-NEXT: br label [[FOR_COND20:%.*]] -// CHECK8: for.cond20: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK8-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK8-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK8: for.body22: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK8-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK8-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK8-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK8-NEXT: br label [[FOR_INC27:%.*]] -// CHECK8: for.inc27: -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK8-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK8-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK8-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end29: -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK8-NEXT: br label [[FOR_COND32:%.*]] -// CHECK8: for.cond32: -// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK8-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK8-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK8: for.body34: -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK8-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK8-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK8-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK8-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK8-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK8-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK8-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK8-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK8-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK8-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK8-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK8-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK8-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK8-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK8-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK8-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK8-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK8-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK8-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK8-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK8-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK8-NEXT: br label [[FOR_INC53:%.*]] -// CHECK8: for.inc53: -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK8-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK8-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK8-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end55: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK8-NEXT: ret i32 [[TMP29]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK8-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK8-NEXT: ret i32 [[ADD10]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP8]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP5]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -11850,1412 +10444,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4:%.*]] -// CHECK13: for.cond4: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK13-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body6: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK13-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK13-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20:%.*]] -// CHECK13: for.cond20: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK13-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK13: for.body22: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK13-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK13-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK13-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK13-NEXT: br label [[FOR_INC27:%.*]] -// CHECK13: for.inc27: -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK13-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK13-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK13-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end29: -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK13-NEXT: br label [[FOR_COND32:%.*]] -// CHECK13: for.cond32: -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK13-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK13-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK13: for.body34: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK13-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK13-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK13-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK13-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK13-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK13-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK13-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK13-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK13-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK13-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK13-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK13-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK13-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK13-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK13-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK13-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK13-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK13-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK13-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK13-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK13-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK13-NEXT: br label [[FOR_INC53:%.*]] -// CHECK13: for.inc53: -// CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK13-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK13-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK13-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end55: -// CHECK13-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK13-NEXT: ret i32 [[TMP31]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK13-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK13-NEXT: ret i32 [[ADD10]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP8]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4:%.*]] -// CHECK14: for.cond4: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK14-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body6: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK14-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK14-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20:%.*]] -// CHECK14: for.cond20: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK14-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK14: for.body22: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK14-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK14-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK14-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK14-NEXT: br label [[FOR_INC27:%.*]] -// CHECK14: for.inc27: -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK14-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK14-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK14-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end29: -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK14-NEXT: br label [[FOR_COND32:%.*]] -// CHECK14: for.cond32: -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK14-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK14-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK14: for.body34: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK14-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK14-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK14-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK14-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK14-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK14-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK14-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK14-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK14-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK14-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK14-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK14-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK14-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK14-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK14-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK14-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK14-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK14-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK14-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK14-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK14-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK14-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK14-NEXT: br label [[FOR_INC53:%.*]] -// CHECK14: for.inc53: -// CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK14-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK14-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK14-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end55: -// CHECK14-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK14-NEXT: ret i32 [[TMP31]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK14-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK14-NEXT: ret i32 [[ADD10]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP8]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4:%.*]] -// CHECK15: for.cond4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK15-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK15: for.body6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: br label [[FOR_INC7:%.*]] -// CHECK15: for.inc7: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK15-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK15-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK15-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end9: -// CHECK15-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK15-NEXT: br label [[FOR_COND11:%.*]] -// CHECK15: for.cond11: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK15-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK15-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK15: for.body13: -// CHECK15-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK15-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC16:%.*]] -// CHECK15: for.inc16: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK15-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK15-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK15-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end18: -// CHECK15-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK15-NEXT: br label [[FOR_COND20:%.*]] -// CHECK15: for.cond20: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK15-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK15-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK15: for.body22: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK15-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK15-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK15-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK15-NEXT: br label [[FOR_INC27:%.*]] -// CHECK15: for.inc27: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK15-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK15-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end29: -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK15-NEXT: br label [[FOR_COND32:%.*]] -// CHECK15: for.cond32: -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK15-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK15-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK15: for.body34: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK15-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK15-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK15-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK15-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK15-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK15-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK15-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK15-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK15-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK15-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK15-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK15-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK15-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK15-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK15-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK15-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK15-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK15-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK15-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK15-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK15-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK15-NEXT: br label [[FOR_INC53:%.*]] -// CHECK15: for.inc53: -// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK15-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK15-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK15-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end55: -// CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK15-NEXT: ret i32 [[TMP29]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK15-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK15-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK15-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK15-NEXT: ret i32 [[ADD10]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP8]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4:%.*]] -// CHECK16: for.cond4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK16-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK16: for.body6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: br label [[FOR_INC7:%.*]] -// CHECK16: for.inc7: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK16-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK16-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK16-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end9: -// CHECK16-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK16-NEXT: br label [[FOR_COND11:%.*]] -// CHECK16: for.cond11: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK16-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK16-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK16: for.body13: -// CHECK16-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK16-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC16:%.*]] -// CHECK16: for.inc16: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK16-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK16-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK16-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end18: -// CHECK16-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK16-NEXT: br label [[FOR_COND20:%.*]] -// CHECK16: for.cond20: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK16-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK16-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK16: for.body22: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK16-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK16-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK16-NEXT: br label [[FOR_INC27:%.*]] -// CHECK16: for.inc27: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK16-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK16-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end29: -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK16-NEXT: br label [[FOR_COND32:%.*]] -// CHECK16: for.cond32: -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK16-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK16-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK16: for.body34: -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK16-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK16-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK16-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK16-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK16-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK16-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK16-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK16-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK16-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK16-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK16-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK16-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK16-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK16-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK16-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK16-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK16-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK16-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK16-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK16-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK16-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK16-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK16-NEXT: br label [[FOR_INC53:%.*]] -// CHECK16: for.inc53: -// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK16-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK16-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK16-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end55: -// CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK16-NEXT: ret i32 [[TMP29]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK16-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK16-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK16-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK16-NEXT: ret i32 [[ADD10]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP8]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -20060,1412 +17248,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK21-NEXT: br label [[FOR_COND4:%.*]] -// CHECK21: for.cond4: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK21-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK21-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body6: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK21-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK21-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK21-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK21-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK21-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK21-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK21-NEXT: br label [[FOR_INC27:%.*]] -// CHECK21: for.inc27: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end29: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK21-NEXT: br label [[FOR_COND32:%.*]] -// CHECK21: for.cond32: -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK21-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK21-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK21: for.body34: -// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK21-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK21-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK21-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK21-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK21-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK21-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK21-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK21-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK21-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK21-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK21-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK21-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK21-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK21-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK21-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK21-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK21-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK21-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK21-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK21-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK21-NEXT: br label [[FOR_INC53:%.*]] -// CHECK21: for.inc53: -// CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK21-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK21-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK21-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end55: -// CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK21-NEXT: ret i32 [[TMP31]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK21-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK21-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK21-NEXT: ret i32 [[ADD10]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP8]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP5]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK22-NEXT: br label [[FOR_COND4:%.*]] -// CHECK22: for.cond4: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK22-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK22-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body6: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK22-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK22-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK22-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK22-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK22-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK22-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK22-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK22-NEXT: br label [[FOR_INC27:%.*]] -// CHECK22: for.inc27: -// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK22-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end29: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK22-NEXT: br label [[FOR_COND32:%.*]] -// CHECK22: for.cond32: -// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK22-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK22-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK22: for.body34: -// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK22-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK22-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK22-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK22-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK22-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK22-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK22-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK22-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK22-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK22-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK22-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK22-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK22-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK22-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK22-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK22-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK22-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK22-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK22-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK22-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK22-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK22-NEXT: br label [[FOR_INC53:%.*]] -// CHECK22: for.inc53: -// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK22-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK22-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK22-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end55: -// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK22-NEXT: ret i32 [[TMP31]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK22-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK22-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK22-NEXT: ret i32 [[ADD10]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP8]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP5]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK23-NEXT: br label [[FOR_COND4:%.*]] -// CHECK23: for.cond4: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK23-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK23-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK23: for.body6: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: br label [[FOR_INC7:%.*]] -// CHECK23: for.inc7: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK23-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK23-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK23-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end9: -// CHECK23-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK23-NEXT: br label [[FOR_COND11:%.*]] -// CHECK23: for.cond11: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK23-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK23-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK23: for.body13: -// CHECK23-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK23-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC16:%.*]] -// CHECK23: for.inc16: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK23-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK23-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK23-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end18: -// CHECK23-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK23-NEXT: br label [[FOR_COND20:%.*]] -// CHECK23: for.cond20: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK23-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK23-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK23: for.body22: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK23-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK23-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK23-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK23-NEXT: br label [[FOR_INC27:%.*]] -// CHECK23: for.inc27: -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK23-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK23-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK23-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end29: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK23-NEXT: br label [[FOR_COND32:%.*]] -// CHECK23: for.cond32: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK23-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK23-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK23: for.body34: -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK23-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK23-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK23-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK23-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK23-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK23-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK23-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK23-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK23-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK23-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK23-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK23-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK23-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK23-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK23-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK23-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK23-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK23-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK23-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK23-NEXT: br label [[FOR_INC53:%.*]] -// CHECK23: for.inc53: -// CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK23-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK23-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK23-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end55: -// CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK23-NEXT: ret i32 [[TMP29]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK23-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK23-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK23-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK23-NEXT: ret i32 [[ADD10]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP8]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP5]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK24-NEXT: br label [[FOR_COND4:%.*]] -// CHECK24: for.cond4: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK24-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK24-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK24: for.body6: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: br label [[FOR_INC7:%.*]] -// CHECK24: for.inc7: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK24-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK24-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK24-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end9: -// CHECK24-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK24-NEXT: br label [[FOR_COND11:%.*]] -// CHECK24: for.cond11: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK24-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK24-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK24: for.body13: -// CHECK24-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK24-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK24-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC16:%.*]] -// CHECK24: for.inc16: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK24-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK24-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK24-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end18: -// CHECK24-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK24-NEXT: br label [[FOR_COND20:%.*]] -// CHECK24: for.cond20: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK24-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK24-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK24: for.body22: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK24-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK24-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK24-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK24-NEXT: br label [[FOR_INC27:%.*]] -// CHECK24: for.inc27: -// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK24-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK24-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK24-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end29: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK24-NEXT: br label [[FOR_COND32:%.*]] -// CHECK24: for.cond32: -// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK24-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK24-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK24: for.body34: -// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK24-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK24-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK24-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK24-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK24-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK24-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK24-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK24-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK24-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK24-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK24-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK24-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK24-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK24-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK24-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK24-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK24-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK24-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK24-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK24-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK24-NEXT: br label [[FOR_INC53:%.*]] -// CHECK24: for.inc53: -// CHECK24-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK24-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK24-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK24-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end55: -// CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK24-NEXT: ret i32 [[TMP29]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK24-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK24-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK24-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK24-NEXT: ret i32 [[ADD10]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP8]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP5]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -24811,1409 +20593,4 @@ // CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK29-NEXT: br label [[FOR_COND4:%.*]] -// CHECK29: for.cond4: -// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK29-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK29-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK29: for.body6: -// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: br label [[FOR_INC7:%.*]] -// CHECK29: for.inc7: -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK29-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK29-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK29-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end9: -// CHECK29-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK29-NEXT: br label [[FOR_COND11:%.*]] -// CHECK29: for.cond11: -// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK29-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK29-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK29: for.body13: -// CHECK29-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK29-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK29-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC16:%.*]] -// CHECK29: for.inc16: -// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK29-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK29-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK29-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK29: for.end18: -// CHECK29-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK29-NEXT: br label [[FOR_COND20:%.*]] -// CHECK29: for.cond20: -// CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK29-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK29-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK29: for.body22: -// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK29-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK29-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK29-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK29-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK29-NEXT: br label [[FOR_INC27:%.*]] -// CHECK29: for.inc27: -// CHECK29-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK29-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK29-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK29-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK29: for.end29: -// CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK29-NEXT: br label [[FOR_COND32:%.*]] -// CHECK29: for.cond32: -// CHECK29-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK29-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK29-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK29: for.body34: -// CHECK29-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK29-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK29-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK29-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK29-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK29-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK29-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK29-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK29-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK29-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK29-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK29-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK29-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK29-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK29-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK29-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK29-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK29-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK29-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK29-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK29-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK29-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK29-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK29-NEXT: br label [[FOR_INC53:%.*]] -// CHECK29: for.inc53: -// CHECK29-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK29-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK29-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK29-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK29: for.end55: -// CHECK29-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK29-NEXT: ret i32 [[TMP31]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK29-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK29-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK29-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK29-NEXT: ret i32 [[ADD10]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP8]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP5]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 -// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK30-NEXT: br label [[FOR_COND4:%.*]] -// CHECK30: for.cond4: -// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK30-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK30-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK30: for.body6: -// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: br label [[FOR_INC7:%.*]] -// CHECK30: for.inc7: -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK30-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK30-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK30-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end9: -// CHECK30-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK30-NEXT: br label [[FOR_COND11:%.*]] -// CHECK30: for.cond11: -// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK30-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10 -// CHECK30-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK30: for.body13: -// CHECK30-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 -// CHECK30-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK30-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC16:%.*]] -// CHECK30: for.inc16: -// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK30-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK30-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK30-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK30: for.end18: -// CHECK30-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK30-NEXT: br label [[FOR_COND20:%.*]] -// CHECK30: for.cond20: -// CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK30-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10 -// CHECK30-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK30: for.body22: -// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK30-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP18:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV24:%.*]] = sext i16 [[TMP18]] to i32 -// CHECK30-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK30-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK30-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK30-NEXT: br label [[FOR_INC27:%.*]] -// CHECK30: for.inc27: -// CHECK30-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK30-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK30-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK30-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK30: for.end29: -// CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK30-NEXT: br label [[FOR_COND32:%.*]] -// CHECK30: for.cond32: -// CHECK30-NEXT: [[TMP21:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK30-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10 -// CHECK30-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK30: for.body34: -// CHECK30-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK30-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[CONV36:%.*]] = fpext float [[TMP23]] to double -// CHECK30-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK30-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK30-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// CHECK30-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[CONV40:%.*]] = fpext float [[TMP24]] to double -// CHECK30-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK30-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK30-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK30-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// CHECK30-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK30-NEXT: [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]] -// CHECK30-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]] -// CHECK30-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3 -// CHECK30-NEXT: [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00 -// CHECK30-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP28:%.*]] = load i64, i64* [[X]], align 8 -// CHECK30-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1 -// CHECK30-NEXT: store i64 [[ADD49]], i64* [[X]], align 8 -// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK30-NEXT: [[TMP29:%.*]] = load i8, i8* [[Y]], align 8 -// CHECK30-NEXT: [[CONV50:%.*]] = sext i8 [[TMP29]] to i32 -// CHECK30-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK30-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK30-NEXT: store i8 [[CONV52]], i8* [[Y]], align 8 -// CHECK30-NEXT: br label [[FOR_INC53:%.*]] -// CHECK30: for.inc53: -// CHECK30-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK30-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK30-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK30-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK30: for.end55: -// CHECK30-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP32]]) -// CHECK30-NEXT: ret i32 [[TMP31]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] -// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP7:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 -// CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK30-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]] -// CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 -// CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK30-NEXT: [[CONV9:%.*]] = sext i16 [[TMP11]] to i32 -// CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]] -// CHECK30-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) -// CHECK30-NEXT: ret i32 [[ADD10]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP8]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP5]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK31-NEXT: br label [[FOR_COND4:%.*]] -// CHECK31: for.cond4: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK31-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK31-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK31: for.body6: -// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: br label [[FOR_INC7:%.*]] -// CHECK31: for.inc7: -// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK31-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK31-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK31-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end9: -// CHECK31-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK31-NEXT: br label [[FOR_COND11:%.*]] -// CHECK31: for.cond11: -// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK31-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK31-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK31: for.body13: -// CHECK31-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK31-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK31-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC16:%.*]] -// CHECK31: for.inc16: -// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK31-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK31-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK31-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK31: for.end18: -// CHECK31-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK31-NEXT: br label [[FOR_COND20:%.*]] -// CHECK31: for.cond20: -// CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK31-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK31-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK31: for.body22: -// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK31-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK31-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK31-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK31-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK31-NEXT: br label [[FOR_INC27:%.*]] -// CHECK31: for.inc27: -// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK31-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK31-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK31-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK31: for.end29: -// CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK31-NEXT: br label [[FOR_COND32:%.*]] -// CHECK31: for.cond32: -// CHECK31-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK31-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK31-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK31: for.body34: -// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK31-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK31-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK31-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK31-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK31-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK31-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK31-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK31-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK31-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK31-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK31-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK31-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK31-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK31-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK31-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK31-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK31-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK31-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK31-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK31-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK31-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK31-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK31-NEXT: br label [[FOR_INC53:%.*]] -// CHECK31: for.inc53: -// CHECK31-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK31-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK31-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK31-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK31: for.end55: -// CHECK31-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK31-NEXT: ret i32 [[TMP29]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK31-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK31-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK31-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK31-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK31-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK31-NEXT: ret i32 [[ADD10]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP5]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 -// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I31:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: store i32 0, i32* [[I3]], align 4 -// CHECK32-NEXT: br label [[FOR_COND4:%.*]] -// CHECK32: for.cond4: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK32-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10 -// CHECK32-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]] -// CHECK32: for.body6: -// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: br label [[FOR_INC7:%.*]] -// CHECK32: for.inc7: -// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[I3]], align 4 -// CHECK32-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK32-NEXT: store i32 [[INC8]], i32* [[I3]], align 4 -// CHECK32-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end9: -// CHECK32-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK32-NEXT: br label [[FOR_COND11:%.*]] -// CHECK32: for.cond11: -// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK32-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10 -// CHECK32-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK32: for.body13: -// CHECK32-NEXT: [[TMP12:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP12]] to i32 -// CHECK32-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16 -// CHECK32-NEXT: store i16 [[CONV15]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC16:%.*]] -// CHECK32: for.inc16: -// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK32-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK32-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK32-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK32: for.end18: -// CHECK32-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK32-NEXT: br label [[FOR_COND20:%.*]] -// CHECK32: for.cond20: -// CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK32-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK32-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]] -// CHECK32: for.body22: -// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK32-NEXT: store i32 [[ADD23]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP16:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV24:%.*]] = sext i16 [[TMP16]] to i32 -// CHECK32-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 -// CHECK32-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16 -// CHECK32-NEXT: store i16 [[CONV26]], i16* [[AA]], align 2 -// CHECK32-NEXT: br label [[FOR_INC27:%.*]] -// CHECK32: for.inc27: -// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK32-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK32-NEXT: store i32 [[INC28]], i32* [[I19]], align 4 -// CHECK32-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK32: for.end29: -// CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I31]], align 4 -// CHECK32-NEXT: br label [[FOR_COND32:%.*]] -// CHECK32: for.cond32: -// CHECK32-NEXT: [[TMP19:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK32-NEXT: [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10 -// CHECK32-NEXT: br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]] -// CHECK32: for.body34: -// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK32-NEXT: store i32 [[ADD35]], i32* [[A]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[CONV36:%.*]] = fpext float [[TMP21]] to double -// CHECK32-NEXT: [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00 -// CHECK32-NEXT: [[CONV38:%.*]] = fptrunc double [[ADD37]] to float -// CHECK32-NEXT: store float [[CONV38]], float* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// CHECK32-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[CONV40:%.*]] = fpext float [[TMP22]] to double -// CHECK32-NEXT: [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00 -// CHECK32-NEXT: [[CONV42:%.*]] = fptrunc double [[ADD41]] to float -// CHECK32-NEXT: store float [[CONV42]], float* [[ARRAYIDX39]], align 4 -// CHECK32-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// CHECK32-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD45]], double* [[ARRAYIDX44]], align 8 -// CHECK32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK32-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]] -// CHECK32-NEXT: [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3 -// CHECK32-NEXT: [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00 -// CHECK32-NEXT: store double [[ADD48]], double* [[ARRAYIDX47]], align 8 -// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP26:%.*]] = load i64, i64* [[X]], align 4 -// CHECK32-NEXT: [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1 -// CHECK32-NEXT: store i64 [[ADD49]], i64* [[X]], align 4 -// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// CHECK32-NEXT: [[TMP27:%.*]] = load i8, i8* [[Y]], align 4 -// CHECK32-NEXT: [[CONV50:%.*]] = sext i8 [[TMP27]] to i32 -// CHECK32-NEXT: [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1 -// CHECK32-NEXT: [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8 -// CHECK32-NEXT: store i8 [[CONV52]], i8* [[Y]], align 4 -// CHECK32-NEXT: br label [[FOR_INC53:%.*]] -// CHECK32: for.inc53: -// CHECK32-NEXT: [[TMP28:%.*]] = load i32, i32* [[I31]], align 4 -// CHECK32-NEXT: [[INC54:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK32-NEXT: store i32 [[INC54]], i32* [[I31]], align 4 -// CHECK32-NEXT: br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK32: for.end55: -// CHECK32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP30]]) -// CHECK32-NEXT: ret i32 [[TMP29]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] -// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double -// CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 -// CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK32-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]] -// CHECK32-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 -// CHECK32-NEXT: [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 -// CHECK32-NEXT: [[CONV9:%.*]] = sext i16 [[TMP10]] to i32 -// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]] -// CHECK32-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK32-NEXT: ret i32 [[ADD10]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 -// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 -// CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 -// CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP5]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -53,12 +53,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -666,242 +666,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -2651,475 +2415,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -62,12 +62,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -1504,320 +1504,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -5557,617 +5243,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -3267,1182 +3267,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done3: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done3: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP13]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -4956,267 +3780,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -824,78 +824,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3687,1083 +3615,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -29,13 +29,13 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 @@ -3029,274 +3029,6 @@ // CHECK5-NEXT: ret void // // -// CHECK6-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK6-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK6-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK7-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK7-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK7-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK7-NEXT: br label [[FOR_INC9:%.*]] -// CHECK7: for.inc9: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end11: -// CHECK7-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK8-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK8-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK8-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP13]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK9-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK9-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK9-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK9-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK9-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3:%.*]] -// CHECK9: for.cond3: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK9: for.body5: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: br label [[FOR_INC8:%.*]] -// CHECK9: for.inc8: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end10: -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK9-NEXT: ret i32 [[TMP13]] -// -// // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 // CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: @@ -5100,271 +4832,4 @@ // CHECK13: omp.precond.end: // CHECK13-NEXT: ret void // -// -// CHECK14-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK14-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK14-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK14-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK14-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3:%.*]] -// CHECK14: for.cond3: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK14: for.body5: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK14-NEXT: br label [[FOR_INC9:%.*]] -// CHECK14: for.inc9: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK14-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK14-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end11: -// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK15-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK15-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 -// CHECK15-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK15-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3:%.*]] -// CHECK15: for.cond3: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK15-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK15: for.body5: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 8 -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i64 0 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 [[IDXPROM7]] -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4 -// CHECK15-NEXT: br label [[FOR_INC9:%.*]] -// CHECK15: for.inc9: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK15-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK15-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK15: for.end11: -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK16-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK16-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK16-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK16-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3:%.*]] -// CHECK16: for.cond3: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK16-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK16: for.body5: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK16-NEXT: br label [[FOR_INC8:%.*]] -// CHECK16: for.inc8: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK16-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK16-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end10: -// CHECK16-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK17-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK17-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 -// CHECK17-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 -// CHECK17-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 -// CHECK17-NEXT: store i32 1000, i32* [[N]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK17-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK17-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 -// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 -// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK17-NEXT: br label [[FOR_COND:%.*]] -// CHECK17: for.cond: -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK17-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK17: for.body: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP5]] -// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK17-NEXT: br label [[FOR_INC:%.*]] -// CHECK17: for.inc: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK17-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK17-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK17: for.end: -// CHECK17-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK17-NEXT: br label [[FOR_COND3:%.*]] -// CHECK17: for.cond3: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK17: for.body5: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[G_ADDR]], align 4 -// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK17-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX7]], align 4 -// CHECK17-NEXT: br label [[FOR_INC8:%.*]] -// CHECK17: for.inc8: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK17-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK17-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK17: for.end10: -// CHECK17-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK17-NEXT: ret i32 [[TMP13]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -54,12 +54,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -963,242 +963,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3760,475 +3524,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -66,12 +66,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -2380,320 +2380,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -8737,645 +8423,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -35,16 +35,16 @@ // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -5096,1450 +5096,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP14]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP14]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK9-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK9-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP14]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK10-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK10-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP14]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// -// // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 // CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -9656,1315 +8212,4 @@ // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK17-NEXT: ret void // -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK18-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK18-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK18-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK18-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK18-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK18-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK18-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done3: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP14]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK18-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK18-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK18-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__cxx_global_var_init() -// CHECK18-NEXT: call void @__cxx_global_var_init.1() -// CHECK18-NEXT: call void @__cxx_global_var_init.2() -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK19-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done1: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK19-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK19-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK19-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK19-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK19-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK19-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK19-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done3: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: ret i32 [[TMP14]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK19-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK19-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK19-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__cxx_global_var_init() -// CHECK19-NEXT: call void @__cxx_global_var_init.1() -// CHECK19-NEXT: call void @__cxx_global_var_init.2() -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done1: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK20-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK20-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK20-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK20-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK20-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK20-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK20-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK20-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done2: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: ret i32 [[TMP14]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK20-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK20-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK20-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__cxx_global_var_init() -// CHECK20-NEXT: call void @__cxx_global_var_init.1() -// CHECK20-NEXT: call void @__cxx_global_var_init.2() -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done1: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK21-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK21-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK21-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK21-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK21-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK21-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK21-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK21-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK21-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK21-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK21-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK21-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done2: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP14]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK21-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK21-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK21-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @__cxx_global_var_init() -// CHECK21-NEXT: call void @__cxx_global_var_init.1() -// CHECK21-NEXT: call void @__cxx_global_var_init.2() -// CHECK21-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK22-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK22: arraydestroy.body: -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK22-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK22-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK22: arraydestroy.done1: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK22-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK22-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK22-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @__cxx_global_var_init() -// CHECK22-NEXT: call void @__cxx_global_var_init.1() -// CHECK22-NEXT: call void @__cxx_global_var_init.2() -// CHECK22-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp @@ -3,33 +3,33 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2753,328 +2753,6 @@ // CHECK2-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: -// CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: -// CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: -// CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: -// CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: ret i32 0 -// -// // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: @@ -5723,328 +5401,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -8693,328 +8049,6 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z9gtid_testv() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn4v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn5v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn6v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn1v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn2v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn3v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z9gtid_testv() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn4v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn5v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn6v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn1v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn2v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn3v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: ret i32 0 -// -// // CHECK13-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -11662,325 +10696,4 @@ // CHECK14-NEXT: call void @__tgt_register_requires(i64 1) // CHECK14-NEXT: ret void // -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z9gtid_testv() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn4v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn5v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn6v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn1v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn2v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn3v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z9gtid_testv() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn4v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn5v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn6v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn1v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn2v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn3v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -13,19 +13,19 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -5370,1163 +5370,4 @@ // CHECK8-NEXT: call void @__tgt_register_requires(i64 1) // CHECK8-NEXT: ret void // -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK9-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK10-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK11-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK11-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK12-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK12-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK12-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done3: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // REQUIRES: powerpc-registered-target // expected-no-diagnostics @@ -338,45 +338,4 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -35,15 +35,15 @@ // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -3534,1650 +3534,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done4: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done8: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK7: arraydestroy.body10: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK7: arraydestroy.done14: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done4: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done8: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK8: arraydestroy.body10: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK8: arraydestroy.done14: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done1: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK9-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK9-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK9-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done3: -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK9: arrayctor.loop: -// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK9-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK9-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK9-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK9-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK9: arraydestroy.body: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK9: arraydestroy.done7: -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK9: arraydestroy.body9: -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK9: arraydestroy.done13: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: ret i32 [[TMP11]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK9-SAME: () #[[ATTR0]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @__cxx_global_var_init() -// CHECK9-NEXT: call void @__cxx_global_var_init.1() -// CHECK9-NEXT: call void @__cxx_global_var_init.2() -// CHECK9-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done1: -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK10-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK10-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK10-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done3: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK10: arrayctor.loop: -// CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK10-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK10-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK10-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK10-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK10: arraydestroy.body: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK10: arraydestroy.done7: -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK10: arraydestroy.body9: -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK10-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK10: arraydestroy.done13: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: ret i32 [[TMP11]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: ret void -// -// -// CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK10-SAME: () #[[ATTR0]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @__cxx_global_var_init() -// CHECK10-NEXT: call void @__cxx_global_var_init.1() -// CHECK10-NEXT: call void @__cxx_global_var_init.2() -// CHECK10-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// -// // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -7373,1515 +5729,4 @@ // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK17-NEXT: ret void // -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK18-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done1: -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK18-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK18-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK18-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK18: arrayctor.loop: -// CHECK18-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK18-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK18-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK18-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK18: arrayctor.cont: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK18-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK18-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done4: -// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK18-NEXT: ret i32 [[CALL]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK18-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK18-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK18-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK18-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK18-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK18-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK18-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK18-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK18-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK18-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK18-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK18-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK18-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK18-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK18: arrayctor.loop: -// CHECK18-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK18-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK18-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK18-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK18: arrayctor.cont: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK18-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND:%.*]] -// CHECK18: for.cond: -// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK18-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK18: for.body: -// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK18-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK18-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK18-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK18-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK18-NEXT: br label [[FOR_INC:%.*]] -// CHECK18: for.inc: -// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK18-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK18-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK18: for.end: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK18: arraydestroy.body: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK18: arraydestroy.done8: -// CHECK18-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK18-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK18: arraydestroy.body10: -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK18-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK18: arraydestroy.done14: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK18-NEXT: ret i32 [[TMP11]] -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK18-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK18-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK18-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK18-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: ret void -// -// -// CHECK18-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK18-SAME: () #[[ATTR0]] { -// CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @__cxx_global_var_init() -// CHECK18-NEXT: call void @__cxx_global_var_init.1() -// CHECK18-NEXT: call void @__cxx_global_var_init.2() -// CHECK18-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK19-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK19-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done1: -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK19-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK19-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK19-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK19: arrayctor.loop: -// CHECK19-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK19-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK19-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK19-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK19: arrayctor.cont: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK19-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK19-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done4: -// CHECK19-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK19-NEXT: ret i32 [[CALL]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK19-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK19-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK19-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK19-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK19-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK19-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK19-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK19-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK19-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK19-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK19-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK19: arrayctor.loop: -// CHECK19-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK19-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK19-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK19-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK19: arrayctor.cont: -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK19-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND:%.*]] -// CHECK19: for.cond: -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK19-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK19: for.body: -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK19-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK19-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK19-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK19-NEXT: br label [[FOR_INC:%.*]] -// CHECK19: for.inc: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK19-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK19-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK19: for.end: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK19: arraydestroy.body: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK19: arraydestroy.done8: -// CHECK19-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK19-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK19: arraydestroy.body10: -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK19-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK19: arraydestroy.done14: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK19-NEXT: ret i32 [[TMP11]] -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK19-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK19-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK19-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK19-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK19-SAME: () #[[ATTR0]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @__cxx_global_var_init() -// CHECK19-NEXT: call void @__cxx_global_var_init.1() -// CHECK19-NEXT: call void @__cxx_global_var_init.2() -// CHECK19-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK20-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK20-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done1: -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK20-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK20-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK20-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK20: arrayctor.loop: -// CHECK20-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK20-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK20-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK20-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK20: arrayctor.cont: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK20-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK20-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK20-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done3: -// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK20-NEXT: ret i32 [[CALL]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK20-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK20-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK20-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK20-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK20-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK20-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK20-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK20-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK20-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK20-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK20-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK20-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK20: arrayctor.loop: -// CHECK20-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK20-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK20-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK20-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK20: arrayctor.cont: -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK20-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND:%.*]] -// CHECK20: for.cond: -// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK20-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK20: for.body: -// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK20-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK20-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK20-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK20-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK20-NEXT: br label [[FOR_INC:%.*]] -// CHECK20: for.inc: -// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK20-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK20-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK20: for.end: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK20: arraydestroy.body: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK20: arraydestroy.done7: -// CHECK20-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK20-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK20: arraydestroy.body9: -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK20-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK20: arraydestroy.done13: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK20-NEXT: ret i32 [[TMP11]] -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK20-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK20-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK20-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK20-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: ret void -// -// -// CHECK20-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK20-SAME: () #[[ATTR0]] { -// CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @__cxx_global_var_init() -// CHECK20-NEXT: call void @__cxx_global_var_init.1() -// CHECK20-NEXT: call void @__cxx_global_var_init.2() -// CHECK20-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done1: -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK21-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK21-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK21: arrayctor.loop: -// CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK21: arrayctor.cont: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK21-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK21-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK21-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done3: -// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK21-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK21-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK21-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK21-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK21-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK21-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK21-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK21-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK21-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK21-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK21: arrayctor.loop: -// CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK21: arrayctor.cont: -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK21-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK21-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK21-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK21-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK21: arraydestroy.body: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK21: arraydestroy.done7: -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK21-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK21: arraydestroy.body9: -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK21-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK21: arraydestroy.done13: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP11]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK21-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK21-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK21-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK21-SAME: () #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @__cxx_global_var_init() -// CHECK21-NEXT: call void @__cxx_global_var_init.1() -// CHECK21-NEXT: call void @__cxx_global_var_init.2() -// CHECK21-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK22-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK22: arraydestroy.body: -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK22-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK22-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK22-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK22: arraydestroy.done1: -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK22-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK22-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK22-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_private_codegen.cpp -// CHECK22-SAME: () #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @__cxx_global_var_init() -// CHECK22-NEXT: call void @__cxx_global_var_init.1() -// CHECK22-NEXT: call void @__cxx_global_var_init.2() -// CHECK22-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp @@ -5,9 +5,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -973,123 +973,4 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp @@ -10,16 +10,16 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2859,255 +2859,4 @@ // CHECK6-NEXT: call void @__tgt_register_requires(i64 1) // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK9-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: ret i32 0 -// -// -// CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK10-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK10-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1898,62 +1898,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG22]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG23:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG26:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG27:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG30]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG30]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG31:![0-9]+]], !llvm.loop [[LOOP32:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG35:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG35]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp @@ -18,12 +18,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 @@ -97,12 +97,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -7402,476 +7402,6 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3:%.*]] -// CHECK9: for.cond3: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK9-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK9: for.body5: -// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: br label [[FOR_INC9:%.*]] -// CHECK9: for.inc9: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK9-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end11: -// CHECK9-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13:%.*]] -// CHECK9: for.cond13: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK9-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK9: for.body15: -// CHECK9-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK9-NEXT: br label [[FOR_INC19:%.*]] -// CHECK9: for.inc19: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end21: -// CHECK9-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23:%.*]] -// CHECK9: for.cond23: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK9-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK9: for.body25: -// CHECK9-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK9-NEXT: br label [[FOR_INC29:%.*]] -// CHECK9: for.inc29: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end31: -// CHECK9-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33:%.*]] -// CHECK9: for.cond33: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK9-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK9: for.body35: -// CHECK9-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK9-NEXT: br label [[FOR_INC39:%.*]] -// CHECK9: for.inc39: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end41: -// CHECK9-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK9-NEXT: ret i32 [[TMP15]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3:%.*]] -// CHECK10: for.cond3: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK10-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK10: for.body5: -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[FOR_INC9:%.*]] -// CHECK10: for.inc9: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK10-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end11: -// CHECK10-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13:%.*]] -// CHECK10: for.cond13: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK10-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK10: for.body15: -// CHECK10-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK10-NEXT: br label [[FOR_INC19:%.*]] -// CHECK10: for.inc19: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end21: -// CHECK10-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23:%.*]] -// CHECK10: for.cond23: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK10-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK10: for.body25: -// CHECK10-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK10-NEXT: br label [[FOR_INC29:%.*]] -// CHECK10: for.inc29: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end31: -// CHECK10-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33:%.*]] -// CHECK10: for.cond33: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK10-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK10: for.body35: -// CHECK10-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK10-NEXT: br label [[FOR_INC39:%.*]] -// CHECK10: for.inc39: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end41: -// CHECK10-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK10-NEXT: ret i32 [[TMP15]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3:%.*]] -// CHECK11: for.cond3: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK11-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK11: for.body5: -// CHECK11-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[FOR_INC8:%.*]] -// CHECK11: for.inc8: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end10: -// CHECK11-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12:%.*]] -// CHECK11: for.cond12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK11-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK11: for.body14: -// CHECK11-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK11-NEXT: br label [[FOR_INC17:%.*]] -// CHECK11: for.inc17: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end19: -// CHECK11-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21:%.*]] -// CHECK11: for.cond21: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK11-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK11: for.body23: -// CHECK11-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK11-NEXT: br label [[FOR_INC26:%.*]] -// CHECK11: for.inc26: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end28: -// CHECK11-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30:%.*]] -// CHECK11: for.cond30: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK11-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK11: for.body32: -// CHECK11-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK11-NEXT: br label [[FOR_INC35:%.*]] -// CHECK11: for.inc35: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end37: -// CHECK11-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK11-NEXT: ret i32 [[TMP15]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3:%.*]] -// CHECK12: for.cond3: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK12-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK12: for.body5: -// CHECK12-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[FOR_INC8:%.*]] -// CHECK12: for.inc8: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end10: -// CHECK12-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12:%.*]] -// CHECK12: for.cond12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK12-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK12: for.body14: -// CHECK12-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK12-NEXT: br label [[FOR_INC17:%.*]] -// CHECK12: for.inc17: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end19: -// CHECK12-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21:%.*]] -// CHECK12: for.cond21: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK12-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK12: for.body23: -// CHECK12-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK12-NEXT: br label [[FOR_INC26:%.*]] -// CHECK12: for.inc26: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end28: -// CHECK12-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30:%.*]] -// CHECK12: for.cond30: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK12-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK12: for.body32: -// CHECK12-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK12-NEXT: br label [[FOR_INC35:%.*]] -// CHECK12: for.inc35: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end37: -// CHECK12-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK12-NEXT: ret i32 [[TMP15]] -// -// // CHECK13-LABEL: define {{[^@]+}}@main // CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -27619,973 +27149,4 @@ // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: ret void // -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK21-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK21-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK21-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP27]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK21-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK22-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK22-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK22-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK22-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: ret i32 [[TMP27]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK22-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@main -// CHECK23-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK23-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK23-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK23-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK23-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: ret i32 [[TMP26]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK23-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: ret i32 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@main -// CHECK24-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK24-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK24-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK24-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK24-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: ret i32 [[TMP26]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK24-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2063,1386 +2063,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done7: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK7: arraydestroy.body9: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK7: arraydestroy.done13: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done7: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK8: arraydestroy.body9: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK8: arraydestroy.done13: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3894,267 +2514,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp --- a/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1370,238 +1370,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -1895,23 +1663,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp --- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 @@ -41,12 +41,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -59,13 +59,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1974,378 +1974,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: ret i32 [[ADD2]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: ret i32 [[ADD2]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV4]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: ret i32 [[ADD2]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV4]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: ret i32 [[ADD2]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3080,378 +2708,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: ret i32 [[ADD2]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: ret i32 [[ADD2]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV4]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: ret i32 [[ADD2]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV4]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: ret i32 [[ADD2]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -5252,378 +4508,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: ret i32 [[ADD2]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: ret i32 [[ADD2]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: ret i32 [[ADD2]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: ret i32 [[ADD2]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -6357,375 +5241,4 @@ // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: ret i32 [[ADD2]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: ret i32 [[ADD2]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: ret i32 [[ADD2]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: ret i32 [[ADD2]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp --- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp +++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -25,13 +25,13 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test host codegen. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 @@ -41,12 +41,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // Test target codegen - host bc file has to be created first. // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc @@ -59,13 +59,13 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2058,394 +2058,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK5-NEXT: ret i32 [[CONV4]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK5-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: ret i32 [[ADD3]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK5-NEXT: ret i32 [[TMP3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK6-NEXT: ret i32 [[CONV4]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK6-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: ret i32 [[ADD3]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK6-NEXT: ret i32 [[TMP3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK7-NEXT: ret i32 [[CONV4]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK7-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: ret i32 [[ADD3]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK7-NEXT: ret i32 [[TMP3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK8-NEXT: ret i32 [[CONV4]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK8-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: ret i32 [[ADD3]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK8-NEXT: ret i32 [[TMP3]] -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3194,394 +2806,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK13-NEXT: ret i32 [[CONV4]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK13-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK13-NEXT: ret i32 [[ADD3]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK13-NEXT: ret i32 [[TMP3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK14-NEXT: ret i32 [[CONV4]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK14-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK14-NEXT: ret i32 [[ADD3]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK14-NEXT: ret i32 [[TMP3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK15-NEXT: ret i32 [[CONV4]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK15-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: ret i32 [[ADD3]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK15-NEXT: ret i32 [[TMP3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK16-NEXT: ret i32 [[CONV4]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK16-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: ret i32 [[ADD3]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK16-NEXT: ret i32 [[TMP3]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -5466,394 +4690,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z3bari -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP6]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK21-NEXT: ret i32 [[CONV4]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK21-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK21-NEXT: ret i32 [[ADD3]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK21-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z3bari -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP6]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK22-NEXT: ret i32 [[CONV4]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK22-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK22-NEXT: ret i32 [[ADD3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK22-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z3bari -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP6]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK23-NEXT: ret i32 [[CONV4]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK23-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK23-NEXT: ret i32 [[ADD3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK23-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z3bari -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP6]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK24-NEXT: ret i32 [[CONV4]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK24-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK24-NEXT: ret i32 [[ADD3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK24-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -6601,391 +5437,4 @@ // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP6]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK29-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK29-NEXT: ret i32 [[CONV4]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK29-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK29-NEXT: ret i32 [[ADD3]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK29-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK29-NEXT: ret i32 [[TMP3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP6]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK30-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 -// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 -// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK30-NEXT: ret i32 [[CONV4]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK30-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK30-NEXT: ret i32 [[ADD3]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK30-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK30-NEXT: ret i32 [[TMP3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP6]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK31-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK31-NEXT: ret i32 [[CONV4]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK31-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK31-NEXT: ret i32 [[ADD3]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK31-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK31-NEXT: ret i32 [[TMP3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] -// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] -// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP6]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK32-NEXT: store i32 1, i32* [[B]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] -// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 -// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double -// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 -// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 -// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 -// CHECK32-NEXT: ret i32 [[CONV4]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 32 -// CHECK32-NEXT: store i32 [[MUL]], i32* [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP2]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_2]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK32-NEXT: ret i32 [[ADD3]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 -// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK32-NEXT: store i16 1, i16* [[B]], align 2 -// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 -// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 -// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] -// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK32-NEXT: ret i32 [[TMP3]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/task_codegen.cpp b/clang/test/OpenMP/task_codegen.cpp --- a/clang/test/OpenMP/task_codegen.cpp +++ b/clang/test/OpenMP/task_codegen.cpp @@ -6,9 +6,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -4692,341 +4692,4 @@ // CHECK4-NEXT: call void @__cxx_global_var_init() // CHECK4-NEXT: ret void // -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[FLAG:%.*]] = alloca i8, align 1 -// CHECK5-NEXT: [[C:%.*]] = alloca i32, align 128 -// CHECK5-NEXT: [[S1:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[S2:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] -// CHECK5-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 -// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK5-NEXT: store i32 15, i32* @a, align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @a, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 -// CHECK5-NEXT: store i8 [[CONV]], i8* [[B]], align 1 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 0 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX]], i32 0, i32 0 -// CHECK5-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK5-NEXT: store i32 15, i32* @a, align 4 -// CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 1 -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 10, i32* [[A2]], align 4 -// CHECK5-NEXT: store i32 1, i32* @a, align 4 -// CHECK5-NEXT: store i32 1, i32* @a, align 4 -// CHECK5-NEXT: store i32 1, i32* @a, align 4 -// CHECK5-NEXT: store i32 2, i32* @a, align 4 -// CHECK5-NEXT: store i32 2, i32* @a, align 4 -// CHECK5-NEXT: store i8 0, i8* [[FLAG]], align 1 -// CHECK5-NEXT: store i32 3, i32* @a, align 4 -// CHECK5-NEXT: store i32 4, i32* @a, align 4 -// CHECK5-NEXT: store i32 5, i32* [[C]], align 128 -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1]]) -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2]]) -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK5-NEXT: store i32 4, i32* [[C]], align 128 -// CHECK5-NEXT: store i32 4, i32* @a, align 4 -// CHECK5-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[S1]] to i8* -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK5-NEXT: store i32 10, i32* [[A4]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2]]) #[[ATTR6]] -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1]]) #[[ATTR6]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @a, align 4 -// CHECK5-NEXT: store i32 [[TMP7]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done6: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP10]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR4:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull align 4 dereferenceable(4) @s1) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK5-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK5-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK5-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR5:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp -// CHECK5-SAME: () #[[ATTR4]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: [[FLAG:%.*]] = alloca i8, align 1 -// CHECK6-NEXT: [[C:%.*]] = alloca i32, align 128 -// CHECK6-NEXT: [[S1:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[S2:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] -// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 -// CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK6-NEXT: store i32 15, i32* @a, align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @a, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP4]] to i8 -// CHECK6-NEXT: store i8 [[CONV]], i8* [[B]], align 1 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 0 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX]], i32 0, i32 0 -// CHECK6-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK6-NEXT: store i32 15, i32* @a, align 4 -// CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i64 0, i64 1 -// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYIDX1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 10, i32* [[A2]], align 4 -// CHECK6-NEXT: store i32 1, i32* @a, align 4 -// CHECK6-NEXT: store i32 1, i32* @a, align 4 -// CHECK6-NEXT: store i32 1, i32* @a, align 4 -// CHECK6-NEXT: store i32 2, i32* @a, align 4 -// CHECK6-NEXT: store i32 2, i32* @a, align 4 -// CHECK6-NEXT: store i8 0, i8* [[FLAG]], align 1 -// CHECK6-NEXT: store i32 3, i32* @a, align 4 -// CHECK6-NEXT: store i32 4, i32* @a, align 4 -// CHECK6-NEXT: store i32 5, i32* [[C]], align 128 -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1]]) -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2]]) -// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A3]], align 4 -// CHECK6-NEXT: store i32 4, i32* [[C]], align 128 -// CHECK6-NEXT: store i32 4, i32* @a, align 4 -// CHECK6-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[S1]] to i8* -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2]], i32 0, i32 0 -// CHECK6-NEXT: store i32 10, i32* [[A4]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2]]) #[[ATTR6]] -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1]]) #[[ATTR6]] -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* @a, align 4 -// CHECK6-NEXT: store i32 [[TMP7]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR6]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done6: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR6]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR4:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull align 4 dereferenceable(4) @s1) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK6-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK6-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK6-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR5:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 -// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp -// CHECK6-SAME: () #[[ATTR4]] section "__TEXT,__StaticInit,regular,pure_instructions" { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/task_if_codegen.cpp b/clang/test/OpenMP/task_if_codegen.cpp --- a/clang/test/OpenMP/task_if_codegen.cpp +++ b/clang/test/OpenMP/task_if_codegen.cpp @@ -3,17 +3,17 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1321,76 +1321,6 @@ // CHECK2-NEXT: ret i32 0 // // -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_Z3fn7v() -// CHECK3-NEXT: call void @_Z3fn8v() -// CHECK3-NEXT: call void @_Z3fn9v() -// CHECK3-NEXT: call void @_Z4fn10v() -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_Z3fn7v() -// CHECK4-NEXT: call void @_Z3fn8v() -// CHECK4-NEXT: call void @_Z3fn9v() -// CHECK4-NEXT: call void @_Z4fn10v() -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: ret i32 0 -// -// // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: @@ -2624,73 +2554,4 @@ // CHECK6-NEXT: call void @_Z3fn6v() #[[ATTR3]] // CHECK6-NEXT: ret i32 0 // -// -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_Z3fn7v() -// CHECK7-NEXT: call void @_Z3fn8v() -// CHECK7-NEXT: call void @_Z3fn9v() -// CHECK7-NEXT: call void @_Z4fn10v() -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_Z3fn7v() -// CHECK8-NEXT: call void @_Z3fn8v() -// CHECK8-NEXT: call void @_Z3fn9v() -// CHECK8-NEXT: call void @_Z4fn10v() -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/task_in_reduction_codegen.cpp b/clang/test/OpenMP/task_in_reduction_codegen.cpp --- a/clang/test/OpenMP/task_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/task_in_reduction_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1394,203 +1394,4 @@ // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[CONV]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP9]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK4-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK4: arrayctor.loop: -// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[CONV]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[A]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK4: arraydestroy.body: -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK4: arraydestroy.done3: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP9]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp --- a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1379,227 +1379,4 @@ // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP10]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK4-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 -// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[DOTTASK_RED_1:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 5 -// CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK4: arrayctor.loop: -// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 -// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], 5 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[IDXPROM]] -// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[ARRAYIDX]], align 2 -// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CONV]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[C]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 5 -// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK4: arraydestroy.body: -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] -// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK4: arraydestroy.done3: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP10]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp --- a/clang/test/OpenMP/teams_codegen.cpp +++ b/clang/test/OpenMP/teams_codegen.cpp @@ -10,12 +10,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int Gbla; @@ -87,12 +87,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -139,12 +139,12 @@ // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -193,13 +193,13 @@ // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -235,13 +235,13 @@ // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK36 // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK37 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK39 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK40 +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifdef CK5 @@ -282,12 +282,12 @@ // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK44 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-version=50 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK45 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-version=50 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK46 -// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK48 +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK6 void foo() { @@ -2222,170 +2222,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK5-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK5-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK5-NEXT: store float 2.500000e+01, float* [[LC]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK5-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK5-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK5-NEXT: ret i32 [[TMP10]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK6-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK6-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK6-NEXT: store float 2.500000e+01, float* [[LC]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK6-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK6-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK6-NEXT: ret i32 [[TMP10]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK7-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK7-NEXT: store float 2.500000e+01, float* [[LC]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK7-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK7-NEXT: ret i32 [[TMP10]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[LA:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[LC:%.*]] = alloca float, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK8-NEXT: store i32 23, i32* [[LA]], align 4 -// CHECK8-NEXT: store float 2.500000e+01, float* [[LC]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK8-NEXT: ret i32 [[TMP10]] -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z18teams_template_argv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3146,74 +2982,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK13-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 -// CHECK13-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK13-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK13-NEXT: ret i32 [[TMP2]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK14-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 -// CHECK14-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK14-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK14-NEXT: ret i32 [[TMP2]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK15-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 -// CHECK15-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK15-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK15-NEXT: ret i32 [[TMP2]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z18teams_template_argv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK16-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 -// CHECK16-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK16-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK16-NEXT: ret i32 [[TMP2]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -3882,110 +3650,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK21-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK21-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK21-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK21-NEXT: ret i32 [[TMP2]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK22-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK22-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK22-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK22-NEXT: ret i32 [[TMP2]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK23-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK23-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK23-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK23-NEXT: ret i32 [[TMP2]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK24-NEXT: [[COMP:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 1, i32* [[COMP]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK24-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK24-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 -// CHECK24-NEXT: ret i32 [[TMP2]] -// -// // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 // CHECK25-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -4172,102 +3836,6 @@ // CHECK28-NEXT: ret void // // -// CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK29-NEXT: ret i32 [[CALL]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK29-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK29-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK29-NEXT: ret i32 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK30-NEXT: ret i32 [[CALL]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK30-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK30-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK30-NEXT: ret i32 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK31-NEXT: ret i32 [[CALL]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK31-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: ret i32 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK32-NEXT: ret i32 [[CALL]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK32-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: ret i32 0 -// -// // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 // CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK33-NEXT: entry: @@ -4526,134 +4094,6 @@ // CHECK36-NEXT: ret void // // -// CHECK37-LABEL: define {{[^@]+}}@main -// CHECK37-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK37-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK37-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK37-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK37-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK37-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK37-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK37-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK37-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK37-NEXT: ret i32 [[CALL]] -// -// -// CHECK37-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK37-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK37-NEXT: entry: -// CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK37-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK37-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK37-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK37-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK37-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK37-NEXT: ret i32 0 -// -// -// CHECK38-LABEL: define {{[^@]+}}@main -// CHECK38-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK38-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK38-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK38-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK38-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK38-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK38-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK38-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK38-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK38-NEXT: ret i32 [[CALL]] -// -// -// CHECK38-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK38-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK38-NEXT: entry: -// CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 -// CHECK38-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK38-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 -// CHECK38-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK38-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK38-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 -// CHECK38-NEXT: ret i32 0 -// -// -// CHECK39-LABEL: define {{[^@]+}}@main -// CHECK39-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK39-NEXT: entry: -// CHECK39-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK39-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK39-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK39-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK39-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK39-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK39-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK39-NEXT: ret i32 [[CALL]] -// -// -// CHECK39-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK39-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK39-NEXT: entry: -// CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK39-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK39-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK39-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK39-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: ret i32 0 -// -// -// CHECK40-LABEL: define {{[^@]+}}@main -// CHECK40-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK40-NEXT: entry: -// CHECK40-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK40-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK40-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK40-NEXT: store i32 20, i32* [[A]], align 4 -// CHECK40-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK40-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 -// CHECK40-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) -// CHECK40-NEXT: ret i32 [[CALL]] -// -// -// CHECK40-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK40-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { -// CHECK40-NEXT: entry: -// CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 -// CHECK40-NEXT: [[A:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK40-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: store i32 10, i32* [[A]], align 4 -// CHECK40-NEXT: store i32 5, i32* [[B]], align 4 -// CHECK40-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: ret i32 0 -// -// // CHECK41-LABEL: define {{[^@]+}}@_Z3foov // CHECK41-SAME: () #[[ATTR0:[0-9]+]] { // CHECK41-NEXT: entry: @@ -4721,27 +4161,4 @@ // CHECK44-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK44-NEXT: ret void // -// -// CHECK45-LABEL: define {{[^@]+}}@_Z3foov -// CHECK45-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK45-NEXT: entry: -// CHECK45-NEXT: ret void -// -// -// CHECK46-LABEL: define {{[^@]+}}@_Z3foov -// CHECK46-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK46-NEXT: entry: -// CHECK46-NEXT: ret void -// -// -// CHECK47-LABEL: define {{[^@]+}}@_Z3foov -// CHECK47-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK47-NEXT: entry: -// CHECK47-NEXT: ret void -// -// -// CHECK48-LABEL: define {{[^@]+}}@_Z3foov -// CHECK48-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK48-NEXT: entry: -// CHECK48-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_codegen.cpp b/clang/test/OpenMP/teams_distribute_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_codegen.cpp @@ -10,12 +10,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -58,12 +58,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -91,12 +91,12 @@ // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -134,12 +134,12 @@ // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -1611,222 +1611,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK5-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z15teams_local_argv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -2629,162 +2413,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK13-NEXT: ret i32 [[TMP7]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK14-NEXT: ret i32 [[TMP7]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -3295,164 +2923,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@main // CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -4876,317 +4346,4 @@ // CHECK28-NEXT: call void @__tgt_register_requires(i64 1) // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK29-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: ret i32 [[TMP9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK29-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK29-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: ret i32 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK30-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: ret i32 [[TMP9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK30-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK30-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: ret i32 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK31-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK31-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK31-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: ret i32 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK32-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK32-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK32-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -54,12 +54,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -669,242 +669,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -2622,475 +2386,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -65,12 +65,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -1513,320 +1513,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -5450,617 +5136,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -3278,1190 +3278,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP13]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP13]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP13]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP13]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -4975,267 +3791,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -789,78 +789,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3620,1099 +3548,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP13]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP13]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK15-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP13]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] -// CHECK16-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP13]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp @@ -10,12 +10,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 int a[100]; @@ -58,12 +58,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 int teams_local_arg(void) { @@ -91,12 +91,12 @@ // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK3 @@ -134,12 +134,12 @@ // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK29 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 -// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK31 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK4 @@ -2435,222 +2435,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK5-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK6-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i64 0, i64 0), align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK7-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 -// CHECK8-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]] -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @a, i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @a, i32 0, i32 0), align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z15teams_local_argv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3849,162 +3633,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK13-NEXT: ret i32 [[TMP7]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 0 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK14-NEXT: ret i32 [[TMP7]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z15teams_local_argv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 0 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -4799,164 +4427,6 @@ // CHECK20-NEXT: ret void // // -// CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK21-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK21-NEXT: ret i32 [[CALL]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK21-NEXT: ret i32 [[TMP3]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK22-NEXT: ret i32 [[CALL]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i64 0, i64 0 -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK22-NEXT: ret i32 [[TMP3]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK23-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK23-NEXT: ret i32 [[CALL]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK23-NEXT: ret i32 [[TMP3]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK24-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK24-NEXT: ret i32 [[CALL]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A2]], i32 0, i32 0 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 -// CHECK24-NEXT: ret i32 [[TMP3]] -// -// // CHECK25-LABEL: define {{[^@]+}}@main // CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: @@ -7056,317 +6526,4 @@ // CHECK28-NEXT: call void @__tgt_register_requires(i64 1) // CHECK28-NEXT: ret void // -// -// CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK29-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK29-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK29-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK29-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK29-NEXT: ret i32 [[TMP9]] -// -// -// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK29-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK29-NEXT: entry: -// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK29-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK29-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK29-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND:%.*]] -// CHECK29: for.cond: -// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK29-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK29: for.body: -// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK29-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK29-NEXT: br label [[FOR_INC:%.*]] -// CHECK29: for.inc: -// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK29-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK29-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK29-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK29: for.end: -// CHECK29-NEXT: ret i32 0 -// -// -// CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK30-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK30-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP7]]) -// CHECK30-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK30-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) -// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK30-NEXT: ret i32 [[TMP9]] -// -// -// CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK30-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK30-NEXT: entry: -// CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK30-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK30-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK30-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND:%.*]] -// CHECK30: for.cond: -// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK30-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK30: for.body: -// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK30-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK30-NEXT: br label [[FOR_INC:%.*]] -// CHECK30: for.inc: -// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK30-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK30-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK30-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK30: for.end: -// CHECK30-NEXT: ret i32 0 -// -// -// CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK31-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK31-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK31-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK31-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK31-NEXT: ret i32 [[TMP8]] -// -// -// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK31-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK31-NEXT: entry: -// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK31-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK31-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK31-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND:%.*]] -// CHECK31: for.cond: -// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK31-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK31: for.body: -// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK31-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK31-NEXT: br label [[FOR_INC:%.*]] -// CHECK31: for.inc: -// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK31-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK31-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK31-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK31: for.end: -// CHECK31-NEXT: ret i32 0 -// -// -// CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK32-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK32-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP6]]) -// CHECK32-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK32-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) -// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK32-NEXT: ret i32 [[TMP8]] -// -// -// CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK32-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK32-NEXT: entry: -// CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK32-NEXT: [[TE:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[TH:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[TE]], align 4 -// CHECK32-NEXT: store i32 128, i32* [[TH]], align 4 -// CHECK32-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND:%.*]] -// CHECK32: for.cond: -// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK32-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK32: for.body: -// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK32-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK32-NEXT: br label [[FOR_INC:%.*]] -// CHECK32: for.inc: -// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK32-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK32-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK32: for.end: -// CHECK32-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -55,12 +55,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -966,242 +966,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2:%.*]] -// CHECK5: for.cond2: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body4: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: br label [[FOR_INC7:%.*]] -// CHECK5: for.inc7: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end9: -// CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK5-NEXT: ret i32 [[TMP6]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END9:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2:%.*]] -// CHECK6: for.cond2: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body4: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: br label [[FOR_INC7:%.*]] -// CHECK6: for.inc7: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC8]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end9: -// CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 -// CHECK6-NEXT: ret i32 [[TMP6]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK7-NEXT: ret i32 [[TMP6]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i64 [[CONV]], 456 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 -// CHECK8-NEXT: ret i32 [[TMP6]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3699,475 +3463,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP17]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1:%.*]] -// CHECK13: for.cond1: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK13-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body3: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK13-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: br label [[FOR_INC6:%.*]] -// CHECK13: for.inc6: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end8: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]] -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP11:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP11]] -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP15]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP17]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1:%.*]] -// CHECK14: for.cond1: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK14-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body3: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM4]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK14-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: br label [[FOR_INC6:%.*]] -// CHECK14: for.inc6: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC7]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end8: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP15]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1:%.*]] -// CHECK15: for.cond1: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK15-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body3: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK15-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: store i32 2, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = mul nsw i32 [[TMP8]], [[TMP1]] -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP10]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP13]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP15]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1:%.*]] -// CHECK16: for.cond1: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK16-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body3: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP2]] -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP3]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX4]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[J]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[J]], align 4 -// CHECK16-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1740,230 +1740,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @x, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -2349,29 +2125,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK11-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK12-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -11,12 +11,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -69,12 +69,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -2389,320 +2389,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3:%.*]] -// CHECK5: for.cond3: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK5: for.body5: -// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK5-NEXT: br label [[FOR_INC9:%.*]] -// CHECK5: for.inc9: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end11: -// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13:%.*]] -// CHECK5: for.cond13: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK5: for.body15: -// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK5-NEXT: br label [[FOR_INC19:%.*]] -// CHECK5: for.inc19: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK5: for.end21: -// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK5-NEXT: ret i32 [[TMP9]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3:%.*]] -// CHECK6: for.cond3: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK6: for.body5: -// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK6-NEXT: br label [[FOR_INC9:%.*]] -// CHECK6: for.inc9: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end11: -// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13:%.*]] -// CHECK6: for.cond13: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK6: for.body15: -// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK6-NEXT: br label [[FOR_INC19:%.*]] -// CHECK6: for.inc19: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK6: for.end21: -// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4 -// CHECK6-NEXT: ret i32 [[TMP9]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK7-NEXT: br label [[FOR_INC8:%.*]] -// CHECK7: for.inc8: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end10: -// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12:%.*]] -// CHECK7: for.cond12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK7: for.body14: -// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK7-NEXT: br label [[FOR_INC17:%.*]] -// CHECK7: for.inc17: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end19: -// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK8-NEXT: br label [[FOR_INC8:%.*]] -// CHECK8: for.inc8: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end10: -// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12:%.*]] -// CHECK8: for.cond12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK8: for.body14: -// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK8-NEXT: br label [[FOR_INC17:%.*]] -// CHECK8: for.inc17: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end19: -// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -8650,645 +8336,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK13-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP18]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2:%.*]] -// CHECK13: for.cond2: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK13: for.body4: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK13-NEXT: br label [[FOR_INC7:%.*]] -// CHECK13: for.inc7: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK13: for.end9: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11:%.*]] -// CHECK13: for.cond11: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK13: for.body13: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK13-NEXT: br label [[FOR_INC16:%.*]] -// CHECK13: for.inc16: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK13: for.end18: -// CHECK13-NEXT: ret i32 0 -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK14-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]]) -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP18]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2:%.*]] -// CHECK14: for.cond2: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK14: for.body4: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK14-NEXT: br label [[FOR_INC7:%.*]] -// CHECK14: for.inc7: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK14: for.end9: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11:%.*]] -// CHECK14: for.cond11: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK14: for.body13: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK14-NEXT: br label [[FOR_INC16:%.*]] -// CHECK14: for.inc16: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK14: for.end18: -// CHECK14-NEXT: ret i32 0 -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK15-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP17]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK15-NEXT: br label [[FOR_INC6:%.*]] -// CHECK15: for.inc6: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end8: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10:%.*]] -// CHECK15: for.cond10: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK15: for.body12: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK15-NEXT: br label [[FOR_INC14:%.*]] -// CHECK15: for.inc14: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end16: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK16-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]]) -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP17]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK16-NEXT: br label [[FOR_INC6:%.*]] -// CHECK16: for.inc6: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end8: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10:%.*]] -// CHECK16: for.cond10: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK16: for.body12: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK16-NEXT: br label [[FOR_INC14:%.*]] -// CHECK16: for.inc14: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end16: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -4372,1194 +4372,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP14]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK6-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP14]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK7-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP14]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK8-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK8-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP14]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -6267,267 +5079,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp @@ -3,33 +3,33 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple aarch64-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple aarch64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2787,328 +2787,6 @@ // CHECK2-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z9gtid_testv() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: call void @_Z3fn4v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z3fn5v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: -// CHECK3-NEXT: call void @_Z3fn6v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: call void @_Z3fn1v() -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: call void @_Z3fn2v() -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9:%.*]] -// CHECK3: for.cond9: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK3-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK3: for.body11: -// CHECK3-NEXT: call void @_Z3fn3v() -// CHECK3-NEXT: br label [[FOR_INC12:%.*]] -// CHECK3: for.inc12: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK3-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK3-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK3-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK3: for.end14: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z9gtid_testv() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: call void @_Z3fn4v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z3fn5v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: -// CHECK4-NEXT: call void @_Z3fn6v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: call void @_Z3fn1v() -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: call void @_Z3fn2v() -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9:%.*]] -// CHECK4: for.cond9: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK4-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK4: for.body11: -// CHECK4-NEXT: call void @_Z3fn3v() -// CHECK4-NEXT: br label [[FOR_INC12:%.*]] -// CHECK4: for.inc12: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK4-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK4-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK4-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK4: for.end14: -// CHECK4-NEXT: ret i32 0 -// -// // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: @@ -5783,328 +5461,6 @@ // CHECK6-NEXT: ret void // // -// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z9gtid_testv() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: call void @_Z3fn4v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z3fn5v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: call void @_Z3fn6v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: call void @_Z3fn1v() -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: call void @_Z3fn2v() -// CHECK7-NEXT: br label [[FOR_INC5:%.*]] -// CHECK7: for.inc5: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK7: for.end7: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9:%.*]] -// CHECK7: for.cond9: -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK7-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK7: for.body11: -// CHECK7-NEXT: call void @_Z3fn3v() -// CHECK7-NEXT: br label [[FOR_INC12:%.*]] -// CHECK7: for.inc12: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK7-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK7-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK7-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK7: for.end14: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z9gtid_testv() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: call void @_Z3fn4v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z3fn5v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: call void @_Z3fn6v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: call void @_Z3fn1v() -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: call void @_Z3fn2v() -// CHECK8-NEXT: br label [[FOR_INC5:%.*]] -// CHECK8: for.inc5: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK8: for.end7: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9:%.*]] -// CHECK8: for.cond9: -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK8-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK8: for.body11: -// CHECK8-NEXT: call void @_Z3fn3v() -// CHECK8-NEXT: br label [[FOR_INC12:%.*]] -// CHECK8: for.inc12: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK8-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK8-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK8-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK8: for.end14: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -8779,328 +8135,6 @@ // CHECK10-NEXT: ret void // // -// CHECK11-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z9gtid_testv() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn4v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn5v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn6v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK11-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: call void @_Z3fn1v() -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2:%.*]] -// CHECK11: for.cond2: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK11-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK11: for.body4: -// CHECK11-NEXT: call void @_Z3fn2v() -// CHECK11-NEXT: br label [[FOR_INC5:%.*]] -// CHECK11: for.inc5: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK11-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK11-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK11-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK11: for.end7: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9:%.*]] -// CHECK11: for.cond9: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK11-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK11: for.body11: -// CHECK11-NEXT: call void @_Z3fn3v() -// CHECK11-NEXT: br label [[FOR_INC12:%.*]] -// CHECK11: for.inc12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK11-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK11-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK11-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK11: for.end14: -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z9gtid_testv() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn4v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn5v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn6v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK12-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: call void @_Z3fn1v() -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2:%.*]] -// CHECK12: for.cond2: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK12-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK12: for.body4: -// CHECK12-NEXT: call void @_Z3fn2v() -// CHECK12-NEXT: br label [[FOR_INC5:%.*]] -// CHECK12: for.inc5: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK12-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK12-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK12-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK12: for.end7: -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9:%.*]] -// CHECK12: for.cond9: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK12-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK12: for.body11: -// CHECK12-NEXT: call void @_Z3fn3v() -// CHECK12-NEXT: br label [[FOR_INC12:%.*]] -// CHECK12: for.inc12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK12-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK12-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK12-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK12: for.end14: -// CHECK12-NEXT: ret i32 0 -// -// // CHECK13-LABEL: define {{[^@]+}}@_Z9gtid_testv // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -11774,325 +10808,4 @@ // CHECK14-NEXT: call void @__tgt_register_requires(i64 1) // CHECK14-NEXT: ret void // -// -// CHECK15-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z9gtid_testv() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn4v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn5v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn6v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK15-NEXT: ret i32 [[CALL]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK15-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: call void @_Z3fn1v() -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2:%.*]] -// CHECK15: for.cond2: -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK15: for.body4: -// CHECK15-NEXT: call void @_Z3fn2v() -// CHECK15-NEXT: br label [[FOR_INC5:%.*]] -// CHECK15: for.inc5: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK15-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK15-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK15: for.end7: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK15-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9:%.*]] -// CHECK15: for.cond9: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK15-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK15: for.body11: -// CHECK15-NEXT: call void @_Z3fn3v() -// CHECK15-NEXT: br label [[FOR_INC12:%.*]] -// CHECK15: for.inc12: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK15-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK15-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK15-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK15: for.end14: -// CHECK15-NEXT: ret i32 0 -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z9gtid_testv -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z9gtid_testv() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn4v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn5v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn6v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP7]]) -// CHECK16-NEXT: ret i32 [[CALL]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK16-NEXT: [[I8:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: call void @_Z3fn1v() -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2:%.*]] -// CHECK16: for.cond2: -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK16: for.body4: -// CHECK16-NEXT: call void @_Z3fn2v() -// CHECK16-NEXT: br label [[FOR_INC5:%.*]] -// CHECK16: for.inc5: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK16-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK16-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK16: for.end7: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 -// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 -// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 -// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK16-NEXT: store i32 0, i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9:%.*]] -// CHECK16: for.cond9: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP5]], 100 -// CHECK16-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END14:%.*]] -// CHECK16: for.body11: -// CHECK16-NEXT: call void @_Z3fn3v() -// CHECK16-NEXT: br label [[FOR_INC12:%.*]] -// CHECK16: for.inc12: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I8]], align 4 -// CHECK16-NEXT: [[INC13:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK16-NEXT: store i32 [[INC13]], i32* [[I8]], align 4 -// CHECK16-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK16: for.end14: -// CHECK16-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1247,78 +1247,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store double* [[G]], double** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 -// CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store double* [[G]], double** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 -// CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -5278,1107 +5206,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK13-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND:%.*]] -// CHECK13: for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK13: for.body: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK13-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK13-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK13-NEXT: br label [[FOR_INC:%.*]] -// CHECK13: for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK13: for.end: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done4: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP14]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK14-NEXT: [[G1:%.*]] = alloca double*, align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done5: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 -// CHECK14-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND:%.*]] -// CHECK14: for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK14: for.body: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK14-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK14-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* -// CHECK14-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) -// CHECK14-NEXT: br label [[FOR_INC:%.*]] -// CHECK14: for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK14: for.end: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done4: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP14]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK15-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done4: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND:%.*]] -// CHECK15: for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK15: for.body: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK15-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK15-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK15-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK15-NEXT: br label [[FOR_INC:%.*]] -// CHECK15: for.inc: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK15: for.end: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP14]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[G:%.*]] = alloca double, align 8 -// CHECK16-NEXT: [[G1:%.*]] = alloca double*, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S* [[TMP3]], %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done4: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND:%.*]] -// CHECK16: for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], 2 -// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK16: for.body: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP7]] -// CHECK16-NEXT: store i32 [[TMP6]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP9]] -// CHECK16-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// CHECK16-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[TMP8]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) -// CHECK16-NEXT: br label [[FOR_INC:%.*]] -// CHECK16: for.inc: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK16: for.end: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done3: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP14]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp @@ -3,17 +3,17 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-ibm-linux-gnu -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2377,524 +2377,6 @@ // CHECK2-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: lpad: -// CHECK3-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: cleanup -// CHECK3-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK3-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK3-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] -// CHECK3-NEXT: br label [[EH_RESUME:%.*]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK3-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont6: -// CHECK3-NEXT: br label [[FOR_INC7:%.*]] -// CHECK3: for.inc7: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK3-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end9: -// CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK3-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont10: -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK3-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK3: invoke.cont12: -// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK3-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP9]] -// CHECK3: eh.resume: -// CHECK3-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK3-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK3-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK3-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK3-NEXT: ret i8 [[CONV]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK3-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont5: -// CHECK3-NEXT: br label [[FOR_INC6:%.*]] -// CHECK3: for.inc6: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK3: for.end8: -// CHECK3-NEXT: ret i32 0 -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK3-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK3-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK3: invoke.cont: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont1: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK3-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK3-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3:%.*]] -// CHECK3: for.cond3: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK3-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK3: for.body5: -// CHECK3-NEXT: invoke void @_Z3foov() -// CHECK3-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK3: invoke.cont6: -// CHECK3-NEXT: br label [[FOR_INC7:%.*]] -// CHECK3: for.inc7: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK3-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK3-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK3: for.end9: -// CHECK3-NEXT: ret i32 0 -// CHECK3: terminate.lpad: -// CHECK3-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK3-NEXT: catch i8* null -// CHECK3-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK3-NEXT: unreachable -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: lpad: -// CHECK4-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: cleanup -// CHECK4-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK4-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK4-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] -// CHECK4-NEXT: br label [[EH_RESUME:%.*]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK4-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont6: -// CHECK4-NEXT: br label [[FOR_INC7:%.*]] -// CHECK4: for.inc7: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK4-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end9: -// CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK4-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont10: -// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK4-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK4-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK4: invoke.cont12: -// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK4-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: ret i32 [[TMP9]] -// CHECK4: eh.resume: -// CHECK4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK4-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK4-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK4-NEXT: ret i8 [[CONV]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK4-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont5: -// CHECK4-NEXT: br label [[FOR_INC6:%.*]] -// CHECK4: for.inc6: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK4: for.end8: -// CHECK4-NEXT: ret i32 0 -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK4-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK4-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK4: invoke.cont: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK4-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont1: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK4-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK4-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3:%.*]] -// CHECK4: for.cond3: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK4-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK4: for.body5: -// CHECK4-NEXT: invoke void @_Z3foov() -// CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK4: invoke.cont6: -// CHECK4-NEXT: br label [[FOR_INC7:%.*]] -// CHECK4: for.inc7: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK4-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK4-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK4: for.end9: -// CHECK4-NEXT: ret i32 0 -// CHECK4: terminate.lpad: -// CHECK4-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK4-NEXT: catch i8* null -// CHECK4-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK4-NEXT: unreachable -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK4-NEXT: ret void -// -// -// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: ret void -// -// // CHECK5-LABEL: define {{[^@]+}}@main // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: @@ -5198,521 +4680,4 @@ // CHECK6-NEXT: call void @__tgt_register_requires(i64 1) // CHECK6-NEXT: ret void // -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK7-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK7-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont1: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK7: lpad: -// CHECK7-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: cleanup -// CHECK7-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK7-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK7-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] -// CHECK7-NEXT: br label [[EH_RESUME:%.*]] -// CHECK7: for.end: -// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont6: -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK7-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont10: -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK7-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK7-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK7: invoke.cont12: -// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK7-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP9]] -// CHECK7: eh.resume: -// CHECK7-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK7-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK7-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK7-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK7-NEXT: ret i8 [[CONV]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK7-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2:%.*]] -// CHECK7: for.cond2: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK7: for.body4: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont5: -// CHECK7-NEXT: br label [[FOR_INC6:%.*]] -// CHECK7: for.inc6: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK7-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK7: for.end8: -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK7-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK7: invoke.cont: -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK7-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont1: -// CHECK7-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK7-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3:%.*]] -// CHECK7: for.cond3: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK7: for.body5: -// CHECK7-NEXT: invoke void @_Z3foov() -// CHECK7-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK7: invoke.cont6: -// CHECK7-NEXT: br label [[FOR_INC7:%.*]] -// CHECK7: for.inc7: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK7-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK7: for.end9: -// CHECK7-NEXT: ret i32 0 -// CHECK7: terminate.lpad: -// CHECK7-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK7-NEXT: catch i8* null -// CHECK7-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK7-NEXT: unreachable -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 -// CHECK8-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) -// CHECK8-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: store i8 [[CALL]], i8* [[A]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont1: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK8: lpad: -// CHECK8-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: cleanup -// CHECK8-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0 -// CHECK8-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 -// CHECK8-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] -// CHECK8-NEXT: br label [[EH_RESUME:%.*]] -// CHECK8: for.end: -// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: store i8 [[TMP5]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP6]], 100 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont6: -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: [[TMP8:%.*]] = load i8, i8* [[A]], align 1 -// CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK8-NEXT: [[CALL11:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT10:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont10: -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL11]] -// CHECK8-NEXT: [[CALL13:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() -// CHECK8-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[LPAD]] -// CHECK8: invoke.cont12: -// CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CALL13]] -// CHECK8-NEXT: store i32 [[ADD14]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP9]] -// CHECK8: eh.resume: -// CHECK8-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 -// CHECK8-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 -// CHECK8-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 -// CHECK8-NEXT: resume { i8*, i32 } [[LPAD_VAL15]] -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP10:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP11:%.*]] = extractvalue { i8*, i32 } [[TMP10]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7:[0-9]+]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A]], align 8 -// CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 -// CHECK8-NEXT: ret i8 [[CONV]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { -// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]] -// CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv -// CHECK8-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2:%.*]] -// CHECK8: for.cond2: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK8: for.body4: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont5: -// CHECK8-NEXT: br label [[FOR_INC6:%.*]] -// CHECK8: for.inc6: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK8-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK8: for.end8: -// CHECK8-NEXT: ret i32 0 -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv -// CHECK8-SAME: () #[[ATTR2]] comdat personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 -// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 100 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] -// CHECK8: invoke.cont: -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK8-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont1: -// CHECK8-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] -// CHECK8-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3:%.*]] -// CHECK8: for.cond3: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], 100 -// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END9:%.*]] -// CHECK8: for.body5: -// CHECK8-NEXT: invoke void @_Z3foov() -// CHECK8-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] -// CHECK8: invoke.cont6: -// CHECK8-NEXT: br label [[FOR_INC7:%.*]] -// CHECK8: for.inc7: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK8-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC8]], i32* [[I2]], align 4 -// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK8: for.end9: -// CHECK8-NEXT: ret i32 0 -// CHECK8: terminate.lpad: -// CHECK8-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK8-NEXT: catch i8* null -// CHECK8-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0 -// CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]] -// CHECK8-NEXT: unreachable -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: store i64 [[TMP0]], i64* [[A2]], align 8 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2890,1386 +2890,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done7: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK7: arraydestroy.body9: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK7: arraydestroy.done13: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done7: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK8: arraydestroy.body9: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK8: arraydestroy.done13: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -4885,267 +3505,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp @@ -5,9 +5,9 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -975,123 +975,4 @@ // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2:%.*]] -// CHECK3: for.cond2: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK3-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK3: for.body4: -// CHECK3-NEXT: br label [[FOR_INC5:%.*]] -// CHECK3: for.inc5: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK3-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK3-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK3: for.end7: -// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK3-NEXT: ret i32 [[CALL]] -// -// -// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK3-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: ret i32 0 -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2:%.*]] -// CHECK4: for.cond2: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], 1000 -// CHECK4-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END7:%.*]] -// CHECK4: for.body4: -// CHECK4-NEXT: br label [[FOR_INC5:%.*]] -// CHECK4: for.inc5: -// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK4-NEXT: [[INC6:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK4-NEXT: store i32 [[INC6]], i32* [[I1]], align 4 -// CHECK4-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK4: for.end7: -// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK4-NEXT: ret i32 [[CALL]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK4-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND:%.*]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 1000 -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK4-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2361,238 +2361,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3126,23 +2894,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp @@ -3,9 +3,9 @@ // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-linux -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -triple x86_64-unknown-linux -verify -fopenmp-simd -fopenmp-version=50 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -1909,62 +1909,4 @@ // CHECK2: omp.arraycpy.done5: // CHECK2-NEXT: ret void // -// -// CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK3-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: store i64 0, i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND:%.*]] -// CHECK3: for.cond: -// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10 -// CHECK3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK3: for.body: -// CHECK3-NEXT: br label [[FOR_INC:%.*]] -// CHECK3: for.inc: -// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 -// CHECK3-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1 -// CHECK3-NEXT: store i64 [[INC]], i64* [[I]], align 8 -// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK3: for.end: -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: ret i32 [[TMP2]] -// -// -// CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { -// CHECK4-NEXT: entry: -// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 -// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] -// CHECK4-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META16:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17:![0-9]+]] -// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[I]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -// CHECK4-NEXT: store i64 0, i64* [[I]], align 8, !dbg [[DBG23]] -// CHECK4-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG24:![0-9]+]] -// CHECK4: for.cond: -// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG25:![0-9]+]] -// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP0]], 10, !dbg [[DBG27:![0-9]+]] -// CHECK4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG28:![0-9]+]] -// CHECK4: for.body: -// CHECK4-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG29:![0-9]+]] -// CHECK4: for.inc: -// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG31:![0-9]+]] -// CHECK4-NEXT: [[INC:%.*]] = add nsw i64 [[TMP1]], 1, !dbg [[DBG31]] -// CHECK4-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG31]] -// CHECK4-NEXT: br label [[FOR_COND]], !dbg [[DBG32:![0-9]+]], !llvm.loop [[LOOP33:![0-9]+]] -// CHECK4: for.end: -// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] -// CHECK4-NEXT: ret i32 [[TMP2]], !dbg [[DBG36]] -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp @@ -18,12 +18,12 @@ // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK1 template @@ -101,12 +101,12 @@ // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" #ifdef CK2 template @@ -7416,476 +7416,6 @@ // CHECK8-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK9-NEXT: ret i32 [[CALL]] -// -// -// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND:%.*]] -// CHECK9: for.cond: -// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK9: for.body: -// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK9-NEXT: br label [[FOR_INC:%.*]] -// CHECK9: for.inc: -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK9-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK9-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK9: for.end: -// CHECK9-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3:%.*]] -// CHECK9: for.cond3: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK9-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK9: for.body5: -// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK9-NEXT: br label [[FOR_INC9:%.*]] -// CHECK9: for.inc9: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK9-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK9-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK9-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK9: for.end11: -// CHECK9-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13:%.*]] -// CHECK9: for.cond13: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK9-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK9: for.body15: -// CHECK9-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK9-NEXT: br label [[FOR_INC19:%.*]] -// CHECK9: for.inc19: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK9-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK9-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK9-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK9: for.end21: -// CHECK9-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23:%.*]] -// CHECK9: for.cond23: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK9-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK9: for.body25: -// CHECK9-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK9-NEXT: br label [[FOR_INC29:%.*]] -// CHECK9: for.inc29: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK9-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK9-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK9-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK9: for.end31: -// CHECK9-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33:%.*]] -// CHECK9: for.cond33: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK9-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK9: for.body35: -// CHECK9-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK9-NEXT: br label [[FOR_INC39:%.*]] -// CHECK9: for.inc39: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK9-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK9-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK9: for.end41: -// CHECK9-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK9-NEXT: ret i32 [[TMP15]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK10-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK10-NEXT: ret i32 [[CALL]] -// -// -// CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK10-NEXT: entry: -// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I12:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I22:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: [[I32:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND:%.*]] -// CHECK10: for.cond: -// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK10: for.body: -// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK10-NEXT: br label [[FOR_INC:%.*]] -// CHECK10: for.inc: -// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK10-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK10-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK10: for.end: -// CHECK10-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3:%.*]] -// CHECK10: for.cond3: -// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK10-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]] -// CHECK10: for.body5: -// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 -// CHECK10-NEXT: br label [[FOR_INC9:%.*]] -// CHECK10: for.inc9: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK10-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK10-NEXT: store i32 [[INC10]], i32* [[I2]], align 4 -// CHECK10-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK10: for.end11: -// CHECK10-NEXT: store i32 0, i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13:%.*]] -// CHECK10: for.cond13: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK10-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]] -// CHECK10: for.body15: -// CHECK10-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4 -// CHECK10-NEXT: br label [[FOR_INC19:%.*]] -// CHECK10: for.inc19: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4 -// CHECK10-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK10-NEXT: store i32 [[INC20]], i32* [[I12]], align 4 -// CHECK10-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK10: for.end21: -// CHECK10-NEXT: store i32 0, i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23:%.*]] -// CHECK10: for.cond23: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[CMP24:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK10-NEXT: br i1 [[CMP24]], label [[FOR_BODY25:%.*]], label [[FOR_END31:%.*]] -// CHECK10: for.body25: -// CHECK10-NEXT: [[A26:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[IDXPROM27:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A26]], i64 0, i64 [[IDXPROM27]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX28]], align 4 -// CHECK10-NEXT: br label [[FOR_INC29:%.*]] -// CHECK10: for.inc29: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I22]], align 4 -// CHECK10-NEXT: [[INC30:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK10-NEXT: store i32 [[INC30]], i32* [[I22]], align 4 -// CHECK10-NEXT: br label [[FOR_COND23]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK10: for.end31: -// CHECK10-NEXT: store i32 0, i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33:%.*]] -// CHECK10: for.cond33: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[CMP34:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK10-NEXT: br i1 [[CMP34]], label [[FOR_BODY35:%.*]], label [[FOR_END41:%.*]] -// CHECK10: for.body35: -// CHECK10-NEXT: [[A36:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A36]], i64 0, i64 [[IDXPROM37]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 -// CHECK10-NEXT: br label [[FOR_INC39:%.*]] -// CHECK10: for.inc39: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I32]], align 4 -// CHECK10-NEXT: [[INC40:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[INC40]], i32* [[I32]], align 4 -// CHECK10-NEXT: br label [[FOR_COND33]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK10: for.end41: -// CHECK10-NEXT: [[A42:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK10-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A42]], i64 0, i64 0 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX43]], align 4 -// CHECK10-NEXT: ret i32 [[TMP15]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK11-NEXT: ret i32 [[CALL]] -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND:%.*]] -// CHECK11: for.cond: -// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK11-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK11: for.body: -// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK11-NEXT: br label [[FOR_INC:%.*]] -// CHECK11: for.inc: -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK11-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK11-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK11: for.end: -// CHECK11-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3:%.*]] -// CHECK11: for.cond3: -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK11-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK11: for.body5: -// CHECK11-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: br label [[FOR_INC8:%.*]] -// CHECK11: for.inc8: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK11-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK11-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK11-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK11: for.end10: -// CHECK11-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12:%.*]] -// CHECK11: for.cond12: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK11-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK11: for.body14: -// CHECK11-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK11-NEXT: br label [[FOR_INC17:%.*]] -// CHECK11: for.inc17: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK11-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK11-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK11-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK11: for.end19: -// CHECK11-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21:%.*]] -// CHECK11: for.cond21: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK11-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK11: for.body23: -// CHECK11-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK11-NEXT: br label [[FOR_INC26:%.*]] -// CHECK11: for.inc26: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK11-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK11-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK11: for.end28: -// CHECK11-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30:%.*]] -// CHECK11: for.cond30: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK11-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK11: for.body32: -// CHECK11-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK11-NEXT: br label [[FOR_INC35:%.*]] -// CHECK11: for.inc35: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK11-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK11-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK11: for.end37: -// CHECK11-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK11-NEXT: ret i32 [[TMP15]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_Z21teams_template_structv -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) -// CHECK12-NEXT: ret i32 [[CALL]] -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND:%.*]] -// CHECK12: for.cond: -// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123 -// CHECK12-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK12: for.body: -// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK12-NEXT: br label [[FOR_INC:%.*]] -// CHECK12: for.inc: -// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK12-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK12-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK12: for.end: -// CHECK12-NEXT: store i32 0, i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3:%.*]] -// CHECK12: for.cond3: -// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123 -// CHECK12-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]] -// CHECK12: for.body5: -// CHECK12-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 -// CHECK12-NEXT: br label [[FOR_INC8:%.*]] -// CHECK12: for.inc8: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4 -// CHECK12-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK12-NEXT: store i32 [[INC9]], i32* [[I2]], align 4 -// CHECK12-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK12: for.end10: -// CHECK12-NEXT: store i32 0, i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12:%.*]] -// CHECK12: for.cond12: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123 -// CHECK12-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]] -// CHECK12: for.body14: -// CHECK12-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4 -// CHECK12-NEXT: br label [[FOR_INC17:%.*]] -// CHECK12: for.inc17: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4 -// CHECK12-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK12-NEXT: store i32 [[INC18]], i32* [[I11]], align 4 -// CHECK12-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK12: for.end19: -// CHECK12-NEXT: store i32 0, i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21:%.*]] -// CHECK12: for.cond21: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[CMP22:%.*]] = icmp slt i32 [[TMP9]], 123 -// CHECK12-NEXT: br i1 [[CMP22]], label [[FOR_BODY23:%.*]], label [[FOR_END28:%.*]] -// CHECK12: for.body23: -// CHECK12-NEXT: [[A24:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A24]], i32 0, i32 [[TMP10]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX25]], align 4 -// CHECK12-NEXT: br label [[FOR_INC26:%.*]] -// CHECK12: for.inc26: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I20]], align 4 -// CHECK12-NEXT: [[INC27:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[INC27]], i32* [[I20]], align 4 -// CHECK12-NEXT: br label [[FOR_COND21]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK12: for.end28: -// CHECK12-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30:%.*]] -// CHECK12: for.cond30: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP12]], 123 -// CHECK12-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK12: for.body32: -// CHECK12-NEXT: [[A33:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A33]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK12-NEXT: br label [[FOR_INC35:%.*]] -// CHECK12: for.inc35: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK12-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK12-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK12: for.end37: -// CHECK12-NEXT: [[A38:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A38]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX39]], align 4 -// CHECK12-NEXT: ret i32 [[TMP15]] -// -// // CHECK13-LABEL: define {{[^@]+}}@main // CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: @@ -27313,973 +26843,4 @@ // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: ret void // -// -// CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK21-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK21-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK21-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK21-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK21-NEXT: ret i32 [[TMP27]] -// -// -// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK21-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK21-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND:%.*]] -// CHECK21: for.cond: -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK21-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK21: for.body: -// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK21-NEXT: br label [[FOR_INC:%.*]] -// CHECK21: for.inc: -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK21-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK21-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK21: for.end: -// CHECK21-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2:%.*]] -// CHECK21: for.cond2: -// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK21-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK21: for.body4: -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK21-NEXT: br label [[FOR_INC7:%.*]] -// CHECK21: for.inc7: -// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK21-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK21-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK21-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK21: for.end9: -// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11:%.*]] -// CHECK21: for.cond11: -// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK21-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK21: for.body13: -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK21-NEXT: br label [[FOR_INC16:%.*]] -// CHECK21: for.inc16: -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK21-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK21-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK21-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK21: for.end18: -// CHECK21-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20:%.*]] -// CHECK21: for.cond20: -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK21-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK21: for.body22: -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK21-NEXT: br label [[FOR_INC25:%.*]] -// CHECK21: for.inc25: -// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK21-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK21-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK21-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK21: for.end27: -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK21-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30:%.*]] -// CHECK21: for.cond30: -// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK21-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK21: for.body32: -// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK21-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK21-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK21-NEXT: br label [[FOR_INC35:%.*]] -// CHECK21: for.inc35: -// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK21-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK21-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK21-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK21: for.end37: -// CHECK21-NEXT: ret i32 0 -// -// -// CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 -// CHECK22-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 -// CHECK22-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 -// CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]] -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]] -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP16]], [[TMP17]] -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[N]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP25]]) -// CHECK22-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK22-NEXT: [[TMP26:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP26]]) -// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: ret i32 [[TMP27]] -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK22-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK22-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I10:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I19:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[I29:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND:%.*]] -// CHECK22: for.cond: -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK22-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK22: for.body: -// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK22-NEXT: br label [[FOR_INC:%.*]] -// CHECK22: for.inc: -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK22-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK22-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK22: for.end: -// CHECK22-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2:%.*]] -// CHECK22: for.cond2: -// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK22-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]] -// CHECK22: for.body4: -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4 -// CHECK22-NEXT: br label [[FOR_INC7:%.*]] -// CHECK22: for.inc7: -// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK22-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK22-NEXT: store i32 [[INC8]], i32* [[I1]], align 4 -// CHECK22-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK22: for.end9: -// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11:%.*]] -// CHECK22: for.cond11: -// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK22-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]] -// CHECK22: for.body13: -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK22-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4 -// CHECK22-NEXT: br label [[FOR_INC16:%.*]] -// CHECK22: for.inc16: -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[I10]], align 4 -// CHECK22-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK22-NEXT: store i32 [[INC17]], i32* [[I10]], align 4 -// CHECK22-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK22: for.end18: -// CHECK22-NEXT: store i32 0, i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20:%.*]] -// CHECK22: for.cond20: -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK22-NEXT: br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END27:%.*]] -// CHECK22: for.body22: -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK22-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM23]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX24]], align 4 -// CHECK22-NEXT: br label [[FOR_INC25:%.*]] -// CHECK22: for.inc25: -// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[I19]], align 4 -// CHECK22-NEXT: [[INC26:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK22-NEXT: store i32 [[INC26]], i32* [[I19]], align 4 -// CHECK22-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK22: for.end27: -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_28]], align 4 -// CHECK22-NEXT: store i32 0, i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30:%.*]] -// CHECK22: for.cond30: -// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK22-NEXT: br i1 [[CMP31]], label [[FOR_BODY32:%.*]], label [[FOR_END37:%.*]] -// CHECK22: for.body32: -// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK22-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM33]] -// CHECK22-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4 -// CHECK22-NEXT: br label [[FOR_INC35:%.*]] -// CHECK22: for.inc35: -// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I29]], align 4 -// CHECK22-NEXT: [[INC36:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK22-NEXT: store i32 [[INC36]], i32* [[I29]], align 4 -// CHECK22-NEXT: br label [[FOR_COND30]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK22: for.end37: -// CHECK22-NEXT: ret i32 0 -// -// -// CHECK23-LABEL: define {{[^@]+}}@main -// CHECK23-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK23-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK23-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK23-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK23-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK23-NEXT: ret i32 [[TMP26]] -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK23-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK23-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND:%.*]] -// CHECK23: for.cond: -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK23-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK23: for.body: -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK23-NEXT: br label [[FOR_INC:%.*]] -// CHECK23: for.inc: -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK23-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK23-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK23: for.end: -// CHECK23-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2:%.*]] -// CHECK23: for.cond2: -// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK23-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK23: for.body4: -// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK23-NEXT: br label [[FOR_INC6:%.*]] -// CHECK23: for.inc6: -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK23-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK23-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK23-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK23: for.end8: -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10:%.*]] -// CHECK23: for.cond10: -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK23-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK23: for.body12: -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK23-NEXT: br label [[FOR_INC14:%.*]] -// CHECK23: for.inc14: -// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK23-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK23-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK23-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK23: for.end16: -// CHECK23-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18:%.*]] -// CHECK23: for.cond18: -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK23-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK23: for.body20: -// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK23-NEXT: br label [[FOR_INC22:%.*]] -// CHECK23: for.inc22: -// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK23-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK23-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK23-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK23: for.end24: -// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK23-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27:%.*]] -// CHECK23: for.cond27: -// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK23-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK23: for.body29: -// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK23-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK23-NEXT: br label [[FOR_INC31:%.*]] -// CHECK23: for.inc31: -// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK23-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK23-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK23-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK23: for.end33: -// CHECK23-NEXT: ret i32 0 -// -// -// CHECK24-LABEL: define {{[^@]+}}@main -// CHECK24-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 -// CHECK24-NEXT: [[N:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 -// CHECK24-NEXT: store i32 100, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 -// CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]] -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]] -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP15]], [[TMP16]] -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP17]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[N]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP22]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP24]]) -// CHECK24-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK24-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) -// CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK24-NEXT: ret i32 [[TMP26]] -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK24-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 -// CHECK24-NEXT: [[M:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I9:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I17:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[I26:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: store i32 10, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND:%.*]] -// CHECK24: for.cond: -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 -// CHECK24-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK24: for.body: -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 -// CHECK24-NEXT: br label [[FOR_INC:%.*]] -// CHECK24: for.inc: -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK24-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK24-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] -// CHECK24: for.end: -// CHECK24-NEXT: store i32 0, i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2:%.*]] -// CHECK24: for.cond2: -// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10 -// CHECK24-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]] -// CHECK24: for.body4: -// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4 -// CHECK24-NEXT: br label [[FOR_INC6:%.*]] -// CHECK24: for.inc6: -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4 -// CHECK24-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK24-NEXT: store i32 [[INC7]], i32* [[I1]], align 4 -// CHECK24-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP10:![0-9]+]] -// CHECK24: for.end8: -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10:%.*]] -// CHECK24: for.cond10: -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP7]], 10 -// CHECK24-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]] -// CHECK24: for.body12: -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP8]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4 -// CHECK24-NEXT: br label [[FOR_INC14:%.*]] -// CHECK24: for.inc14: -// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[I9]], align 4 -// CHECK24-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK24-NEXT: store i32 [[INC15]], i32* [[I9]], align 4 -// CHECK24-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP11:![0-9]+]] -// CHECK24: for.end16: -// CHECK24-NEXT: store i32 0, i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18:%.*]] -// CHECK24: for.cond18: -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[CMP19:%.*]] = icmp slt i32 [[TMP10]], 10 -// CHECK24-NEXT: br i1 [[CMP19]], label [[FOR_BODY20:%.*]], label [[FOR_END24:%.*]] -// CHECK24: for.body20: -// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX21]], align 4 -// CHECK24-NEXT: br label [[FOR_INC22:%.*]] -// CHECK24: for.inc22: -// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[I17]], align 4 -// CHECK24-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK24-NEXT: store i32 [[INC23]], i32* [[I17]], align 4 -// CHECK24-NEXT: br label [[FOR_COND18]], !llvm.loop [[LOOP12:![0-9]+]] -// CHECK24: for.end24: -// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[M]], align 4 -// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_25]], align 4 -// CHECK24-NEXT: store i32 0, i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27:%.*]] -// CHECK24: for.cond27: -// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP14]], 10 -// CHECK24-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END33:%.*]] -// CHECK24: for.body29: -// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP15]] -// CHECK24-NEXT: store i32 0, i32* [[ARRAYIDX30]], align 4 -// CHECK24-NEXT: br label [[FOR_INC31:%.*]] -// CHECK24: for.inc31: -// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[I26]], align 4 -// CHECK24-NEXT: [[INC32:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK24-NEXT: store i32 [[INC32]], i32* [[I26]], align 4 -// CHECK24-NEXT: br label [[FOR_COND27]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK24: for.end33: -// CHECK24-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_private_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_private_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -2066,1386 +2066,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done4: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK5: arraydestroy.done8: -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK5: arraydestroy.body10: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK5: arraydestroy.done14: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: ret i32 [[TMP11]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init() -// CHECK5-NEXT: call void @__cxx_global_var_init.1() -// CHECK5-NEXT: call void @__cxx_global_var_init.2() -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done1: -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] -// CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done4: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK6: arrayctor.loop: -// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] -// CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* -// CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK6: arraydestroy.body: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK6: arraydestroy.done8: -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 -// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] -// CHECK6: arraydestroy.body10: -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] -// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] -// CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] -// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] -// CHECK6: arraydestroy.done14: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: ret i32 [[TMP11]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK6-SAME: () #[[ATTR0]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @__cxx_global_var_init() -// CHECK6-NEXT: call void @__cxx_global_var_init.1() -// CHECK6-NEXT: call void @__cxx_global_var_init.2() -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done1: -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done3: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK7: arrayctor.loop: -// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK7: arraydestroy.body: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK7: arraydestroy.done7: -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK7: arraydestroy.body9: -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK7: arraydestroy.done13: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: ret i32 [[TMP11]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK7-SAME: () #[[ATTR0]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @__cxx_global_var_init() -// CHECK7-NEXT: call void @__cxx_global_var_init.1() -// CHECK7-NEXT: call void @__cxx_global_var_init.2() -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 -// CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done1: -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] -// CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done3: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK8: arrayctor.loop: -// CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] -// CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] -// CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK8: arraydestroy.body: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK8: arraydestroy.done7: -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK8: arraydestroy.body9: -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] -// CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK8: arraydestroy.done13: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: ret i32 [[TMP11]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK8-SAME: () #[[ATTR0]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @__cxx_global_var_init() -// CHECK8-NEXT: call void @__cxx_global_var_init.1() -// CHECK8-NEXT: call void @__cxx_global_var_init.2() -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3907,267 +2527,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK11: arraydestroy.body: -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK11: arraydestroy.done1: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK11-SAME: () #[[ATTR0]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @__cxx_global_var_init() -// CHECK11-NEXT: call void @__cxx_global_var_init.1() -// CHECK11-NEXT: call void @__cxx_global_var_init.2() -// CHECK11-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 -// CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK12: arraydestroy.body: -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) -// CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK12: arraydestroy.done1: -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) -// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 -// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK12-NEXT: ret void -// -// -// CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp -// CHECK12-SAME: () #[[ATTR0]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @__cxx_global_var_init() -// CHECK12-NEXT: call void @__cxx_global_var_init.1() -// CHECK12-NEXT: call void @__cxx_global_var_init.2() -// CHECK12-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp --- a/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp @@ -6,20 +6,20 @@ // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER @@ -1406,238 +1406,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK5-NEXT: ret i32 [[CALL]] -// -// -// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK5-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND:%.*]] -// CHECK5: for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK5: for.body: -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK5-NEXT: br label [[FOR_INC:%.*]] -// CHECK5: for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK5: for.end: -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK6-NEXT: ret i32 [[CALL]] -// -// -// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK6-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND:%.*]] -// CHECK6: for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK6: for.body: -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK6-NEXT: br label [[FOR_INC:%.*]] -// CHECK6: for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// CHECK6: for.end: -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK7-NEXT: ret i32 [[CALL]] -// -// -// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK7-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND:%.*]] -// CHECK7: for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK7: for.body: -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK7-NEXT: br label [[FOR_INC:%.*]] -// CHECK7: for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK7: for.end: -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -// CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK8-NEXT: ret i32 [[CALL]] -// -// -// CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK8-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND:%.*]] -// CHECK8: for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 -// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK8: for.body: -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[T_VAR]], align 4 -// CHECK8-NEXT: br label [[FOR_INC:%.*]] -// CHECK8: for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 -// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] -// CHECK8: for.end: -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -1931,23 +1699,4 @@ // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // -// -// CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK11-NEXT: ret i32 0 -// -// -// CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK12-NEXT: entry: -// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK12-NEXT: ret i32 0 -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp --- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp @@ -7,12 +7,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping @@ -21,12 +21,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping @@ -35,12 +35,12 @@ // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK21 +// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK22 -// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK23 +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK24 +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -411,46 +411,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3351,922 +3311,6 @@ // CHECK12-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done2: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP5]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK13-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done2: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP5]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done2: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP5]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK15-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK15-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done2: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP5]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float -// CHECK16-NEXT: store float [[CONV]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float -// CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] -// CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 -// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: @@ -6214,355 +5258,4 @@ // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: ret void // -// -// CHECK21-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg -// CHECK21-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK21-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK21-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK21-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 -// CHECK21-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP11:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 signext [[TMP10]], ppc_fp128* [[TMP11]]) -// CHECK21-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK21-NEXT: ret void -// -// -// CHECK21-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg -// CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK21-NEXT: entry: -// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK21-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK21-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK21-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK21-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK21-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 -// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double -// CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] -// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 -// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK21-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK21-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to ppc_fp128 -// CHECK21-NEXT: [[TMP12:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK21-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK21-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP12]], i64 [[IDXPROM7]] -// CHECK21-NEXT: store ppc_fp128 [[CONV5]], ppc_fp128* [[ARRAYIDX8]], align 16 -// CHECK21-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK21-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg -// CHECK22-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK22-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK22-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK22-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 -// CHECK22-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP11:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 signext [[TMP10]], ppc_fp128* [[TMP11]]) -// CHECK22-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) -// CHECK22-NEXT: ret void -// -// -// CHECK22-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg -// CHECK22-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK22-NEXT: entry: -// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK22-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK22-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 -// CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 -// CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK22-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -// CHECK22-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() -// CHECK22-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] -// CHECK22-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 -// CHECK22-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 -// CHECK22-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 -// CHECK22-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 -// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 -// CHECK22-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK22-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 -// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double -// CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] -// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 -// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 -// CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] -// CHECK22-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK22-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to ppc_fp128 -// CHECK22-NEXT: [[TMP12:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 -// CHECK22-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK22-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP12]], i64 [[IDXPROM7]] -// CHECK22-NEXT: store ppc_fp128 [[CONV5]], ppc_fp128* [[ARRAYIDX8]], align 16 -// CHECK22-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) -// CHECK22-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK23-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK23-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK23-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[TMP5:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP5]], i32 0 -// CHECK23-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP8:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP6]], i32 [[TMP7]], x86_fp80* [[TMP8]]) -// CHECK23-NEXT: [[TMP9:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP9]]) -// CHECK23-NEXT: ret void -// -// -// CHECK23-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK23-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK23-NEXT: entry: -// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK23-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK23-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK23-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK23-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 -// CHECK23-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: store i32 [[TMP6]], i32* [[A3]], align 4 -// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i32 [[TMP7]] -// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 1 -// CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] -// CHECK23-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK23-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK23-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK23-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP9]], i32 [[TMP10]] -// CHECK23-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX7]], align 4 -// CHECK23-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK23-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe -// CHECK24-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 -// CHECK24-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 -// CHECK24-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[TMP5:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP5]], i32 0 -// CHECK24-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP8:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP6]], i32 [[TMP7]], x86_fp80* [[TMP8]]) -// CHECK24-NEXT: [[TMP9:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP9]]) -// CHECK24-NEXT: ret void -// -// -// CHECK24-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe -// CHECK24-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { -// CHECK24-NEXT: entry: -// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK24-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 -// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 -// CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 -// CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK24-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 -// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK24-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] -// CHECK24-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 -// CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK24-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 -// CHECK24-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B2]], align 4 -// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 -// CHECK24-NEXT: store i32 [[TMP6]], i32* [[A3]], align 4 -// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double -// CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i32 [[TMP7]] -// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 1 -// CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] -// CHECK24-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 -// CHECK24-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 -// CHECK24-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 -// CHECK24-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 -// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[B6]], align 4 -// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP9]], i32 [[TMP10]] -// CHECK24-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX7]], align 4 -// CHECK24-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) -// CHECK24-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_private_codegen.cpp b/clang/test/OpenMP/teams_private_codegen.cpp --- a/clang/test/OpenMP/teams_private_codegen.cpp +++ b/clang/test/OpenMP/teams_private_codegen.cpp @@ -6,12 +6,12 @@ // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 -// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s @@ -20,12 +20,12 @@ // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER @@ -831,366 +831,6 @@ // CHECK4-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK5-NEXT: ret i32 0 -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK5-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK5-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK5-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store i32* [[B3]], i32** [[TMP4]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK5-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK5-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK5-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK5-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK5-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK5-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK6-NEXT: ret i32 0 -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK6-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK6-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK6-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK6-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK6-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK6-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK6-NEXT: store i32* [[B3]], i32** [[TMP4]], align 8 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK6-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK6-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK6-NEXT: ret void -// -// -// CHECK6-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK6-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK6-NEXT: entry: -// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 -// CHECK6-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 -// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK6-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK6-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK6-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK7-NEXT: ret i32 0 -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 -// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK7-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK7-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK7-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK7-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK7-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK7-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK7-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK7-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK7-NEXT: store i32* [[B3]], i32** [[TMP4]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK7-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) -// CHECK7-NEXT: ret void -// -// -// CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK7-NEXT: entry: -// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 -// CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK7-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK7-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK7-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK7-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) -// CHECK8-NEXT: ret i32 0 -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 -// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK8-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK8-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK8-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK8-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK8-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK8-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK8-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK8-NEXT: store i32* [[TMP3]], i32** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK8-NEXT: store i32* [[B3]], i32** [[TMP4]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK8-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 -// CHECK8-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) -// CHECK8-NEXT: ret void -// -// -// CHECK8-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK8-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { -// CHECK8-NEXT: entry: -// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 -// CHECK8-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 -// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 -// CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 -// CHECK8-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 -// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 -// CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 -// CHECK8-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 -// CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 -// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 -// CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 -// CHECK8-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 -// CHECK8-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@main // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: @@ -3182,1431 +2822,4 @@ // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // -// -// CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done7: -// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK13: arraydestroy.body9: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK13: arraydestroy.done13: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK13-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK13-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done7: -// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK13: arraydestroy.body9: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK13: arraydestroy.done13: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: ret i32 [[TMP6]] -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK13-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK13-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK13-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK13-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK13-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK13-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK13-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK13-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK13-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK13-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK13-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK13-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK13-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK13-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK13-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK13-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK13-NEXT: ret void -// -// -// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK14-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done7: -// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() -// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK14: arraydestroy.body9: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK14: arraydestroy.done13: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK14-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK14-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK14-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK14-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) -// CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK14: arrayctor.loop: -// CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 -// CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 -// CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK14: arraydestroy.body: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK14: arraydestroy.done7: -// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 -// CHECK14-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK14: arraydestroy.body9: -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK14-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK14: arraydestroy.done13: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: ret i32 [[TMP6]] -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK14-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 -// CHECK14-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 8 -// CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK14-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK14-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK14-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK14-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK14-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 -// CHECK14-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK14-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 8 -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK14-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK14-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK14-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 -// CHECK14-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: [[TMP:%.*]] = alloca i32*, align 8 -// CHECK14-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK14-NEXT: store i32* [[A2]], i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 8 -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK14-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK14-NEXT: ret void -// -// -// CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK14-NEXT: entry: -// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK15-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK15-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK15-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done7: -// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK15: arraydestroy.body9: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK15: arraydestroy.done13: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: ret i32 [[TMP6]] -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK15-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK15-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK15-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK15-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK15-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK15-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK15-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK15-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK15-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK15-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK15-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK15-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK15-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK15-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK15-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK15-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK15-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK15-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK15-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK16-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 4 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() -// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK16-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK16-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 -// CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 -// CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK16-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 -// CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 -// CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) -// CHECK16-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) -// CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) -// CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) -// CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) -// CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 -// CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK16: arrayctor.loop: -// CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 -// CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR1]], align 128 -// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 -// CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 -// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* -// CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK16: arraydestroy.body: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK16: arraydestroy.done7: -// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 -// CHECK16-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] -// CHECK16: arraydestroy.body9: -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] -// CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR4]] -// CHECK16-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] -// CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] -// CHECK16: arraydestroy.done13: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: ret i32 [[TMP6]] -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK16-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 -// CHECK16-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: [[B3:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[C4:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 -// CHECK16-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 -// CHECK16-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 -// CHECK16-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 -// CHECK16-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK16-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 -// CHECK16-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK16-NEXT: store i32* [[C4]], i32** [[_TMP5]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[B3]], align 4 -// CHECK16-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 -// CHECK16-NEXT: store i32 [[DEC]], i32* [[B3]], align 4 -// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP5]], align 4 -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 -// CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 -// CHECK16-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store float 0.000000e+00, float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 -// CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: store float [[TMP0]], float* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK16-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK16-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK16-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 -// CHECK16-NEXT: [[A2:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: [[TMP:%.*]] = alloca i32*, align 4 -// CHECK16-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK16-NEXT: store i32* [[A2]], i32** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[TMP]], align 4 -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 -// CHECK16-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 -// CHECK16-NEXT: ret void -// -// -// CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK16-NEXT: entry: -// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: ret void -// +// \ No newline at end of file diff --git a/clang/test/OpenMP/vla_crash.c b/clang/test/OpenMP/vla_crash.c --- a/clang/test/OpenMP/vla_crash.c +++ b/clang/test/OpenMP/vla_crash.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" int a; @@ -130,55 +130,4 @@ // CHECK1: if.end: // CHECK1-NEXT: ret void // -// -// CHECK2-LABEL: define {{[^@]+}}@foo -// CHECK2-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[B:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: [[C:%.*]] = alloca i32***, align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32***, i32**** [[C]], align 8 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32**, i32*** [[TMP4]], i64 0 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32**, i32*** [[ARRAYIDX]], align 8 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK2-NEXT: [[TMP7:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32*, i32** [[TMP5]], i64 [[TMP7]] -// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32*, i32** [[ARRAYIDX1]], i64 0 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[ARRAYIDX2]], align 8 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* @a, align 4 -// CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM3]] -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[B]], align 8 -// CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 0, [[TMP1]] -// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i64 [[TMP12]] -// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX5]], i64 0 -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX6]], align 4 -// CHECK2-NEXT: ret void -// -// -// CHECK2-LABEL: define {{[^@]+}}@bar -// CHECK2-SAME: (i32 signext [[N:%.*]], i32* [[A:%.*]]) #[[ATTR0]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: [[P:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK2-NEXT: [[TMP2:%.*]] = bitcast i32** [[A_ADDR]] to i32* -// CHECK2-NEXT: store i32* [[TMP2]], i32** [[P]], align 8 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[P]], align 8 -// CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32** [[A_ADDR]] to i32* -// CHECK2-NEXT: [[CMP:%.*]] = icmp eq i32* [[TMP3]], [[TMP4]] -// CHECK2-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] -// CHECK2: if.then: -// CHECK2-NEXT: br label [[IF_END]] -// CHECK2: if.end: -// CHECK2-NEXT: ret void -// +// \ No newline at end of file