diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -71,6 +71,7 @@
 def : SysReg<"uscratch", 0x040>;
 def : SysReg<"uepc", 0x041>;
 def : SysReg<"ucause", 0x042>;
+let AltName = "ubadaddr" in
 def : SysReg<"utval", 0x043>;
 def : SysReg<"uip", 0x044>;
 
@@ -171,12 +172,14 @@
 def : SysReg<"sscratch", 0x140>;
 def : SysReg<"sepc", 0x141>;
 def : SysReg<"scause", 0x142>;
+let AltName = "sbadaddr" in
 def : SysReg<"stval", 0x143>;
 def : SysReg<"sip", 0x144>;
 
 //===-------------------------------------
 // Supervisor Protection and Translation
 //===-------------------------------------
+let AltName = "sptbr" in
 def : SysReg<"satp", 0x180>;
 
 //===-----------------------------
@@ -205,6 +208,7 @@
 def : SysReg<"mscratch", 0x340>;
 def : SysReg<"mepc", 0x341>;
 def : SysReg<"mcause", 0x342>;
+let AltName = "mbadaddr" in
 def : SysReg<"mtval", 0x343>;
 def : SysReg<"mip", 0x344>;
 
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -1283,3 +1283,59 @@
 csrrs t1, mhpmevent31, zero
 # uimm12
 csrrs t2, 0x33F, zero
+
+# sbadaddr
+# name
+# CHECK-INST: csrrw zero, stval, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x30,0x14]
+# CHECK-INST-ALIAS: csrw stval, zero
+# uimm12
+# CHECK-INST: csrrw zero, stval, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x30,0x14]
+# CHECK-INST-ALIAS: csrw stval, zero
+# name
+csrw sbadaddr, zero
+# uimm12
+csrrw zero, 0x143, zero
+
+# mbadaddr
+# name
+# CHECK-INST: csrrw zero, mtval, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x30,0x34]
+# CHECK-INST-ALIAS: csrw mtval, zero
+# uimm12
+# CHECK-INST: csrrw zero, mtval, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x30,0x34]
+# CHECK-INST-ALIAS: csrw mtval, zero
+# name
+csrw mbadaddr, zero
+# uimm12
+csrrw zero, 0x343, zero
+
+# ubadaddr
+# name
+# CHECK-INST: csrrw zero, utval, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
+# CHECK-INST-ALIAS: csrw utval, zero
+# uimm12
+# CHECK-INST: csrrw zero, utval, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
+# CHECK-INST-ALIAS: csrw utval, zero
+# name
+csrw ubadaddr, zero
+# uimm12
+csrrw zero, 0x043, zero
+
+# sptbr
+# name
+# CHECK-INST: csrrw zero, satp, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x00,0x18]
+# CHECK-INST-ALIAS: csrw satp, zero
+# uimm12
+# CHECK-INST: csrrw zero, satp, zero
+# CHECK-ENC: encoding: [0x73,0x10,0x00,0x18]
+# CHECK-INST-ALIAS: csrw satp, zero
+# name
+csrw sptbr, zero
+# uimm12
+csrrw zero, 0x180, zero