diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -3884,7 +3884,12 @@
   }
 
   case Intrinsic::invariant_start:
-  case Intrinsic::invariant_end:
+  case Intrinsic::invariant_end: {
+    SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
+                                 CI->arg_operands().end());
+    NewCall = Builder.CreateCall(NewFn, Args);
+    break;
+  }
   case Intrinsic::masked_load:
   case Intrinsic::masked_store:
   case Intrinsic::masked_gather:
@@ -3892,6 +3897,7 @@
     SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
                                  CI->arg_operands().end());
     NewCall = Builder.CreateCall(NewFn, Args);
+    NewCall->copyMetadata(*CI);
     break;
   }
 
diff --git a/llvm/test/Bitcode/upgrade-masked-keep-tbaa.ll b/llvm/test/Bitcode/upgrade-masked-keep-tbaa.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Bitcode/upgrade-masked-keep-tbaa.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S < %s | FileCheck %s
+
+define <4 x i32> @load(<4 x i32>* %a0) {
+; CHECK-LABEL: @load(
+; CHECK-NEXT:  b0:
+; CHECK-NEXT:    [[V0:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[A0:%.*]], i32 128, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT:    ret <4 x i32> [[V0]]
+;
+b0:
+  %v0 = call <4 x i32> @llvm.masked.load(<4 x i32>* %a0, i32 128, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !tbaa !0
+  ret <4 x i32> %v0
+}
+
+define void @store(<4 x i32> %a0, <4 x i32>* %a1) {
+; CHECK-LABEL: @store(
+; CHECK-NEXT:  b0:
+; CHECK-NEXT:    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[A0:%.*]], <4 x i32>* [[A1:%.*]], i32 128, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !tbaa [[TBAA0]]
+; CHECK-NEXT:    ret void
+;
+b0:
+  call void @llvm.masked.store(<4 x i32> %a0, <4 x i32>* %a1, i32 128, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !tbaa !0
+  ret void
+}
+
+define <4 x i32> @gather(<4 x i32*> %a0) {
+; CHECK-LABEL: @gather(
+; CHECK-NEXT:    [[V0:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !tbaa [[TBAA0]]
+; CHECK-NEXT:    ret <4 x i32> [[V0]]
+;
+  %v0 = call <4 x i32> @llvm.masked.gather(<4 x i32*> %a0, i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !tbaa !0
+  ret <4 x i32> %v0
+}
+
+define void @scatter(<4 x i32> %a0, <4 x i32*> %a1) {
+; CHECK-LABEL: @scatter(
+; CHECK-NEXT:  b0:
+; CHECK-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[A0:%.*]], <4 x i32*> [[A1:%.*]], i32 128, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !tbaa [[TBAA0]]
+; CHECK-NEXT:    ret void
+;
+b0:
+  call void @llvm.masked.scatter(<4 x i32> %a0, <4 x i32*> %a1, i32 128, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !tbaa !0
+  ret void
+}
+
+define <4 x i32> @expandload(i32* %a0) {
+; CHECK-LABEL: @expandload(
+; CHECK-NEXT:  b0:
+; CHECK-NEXT:    [[V0:%.*]] = call <4 x i32> @llvm.masked.expandload.v4i32(i32* [[A0:%.*]], <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !tbaa [[TBAA0]]
+; CHECK-NEXT:    ret <4 x i32> [[V0]]
+;
+b0:
+  %v0 = call <4 x i32> @llvm.masked.expandload(i32* %a0, <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !tbaa !0
+  ret <4 x i32> %v0
+}
+
+define void @compressstore(<4 x i32> %a0, i32* %a1) {
+; CHECK-LABEL: @compressstore(
+; CHECK-NEXT:  b0:
+; CHECK-NEXT:    call void @llvm.masked.compressstore.v4i32(<4 x i32> [[A0:%.*]], i32* [[A1:%.*]], <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !tbaa [[TBAA0]]
+; CHECK-NEXT:    ret void
+;
+b0:
+  call void @llvm.masked.compressstore(<4 x i32> %a0, i32* %a1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !tbaa !0
+  ret void
+}
+
+declare <4 x i32> @llvm.masked.load(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
+declare void @llvm.masked.store(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
+declare <4 x i32> @llvm.masked.gather(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
+declare void @llvm.masked.scatter(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
+declare <4 x i32> @llvm.masked.expandload(i32*, <4 x i1>, <4 x i32>)
+declare void @llvm.masked.compressstore(<4 x i32>, i32*, <4 x i1>)
+
+!0 = !{!1, !1, i64 0}
+!1 = !{!"omnipotent char", !2, i64 0}
+!2 = !{!"Simple C/C++ TBAA"}