diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5384,8 +5384,7 @@ AArch64FunctionInfo *FuncInfo = MF.getInfo(); bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; bool IsSibCall = false; - bool IsWin64 = - Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv()); + bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CallConv); // Check callee args/returns for SVE registers and set calling convention // accordingly. @@ -5438,7 +5437,7 @@ bool UseVarArgCC = !Outs[i].IsFixed; // On Windows, the fixed arguments in a vararg call are passed in GPRs // too, so use the vararg CC to force them to integer registers. - if (IsWin64) + if (IsCalleeWin64) UseVarArgCC = true; CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, UseVarArgCC); bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -164,17 +164,12 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn, - CCAssignFn *AssignFnVarArg, bool IsVarArg, - bool IsTailCall = false, int FPDiff = 0) + CCAssignFn *AssignFnVarArg, bool IsTailCall = false, + int FPDiff = 0) : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff), - StackSize(0), SPReg(0) { - MachineFunction &MF = MIRBuilder.getMF(); - const auto &Subtarget = MF.getSubtarget(); - bool IsWin = - Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv()); - UseVarArgsCCForFixed = IsVarArg && IsWin; - } + StackSize(0), SPReg(0), + Subtarget(MIRBuilder.getMF().getSubtarget()) {} Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, @@ -246,6 +241,8 @@ ISD::ArgFlagsTy Flags, CCState &State) override { bool Res; + bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv()); + bool UseVarArgsCCForFixed = IsCalleeWin && State.isVarArg(); if (Info.IsFixed && !UseVarArgsCCForFixed) Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State); else @@ -258,7 +255,6 @@ MachineInstrBuilder MIB; CCAssignFn *AssignFnVarArg; bool IsTailCall; - bool UseVarArgsCCForFixed; /// For tail calls, the byte offset of the call's argument area from the /// callee's. Unused elsewhere. @@ -267,6 +263,8 @@ // Cache the SP register vreg if we need it more than once in this call site. Register SPReg; + + const AArch64Subtarget &Subtarget; }; } // namespace @@ -383,8 +381,7 @@ splitToValueTypes(CurArgInfo, SplitArgs, DL, CC); } - OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn, - F.isVarArg()); + OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn); Success = handleAssignments(MIRBuilder, SplitArgs, Handler, CC, F.isVarArg()); } @@ -888,7 +885,7 @@ // Do the actual argument marshalling. OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, - AssignFnVarArg, Info.IsVarArg, true, FPDiff); + AssignFnVarArg, true, FPDiff); if (!handleAssignments(MIRBuilder, OutArgs, Handler, CalleeCC, Info.IsVarArg)) return false; @@ -1000,7 +997,7 @@ // Do the actual argument marshalling. OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, - AssignFnVarArg, Info.IsVarArg, false); + AssignFnVarArg, false); if (!handleAssignments(MIRBuilder, OutArgs, Handler, Info.CallConv, Info.IsVarArg)) return false; diff --git a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll b/llvm/test/CodeGen/AArch64/win64_vararg_float.ll --- a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll +++ b/llvm/test/CodeGen/AArch64/win64_vararg_float.ll @@ -101,8 +101,22 @@ ; GISEL: fmov d0, #3.00000000 ; CHECK: mov w3, #4 ; CHECK: b other_d_va_fn - tail call void (double, i32, ...) @other_d_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4) #4 + tail call void (double, i32, ...) @other_d_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4) ret void } -declare dso_local void @other_d_va_fn(double, i32, ...) +declare void @other_d_va_fn(double, i32, ...) + +define void @call_d_non_va() nounwind { +entry: +; CHECK-LABEL: call_d_non_va: +; CHECK-DAG: fmov d0, #1.00000000 +; CHECK-DAG: fmov d1, #3.00000000 +; CHECK-DAG: mov w0, #2 +; CHECK-DAG: mov w1, #4 +; CHECK: b other_d_non_va_fn + tail call void (double, i32, double, i32) @other_d_non_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4) + ret void +} + +declare void @other_d_non_va_fn(double, i32, double, i32) diff --git a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll b/llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll copy from llvm/test/CodeGen/AArch64/win64_vararg_float.ll copy to llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll --- a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll +++ b/llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DAGISEL -; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs -O0 -fast-isel | FileCheck %s --check-prefixes=CHECK,O0 -; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs -O0 -global-isel | FileCheck %s --check-prefixes=CHECK,O0 +; RUN: llc < %s -mtriple=aarch64-linux -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DAGISEL +; RUN: llc < %s -mtriple=aarch64-linux -verify-machineinstrs -O0 -fast-isel | FileCheck %s --check-prefixes=CHECK,O0 +; RUN: llc < %s -mtriple=aarch64-linux -verify-machineinstrs -O0 -global-isel | FileCheck %s --check-prefixes=CHECK,O0 -define void @float_va_fn(float %a, i32 %b, ...) nounwind { +define win64cc void @float_va_fn(float %a, i32 %b, ...) nounwind { entry: ; CHECK-LABEL: float_va_fn: ; O0: str x7, [sp, #72] @@ -15,10 +15,10 @@ ; O0: add x8, sp, #32 ; O0: str x8, [sp, #8] ; O0: ldr x0, [sp, #8] -; DAGISEL: add x0, sp, #16 -; DAGISEL: stp x2, x3, [sp, #16] -; DAGISEL: stp x4, x5, [sp, #32] -; DAGISEL: stp x6, x7, [sp, #48] +; DAGISEL: add x0, sp, #32 +; DAGISEL: stp x2, x3, [sp, #32] +; DAGISEL: stp x4, x5, [sp, #48] +; DAGISEL: stp x6, x7, [sp, #64] ; CHECK: bl f_va_list %ap = alloca i8*, align 8 %0 = bitcast i8** %ap to i8* @@ -37,7 +37,7 @@ declare void @llvm.va_end(i8*) declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) -define void @double_va_fn(double %a, i32 %b, ...) nounwind { +define win64cc void @double_va_fn(double %a, i32 %b, ...) nounwind { entry: ; CHECK-LABEL: double_va_fn: ; O0: str x7, [sp, #72] @@ -50,10 +50,10 @@ ; O0: add x8, sp, #32 ; O0: str x8, [sp, #8] ; O0: ldr x0, [sp, #8] -; DAGISEL: add x0, sp, #16 -; DAGISEL: stp x2, x3, [sp, #16] -; DAGISEL: stp x4, x5, [sp, #32] -; DAGISEL: stp x6, x7, [sp, #48] +; DAGISEL: add x0, sp, #32 +; DAGISEL: stp x2, x3, [sp, #32] +; DAGISEL: stp x4, x5, [sp, #48] +; DAGISEL: stp x6, x7, [sp, #64] ; CHECK: bl d_va_list %ap = alloca i8*, align 8 %0 = bitcast i8** %ap to i8* @@ -81,12 +81,12 @@ ; GISEL: fmov d0, #3.00000000 ; GISEL: fmov x2, d0 ; CHECK: mov w3, #4 -; CHECK: b other_f_va_fn - tail call void (float, i32, ...) @other_f_va_fn(float 1.000000e+00, i32 2, double 3.000000e+00, i32 4) +; CHECK: bl other_f_va_fn + tail call win64cc void (float, i32, ...) @other_f_va_fn(float 1.000000e+00, i32 2, double 3.000000e+00, i32 4) ret void } -declare void @other_f_va_fn(float, i32, ...) +declare win64cc void @other_f_va_fn(float, i32, ...) define void @call_d_va() nounwind { entry: @@ -100,9 +100,23 @@ ; FASTISEL: mov x2, #4613937818241073152 ; GISEL: fmov d0, #3.00000000 ; CHECK: mov w3, #4 -; CHECK: b other_d_va_fn - tail call void (double, i32, ...) @other_d_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4) #4 +; CHECK: bl other_d_va_fn + tail call win64cc void (double, i32, ...) @other_d_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4) ret void } -declare dso_local void @other_d_va_fn(double, i32, ...) +declare win64cc void @other_d_va_fn(double, i32, ...) + +define void @call_d_non_va() nounwind { +entry: +; CHECK-LABEL: call_d_non_va: +; CHECK-DAG: fmov d0, #1.00000000 +; CHECK-DAG: fmov d1, #3.00000000 +; CHECK-DAG: mov w0, #2 +; CHECK-DAG: mov w1, #4 +; CHECK: bl other_d_non_va_fn + tail call win64cc void (double, i32, double, i32) @other_d_non_va_fn(double 1.000000e+00, i32 2, double 3.000000e+00, i32 4) + ret void +} + +declare win64cc void @other_d_non_va_fn(double, i32, double, i32)