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[AArch64][SVE] Allow generation of MOVPRFX for intrinsic nodes

Authored by bsmith on Apr 20 2021, 7:48 AM.



This patch does several things to achieve this:

  • All patterns for destructive instructions with psuedos have been moved out of the main instruction multiclass and into the pseudo instruction multiclasses
  • The pseudo instruction mutliclasses now contain patterns for both the ISD nodes and the intrinsic nodes.
  • The set of pseudo instructions has been expanded in some cases to allow for a 'reverse' intrinsic (e.g. subr) to be reversed (e.g. into a sub), and to allow matching intrinsic nodes that don't have an ISD node equivalent.

As part of this patch missing patterns for the immediate versions of
UQSHL and SQSHL have been added. As well as support for DestructiveBinary
in AArch64ExpandPseudo::expand_DestructiveOp, which allows for expanding
pseudos where the operands cannot be swapped, (e.g. fscale, more will

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Event Timeline

bsmith created this revision.Apr 20 2021, 7:48 AM
bsmith requested review of this revision.Apr 20 2021, 7:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 20 2021, 7:48 AM
Matt added a subscriber: Matt.Apr 21 2021, 5:42 AM
paulwalker-arm added inline comments.Apr 21 2021, 5:56 AM

Are you sure this is safe? The intrinsics have strict requirement regarding how inactive lanes are handled that I believe these patterns will not honour.

bsmith abandoned this revision.Apr 21 2021, 10:05 AM

The fact that the DestructiveBinary case in this needs to insert extra MOV's to make up for what is essentially poor register allocation choices, is less than ideal. I'm abandoning this in favour of a proper solution at a later date that will depend on D88595.


You are correct, this is being overzealous in what it covers.