diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1924,8 +1924,9 @@ } bool AMDGPUOperand::isBoolReg() const { - return (AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || - (AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()); + auto FB = AsmParser->getFeatureBits(); + return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || + (FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32())); } uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_err.s --- a/llvm/test/MC/AMDGPU/gfx10_asm_err.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_err.s @@ -273,3 +273,27 @@ v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] // GFX6-7: error: dpp variant of this instruction is not supported // GFX8-9: error: not a valid operand + +//===----------------------------------------------------------------------===// +// VOP2 E64. +//===----------------------------------------------------------------------===// + +v_add_co_ci_u32 v5, 0, v1, v2, vcc +// GFX6-7: error: instruction not supported on this GPU +// GFX8-9: error: instruction not supported on this GPU +// GFX10: error: invalid operand for instruction + +v_add_co_ci_u32 v5, vcc, v1, v2, 0 +// GFX6-7: error: instruction not supported on this GPU +// GFX8-9: error: instruction not supported on this GPU +// GFX10: error: invalid operand for instruction + +v_add_co_ci_u32 v5, 0, v1, v2, vcc_lo +// GFX6-7: error: instruction not supported on this GPU +// GFX8-9: error: instruction not supported on this GPU +// GFX10: error: invalid operand for instruction + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, 0 +// GFX6-7: error: instruction not supported on this GPU +// GFX8-9: error: instruction not supported on this GPU +// GFX10: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/vop2-err.s b/llvm/test/MC/AMDGPU/vop2-err.s --- a/llvm/test/MC/AMDGPU/vop2-err.s +++ b/llvm/test/MC/AMDGPU/vop2-err.s @@ -56,9 +56,21 @@ v_addc_u32_e32 v1, -1, v2, v3, s0 // CHECK: error: invalid operand for instruction +v_addc_u32 v1, -1, v2, v3, vcc +// CHECK: error: invalid operand for instruction + +v_addc_u32 v1, vcc, v2, v3, 0 +// CHECK: error: invalid operand for instruction + v_addc_u32_e64 v1, s[0:1], v2, v3, 123 // CHECK: error: invalid operand for instruction +v_addc_u32_e64 v1, 0, v2, v3, s[0:1] +// CHECK: error: invalid operand for instruction + +v_addc_u32_e64 v1, s[0:1], v2, v3, 0 +// CHECK: error: invalid operand for instruction + v_addc_u32 v1, s[0:1], v2, v3, 123 // CHECK: error: invalid operand for instruction