diff --git a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
@@ -0,0 +1,106 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v -run-pass=prologepilog -o - \
+# RUN:     -verify-machineinstrs %s | FileCheck %s
+--- |
+  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+  target triple = "riscv64"
+
+  define void @spillslot() {
+    ret void
+  }
+
+...
+---
+name:            spillslot
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x12', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    128
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: default, offset: 0, size: 2048, alignment: 128,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: 0, size: 400, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $x12
+
+    dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
+    renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 16, implicit $vl, implicit $vtype
+    PseudoVSPILL_M1 killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    renamable $x1 = ADDI $x0, 255
+    renamable $x5 = nuw ADDI %stack.0, 256
+    renamable $x6 = ADDI %stack.0, 384
+    renamable $x7 = nuw ADDI %stack.0, 512
+    renamable $x10 = ADDI $x0, 128
+    renamable $x12 = nuw ADDI %stack.0, 128
+    renamable $x14 = COPY $x0
+    renamable $x17 = nuw ADDI %stack.0, 128
+    renamable $x18 = ADDI %stack.0, 1152
+    renamable $x19 = ADDI %stack.0, 1280
+    renamable $x20 = ADDI %stack.0, 1408
+    renamable $x21 = ADDI %stack.0, 1536
+    renamable $x22 = ADDI %stack.0, 1664
+    renamable $x23 = ADDI %stack.0, 1792
+    renamable $x24 = ADDI %stack.0, 1920
+    renamable $x25 = ADDI %stack.0, 0
+    renamable $x26 = ADDI %stack.0, 0
+    renamable $x27 = ADDI $x0, 2
+    renamable $x28 = ADDI %stack.0, 640
+    renamable $x29 = ADDI %stack.0, 768
+    renamable $x30 = ADDI %stack.0, 896
+    renamable $x31 = nuw ADDI %stack.0, 1024
+    renamable $x15 = ADDIW renamable $x14, 0
+    renamable $x11 = ANDI renamable $x15, 255
+    renamable $x13 = SLLI renamable $x11, 3
+    renamable $x13 = ADD renamable $x26, killed renamable $x13
+    renamable $x13 = LD killed renamable $x13, 0 :: (load 8)
+    renamable $x9 = SRAI renamable $x13, 63
+    renamable $x9 = SRLI killed renamable $x9, 62
+    renamable $x9 = ADD renamable $x13, killed renamable $x9
+    renamable $x9 = ANDI killed renamable $x9, -4
+    renamable $x16 = SUB killed renamable $x13, killed renamable $x9
+    dead renamable $x13 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
+    renamable $x13 = nsw ADDI renamable $x16, -2
+    renamable $v0 = PseudoVRELOAD_M1 %stack.1 :: (load unknown-size from %stack.1, align 8)
+    renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 8, implicit $vl, implicit $vtype
+    renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 8, implicit $vl, implicit $vtype
+    BLT killed renamable $x16, renamable $x27, %bb.2
+
+  bb.1:
+    successors: %bb.2
+    liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
+
+    renamable $x9 = COPY killed renamable $x13
+    PseudoBR %bb.2
+
+  bb.2:
+    PseudoRET
+...