diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -718,6 +718,8 @@
   getActionDefinitionsBuilder({G_SBFX, G_UBFX})
       .customFor({{s32, s32}, {s64, s64}});
 
+  getActionDefinitionsBuilder(G_CTPOP).legalFor({{v8s8, v8s8}, {v16s8, v16s8}});
+
   computeTables();
   verify(*ST.getInstrInfo());
 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
@@ -0,0 +1,39 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
+...
+---
+name:            v8s8_legal
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: v8s8_legal
+    ; CHECK: liveins: $d0
+    ; CHECK: %copy:_(<8 x s8>) = COPY $d0
+    ; CHECK: %ctpop:_(<8 x s8>) = G_CTPOP %copy(<8 x s8>)
+    ; CHECK: $d0 = COPY %ctpop(<8 x s8>)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %copy:_(<8 x s8>) = COPY $d0
+    %ctpop:_(<8 x s8>) = G_CTPOP %copy(<8 x s8>)
+    $d0 = COPY %ctpop(<8 x s8>)
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            v16s8_legal
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v16s8_legal
+    ; CHECK: liveins: $q0
+    ; CHECK: %copy:_(<16 x s8>) = COPY $q0
+    ; CHECK: %ctpop:_(<16 x s8>) = G_CTPOP %copy(<16 x s8>)
+    ; CHECK: $q0 = COPY %ctpop(<16 x s8>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %copy:_(<16 x s8>) = COPY $q0
+    %ctpop:_(<16 x s8>) = G_CTPOP %copy(<16 x s8>)
+    $q0 = COPY %ctpop(<16 x s8>)
+    RET_ReallyLR implicit $q0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -551,8 +551,8 @@
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_CTPOP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 # DEBUG-NEXT: G_BSWAP (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=instruction-select %s -o - | FileCheck %s
+
+...
+---
+name:            CNTv8i8
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: CNTv8i8
+    ; CHECK: liveins: $d0
+    ; CHECK: %copy:fpr64 = COPY $d0
+    ; CHECK: %ctpop:fpr64 = CNTv8i8 %copy
+    ; CHECK: $d0 = COPY %ctpop
+    ; CHECK: RET_ReallyLR implicit $d0
+    %copy:fpr(<8 x s8>) = COPY $d0
+    %ctpop:fpr(<8 x s8>) = G_CTPOP %copy(<8 x s8>)
+    $d0 = COPY %ctpop(<8 x s8>)
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            CNTv16i8
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: CNTv16i8
+    ; CHECK: liveins: $q0
+    ; CHECK: %copy:fpr128 = COPY $q0
+    ; CHECK: %ctpop:fpr128 = CNTv16i8 %copy
+    ; CHECK: $q0 = COPY %ctpop
+    ; CHECK: RET_ReallyLR implicit $q0
+    %copy:fpr(<16 x s8>) = COPY $q0
+    %ctpop:fpr(<16 x s8>) = G_CTPOP %copy(<16 x s8>)
+    $q0 = COPY %ctpop(<16 x s8>)
+    RET_ReallyLR implicit $q0
+
+...