diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -38,6 +38,9 @@ def SDT_RISCVIntUnaryOpW : SDTypeProfile<1, 1, [ SDTCisSameAs<0, 1>, SDTCisVT<0, i64> ]>; +def SDT_RISCVIntBinOp : SDTypeProfile<1, 2, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, XLenVT> +]>; def SDT_RISCVIntBinOpW : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64> ]>; @@ -860,9 +863,9 @@ /// Generic pattern classes class PatGpr - : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>; + : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1))), (Inst GPR:$rs1)>; class PatGprGpr - : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; + : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2)>; class PatGprImm : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)), @@ -929,7 +932,7 @@ (operator node:$val, (XLenVT (shiftMaskXLen node:$count)))>; class shiftopw : PatFrag<(ops node:$val, node:$count), - (operator node:$val, (i64 (shiftMask32 node:$count)))>; + (operator node:$val, (i64 (shiftMask32 (i64 node:$count))))>; def : PatGprGpr, SLL>; def : PatGprGpr, SRL>; @@ -960,20 +963,28 @@ // Define pattern expansions for setcc operations that aren't directly // handled by a RISC-V instruction. -def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>; -def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; -def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12), +def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), 0)), (SLTIU GPR:$rs1, 1)>; +def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), GPR:$rs2)), + (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), simm12_plus1:$imm12)), (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>; -def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>; -def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>; -def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12), - (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>; -def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>; -def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; -def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; -def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>; -def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; -def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; +def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), 0)), (SLTU (XLenVT X0), GPR:$rs1)>; +def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), GPR:$rs2)), + (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>; +def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), simm12_plus1:$imm12)), + (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>; +def : Pat<(XLenVT (setugt (XLenVT GPR:$rs1), GPR:$rs2)), + (SLTU GPR:$rs2, GPR:$rs1)>; +def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(XLenVT (setule (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; +def : Pat<(XLenVT (setgt (XLenVT GPR:$rs1), GPR:$rs2)), + (SLT GPR:$rs2, GPR:$rs1)>; +def : Pat<(XLenVT (setge (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(XLenVT (setle (XLenVT GPR:$rs1), GPR:$rs2)), + (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; def IntCCtoRISCVCC : SDNodeXForm(N->getOperand(2))->get(); @@ -989,21 +1000,22 @@ IntCCtoRISCVCC>; let usesCustomInserter = 1 in -class SelectCC_rrirr +class SelectCC_rrirr : Pseudo<(outs valty:$dst), (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm, valty:$truev, valty:$falsev), [(set valty:$dst, - (riscv_selectcc_frag:$imm cmpty:$lhs, cmpty:$rhs, cond, - valty:$truev, valty:$falsev))]>; + (riscv_selectcc_frag:$imm (cmpvt cmpty:$lhs), cmpty:$rhs, cond, + (valvt valty:$truev), valty:$falsev))]>; -def Select_GPR_Using_CC_GPR : SelectCC_rrirr; +def Select_GPR_Using_CC_GPR : SelectCC_rrirr; /// Branches and jumps // Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction. class BccPat - : Pat<(riscv_brcc GPR:$rs1, GPR:$rs2, Cond, bb:$imm12), + : Pat<(riscv_brcc (XLenVT GPR:$rs1), GPR:$rs2, Cond, bb:$imm12), (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>; def : BccPat; @@ -1050,9 +1062,9 @@ def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>; def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; -def : Pat<(riscv_uret_flag), (URET X0, X0)>; -def : Pat<(riscv_sret_flag), (SRET X0, X0)>; -def : Pat<(riscv_mret_flag), (MRET X0, X0)>; +def : Pat<(riscv_uret_flag), (URET (XLenVT X0), (XLenVT X0))>; +def : Pat<(riscv_sret_flag), (SRET (XLenVT X0), (XLenVT X0))>; +def : Pat<(riscv_mret_flag), (MRET (XLenVT X0), (XLenVT X0))>; let isCall = 1, Defs = [X1] in def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1), @@ -1189,7 +1201,7 @@ class ReadSysReg Regs> : Pseudo<(outs GPR:$rd), (ins), - [(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>, + [(set (XLenVT GPR:$rd), (riscv_read_csr (XLenVT SR.Encoding)))]>, PseudoInstExpansion<(CSRRS GPR:$rd, SR.Encoding, X0)> { let hasSideEffects = 0; let Uses = Regs; @@ -1197,7 +1209,7 @@ class WriteSysReg Regs> : Pseudo<(outs), (ins GPR:$val), - [(riscv_write_csr (XLenVT SR.Encoding), GPR:$val)]>, + [(riscv_write_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))]>, PseudoInstExpansion<(CSRRW X0, SR.Encoding, GPR:$val)> { let hasSideEffects = 0; let Defs = Regs; @@ -1306,7 +1318,7 @@ /// readcyclecounter // On RV64, we can directly read the 64-bit "cycle" CSR. let Predicates = [IsRV64] in -def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, X0)>; +def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, (XLenVT X0))>; // On RV32, ReadCycleWide will be expanded to the suggested loop reading both // halves of the 64-bit "cycle" CSR. let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in @@ -1325,13 +1337,13 @@ def : Pat<(debugtrap), (EBREAK)>; /// Simple optimization -def : Pat<(add GPR:$rs1, (AddiPair:$rs2)), +def : Pat<(add (XLenVT GPR:$rs1), (AddiPair:$rs2)), (ADDI (ADDI GPR:$rs1, (AddiPairImmB AddiPair:$rs2)), (AddiPairImmA GPR:$rs2))>; let Predicates = [IsRV64] in { // Select W instructions if only the lower 32-bits of the result are used. -def : Pat<(overflowingbinopw GPR:$rs1, (AddiPair:$rs2)), +def : Pat<(overflowingbinopw (XLenVT GPR:$rs1), (AddiPair:$rs2)), (ADDIW (ADDIW GPR:$rs1, (AddiPairImmB AddiPair:$rs2)), (AddiPairImmA AddiPair:$rs2))>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -167,16 +167,16 @@ defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">; defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">; -def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr), - (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>; -def : Pat<(atomic_load_sub_32_acquire GPR:$addr, GPR:$incr), - (AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>; -def : Pat<(atomic_load_sub_32_release GPR:$addr, GPR:$incr), - (AMOADD_W_RL GPR:$addr, (SUB X0, GPR:$incr))>; -def : Pat<(atomic_load_sub_32_acq_rel GPR:$addr, GPR:$incr), - (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>; -def : Pat<(atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr), - (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>; +def : Pat<(XLenVT (atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr)), + (AMOADD_W GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; +def : Pat<(XLenVT (atomic_load_sub_32_acquire GPR:$addr, GPR:$incr)), + (AMOADD_W_AQ GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; +def : Pat<(XLenVT (atomic_load_sub_32_release GPR:$addr, GPR:$incr)), + (AMOADD_W_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; +def : Pat<(XLenVT (atomic_load_sub_32_acq_rel GPR:$addr, GPR:$incr)), + (AMOADD_W_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; +def : Pat<(XLenVT (atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr)), + (AMOADD_W_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; /// Pseudo AMOs @@ -191,15 +191,15 @@ def PseudoAtomicLoadNand32 : PseudoAMO; // Ordering constants must be kept in sync with the AtomicOrdering enum in // AtomicOrdering.h. -def : Pat<(atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr), +def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)), (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>; -def : Pat<(atomic_load_nand_32_acquire GPR:$addr, GPR:$incr), +def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)), (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>; -def : Pat<(atomic_load_nand_32_release GPR:$addr, GPR:$incr), +def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)), (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>; -def : Pat<(atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr), +def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)), (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>; -def : Pat<(atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr), +def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)), (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>; class PseudoMaskedAMO @@ -281,15 +281,15 @@ // Ordering constants must be kept in sync with the AtomicOrdering enum in // AtomicOrdering.h. multiclass PseudoCmpXchgPat { - def : Pat<(!cast(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new), + def : Pat<(XLenVT (!cast(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new)), (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 2)>; - def : Pat<(!cast(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new), + def : Pat<(XLenVT (!cast(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new)), (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 4)>; - def : Pat<(!cast(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new), + def : Pat<(XLenVT (!cast(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new)), (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 5)>; - def : Pat<(!cast(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new), + def : Pat<(XLenVT (!cast(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new)), (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 6)>; - def : Pat<(!cast(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new), + def : Pat<(XLenVT (!cast(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new)), (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>; } @@ -335,15 +335,15 @@ /// 64-bit AMOs def : Pat<(i64 (atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr)), - (AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>; + (AMOADD_D GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; def : Pat<(i64 (atomic_load_sub_64_acquire GPR:$addr, GPR:$incr)), - (AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>; + (AMOADD_D_AQ GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; def : Pat<(i64 (atomic_load_sub_64_release GPR:$addr, GPR:$incr)), - (AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>; + (AMOADD_D_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; def : Pat<(i64 (atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr)), - (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>; + (AMOADD_D_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; def : Pat<(i64 (atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr)), - (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>; + (AMOADD_D_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>; /// 64-bit pseudo AMOs diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -25,9 +25,9 @@ def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>; def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>; def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>; -def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>; +def riscv_grev : SDNode<"RISCVISD::GREV", SDT_RISCVIntBinOp>; def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>; -def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>; +def riscv_gorc : SDNode<"RISCVISD::GORC", SDT_RISCVIntBinOp>; def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>; def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>; def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>; @@ -815,9 +815,9 @@ //===----------------------------------------------------------------------===// let Predicates = [HasStdExtZbbOrZbp] in { -def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>; -def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>; -def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>; +def : Pat<(XLenVT (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>; +def : Pat<(XLenVT (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>; +def : Pat<(XLenVT (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbbOrZbp] let Predicates = [HasStdExtZbbOrZbp] in { @@ -826,18 +826,18 @@ } // Predicates = [HasStdExtZbbOrZbp] let Predicates = [HasStdExtZbs] in { -def : Pat<(and (not (shiftop 1, GPR:$rs2)), GPR:$rs1), +def : Pat<(XLenVT (and (not (shiftop 1, (XLenVT GPR:$rs2))), GPR:$rs1)), (BCLR GPR:$rs1, GPR:$rs2)>; -def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>; -def : Pat<(or (shiftop 1, GPR:$rs2), GPR:$rs1), +def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)), (BCLR GPR:$rs1, GPR:$rs2)>; +def : Pat<(XLenVT (or (shiftop 1, (XLenVT GPR:$rs2)), GPR:$rs1)), (BSET GPR:$rs1, GPR:$rs2)>; -def : Pat<(xor (shiftop 1, GPR:$rs2), GPR:$rs1), +def : Pat<(XLenVT (xor (shiftop 1, (XLenVT GPR:$rs2)), GPR:$rs1)), (BINV GPR:$rs1, GPR:$rs2)>; -def : Pat<(and (shiftop GPR:$rs1, GPR:$rs2), 1), +def : Pat<(XLenVT (and (shiftop GPR:$rs1, (XLenVT GPR:$rs2)), 1)), (BEXT GPR:$rs1, GPR:$rs2)>; -def : Pat<(shiftop 1, GPR:$rs2), - (BSET X0, GPR:$rs2)>; +def : Pat<(XLenVT (shiftop 1, (XLenVT GPR:$rs2))), + (BSET (XLenVT X0), GPR:$rs2)>; def : Pat<(and GPR:$rs1, BCLRMask:$mask), (BCLRI GPR:$rs1, BCLRMask:$mask)>; @@ -849,22 +849,22 @@ def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)), (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>; -def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i), +def : Pat<(or (XLenVT GPR:$r), BSETINVTwoBitsMask:$i), (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)), (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>; -def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i), +def : Pat<(xor (XLenVT GPR:$r), BSETINVTwoBitsMask:$i), (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)), (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>; -def : Pat<(or GPR:$r, BSETINVORIMask:$i), +def : Pat<(or (XLenVT GPR:$r), BSETINVORIMask:$i), (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)), (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>; -def : Pat<(xor GPR:$r, BSETINVORIMask:$i), +def : Pat<(xor (XLenVT GPR:$r), BSETINVORIMask:$i), (BINVI (XORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)), (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>; -def : Pat<(and GPR:$r, BCLRITwoBitsMask:$i), +def : Pat<(and (XLenVT GPR:$r), BCLRITwoBitsMask:$i), (BCLRI (BCLRI GPR:$r, (BCLRITwoBitsMaskLow BCLRITwoBitsMask:$i)), (BCLRITwoBitsMaskHigh BCLRITwoBitsMask:$i))>; -def : Pat<(and GPR:$r, BCLRIANDIMask:$i), +def : Pat<(and (XLenVT GPR:$r), BCLRIANDIMask:$i), (BCLRI (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i)), (BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>; } @@ -873,7 +873,7 @@ // implemented with rori by negating the immediate. let Predicates = [HasStdExtZbbOrZbp] in { def : PatGprImm; -def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt), +def : Pat<(XLenVT (rotl GPR:$rs1, uimmlog2xlen:$shamt)), (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>; // We treat orc.b as a separate instruction, so match it directly. We also @@ -910,30 +910,30 @@ } // Predicates = [HasStdExtZbp, IsRV64] let Predicates = [HasStdExtZbt] in { -def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), +def : Pat<(XLenVT (or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1))), (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3), +def : Pat<(XLenVT (select (XLenVT (setne (XLenVT GPR:$rs2), 0)), GPR:$rs1, GPR:$rs3)), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (seteq (XLenVT GPR:$rs2), 0)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3), +def : Pat<(XLenVT (select (XLenVT (setne (XLenVT GPR:$x), simm12_plus1:$y)), GPR:$rs1, GPR:$rs3)), (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; -def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (seteq (XLenVT GPR:$x), simm12_plus1:$y)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; -def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3), +def : Pat<(XLenVT (select (XLenVT (setne (XLenVT GPR:$x), GPR:$y)), GPR:$rs1, GPR:$rs3)), (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>; -def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (seteq (XLenVT GPR:$x), GPR:$y)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>; -def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (setuge (XLenVT GPR:$x), GPR:$y)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>; -def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (setule (XLenVT GPR:$y), GPR:$x)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>; -def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (setge (XLenVT GPR:$x), GPR:$y)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>; -def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1), +def : Pat<(XLenVT (select (XLenVT (setle (XLenVT GPR:$y), GPR:$x)), GPR:$rs3, GPR:$rs1)), (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>; -def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3), +def : Pat<(XLenVT (select (XLenVT GPR:$rs2), GPR:$rs1, GPR:$rs3)), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; } // Predicates = [HasStdExtZbt] @@ -942,16 +942,16 @@ // shift of zero, fshr will return its second operand. fsl and fsr both return // $rs1 so the patterns need to have different operand orders. let Predicates = [HasStdExtZbt] in { -def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2), +def : Pat<(XLenVT (riscv_fsl GPR:$rs1, GPR:$rs3, (XLenVT GPR:$rs2))), (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(riscv_fsr GPR:$rs3, GPR:$rs1, GPR:$rs2), +def : Pat<(XLenVT (riscv_fsr GPR:$rs3, GPR:$rs1, (XLenVT GPR:$rs2))), (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), +def : Pat<(XLenVT (fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt)), (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>; // We can use FSRI for fshl by immediate if we subtract the immediate from // XLen and swap the operands. -def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), +def : Pat<(XLenVT (fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt)), (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>; } // Predicates = [HasStdExtZbt] @@ -995,7 +995,7 @@ (PACKU GPR:$rs1, GPR:$rs2)>; } let Predicates = [HasStdExtZbp] in -def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF), +def : Pat<(or (and (shl (XLenVT GPR:$rs2), (XLenVT 8)), 0xFFFF), (and GPR:$rs1, 0x00FF)), (PACKH GPR:$rs1, GPR:$rs2)>; @@ -1037,20 +1037,20 @@ def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2), (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>; -def : Pat<(add GPR:$r, CSImm12MulBy4:$i), - (SH2ADD (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)), +def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy4:$i), + (SH2ADD (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i)), GPR:$r)>; -def : Pat<(add GPR:$r, CSImm12MulBy8:$i), - (SH3ADD (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)), +def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy8:$i), + (SH3ADD (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i)), GPR:$r)>; -def : Pat<(mul GPR:$r, C3LeftShift:$i), +def : Pat<(mul (XLenVT GPR:$r), C3LeftShift:$i), (SLLI (SH1ADD GPR:$r, GPR:$r), (TrailingZerosXForm C3LeftShift:$i))>; -def : Pat<(mul GPR:$r, C5LeftShift:$i), +def : Pat<(mul (XLenVT GPR:$r), C5LeftShift:$i), (SLLI (SH2ADD GPR:$r, GPR:$r), (TrailingZerosXForm C5LeftShift:$i))>; -def : Pat<(mul GPR:$r, C9LeftShift:$i), +def : Pat<(mul (XLenVT GPR:$r), C9LeftShift:$i), (SLLI (SH3ADD GPR:$r, GPR:$r), (TrailingZerosXForm C9LeftShift:$i))>; @@ -1083,7 +1083,7 @@ (SLLIUW GPR:$rs1, uimm5:$shamt)>; def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)), (ADDUW GPR:$rs1, GPR:$rs2)>; -def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, X0)>; +def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, (i64 X0))>; def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), non_imm12:$rs2)), (SH1ADDUW GPR:$rs1, GPR:$rs2)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -230,8 +230,8 @@ // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// -class PatFpr64Fpr64 - : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>; +class PatFpr64Fpr64 + : Pat<(vt (OpNode FPR64:$rs1, FPR64:$rs2)), (Inst $rs1, $rs2)>; class PatFpr64Fpr64DynFrm : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>; @@ -259,7 +259,7 @@ def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; -def : PatFpr64Fpr64; +def : PatFpr64Fpr64; def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, @@ -284,8 +284,8 @@ // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // LLVM's fminnum and fmaxnum. // . -def : PatFpr64Fpr64; -def : PatFpr64Fpr64; +def : PatFpr64Fpr64; +def : PatFpr64Fpr64; /// Setcc @@ -296,7 +296,7 @@ def : PatFpr64Fpr64; def : PatFpr64Fpr64; -def Select_FPR64_Using_CC_GPR : SelectCC_rrirr; +def Select_FPR64_Using_CC_GPR : SelectCC_rrirr; /// Loads diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -302,8 +302,8 @@ def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; /// Generic pattern classes -class PatFpr32Fpr32 - : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; +class PatFpr32Fpr32 + : Pat<(vt (OpNode FPR32:$rs1, FPR32:$rs2)), (Inst $rs1, $rs2)>; class PatFpr32Fpr32DynFrm : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; @@ -311,7 +311,7 @@ let Predicates = [HasStdExtF] in { /// Float constants -def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; +def : Pat<(f32 (fpimm0)), (FMV_W_X (XLenVT X0))>; /// Float conversion operations @@ -330,7 +330,7 @@ def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; -def : PatFpr32Fpr32; +def : PatFpr32Fpr32; def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; // fmadd: rs1 * rs2 + rs3 @@ -352,8 +352,8 @@ // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // LLVM's fminnum and fmaxnum // . -def : PatFpr32Fpr32; -def : PatFpr32Fpr32; +def : PatFpr32Fpr32; +def : PatFpr32Fpr32; /// Setcc @@ -364,7 +364,7 @@ def : PatFpr32Fpr32; def : PatFpr32Fpr32; -def Select_FPR32_Using_CC_GPR : SelectCC_rrirr; +def Select_FPR32_Using_CC_GPR : SelectCC_rrirr; /// Loads diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td @@ -93,7 +93,7 @@ // Although the sexti32 operands may not have originated from an i32 srem, // this pattern is safe as it is impossible for two sign extended inputs to // produce a result where res[63:32]=0 and res[31]=1. -def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))), +def : Pat<(i64 (srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2)))), (REMW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtM, IsRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -15,7 +15,7 @@ //===----------------------------------------------------------------------===// def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", - SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>, + SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVec<1>, SDTCisInt<1>]>>; def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -132,7 +132,7 @@ DAGOperand xop_kind> : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), - (vop_type (SplatPatKind xop_kind:$rs2)))), + (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))), (!cast(instruction_name#_#suffix#_# vlmul.MX) vop_reg_class:$rs1, xop_kind:$rs2, @@ -227,7 +227,7 @@ foreach vti = AllIntegerVectors in { defvar instruction = !cast(instruction_name#_#kind#_#vti.LMul.MX); def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), - (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)), + (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))), cc)), SwapHelper<(instruction), (instruction vti.RegClass:$rs1), (instruction xop_kind:$rs2), @@ -395,7 +395,7 @@ // Handle VRSUB specially since it's the only integer binary op with reversed // pattern operands foreach vti = AllIntegerVectors in { - def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)), + def : Pat<(sub (vti.Vector (SplatPat (XLenVT GPR:$rs2))), (vti.Vector vti.RegClass:$rs1)), (!cast("PseudoVRSUB_VX_"# vti.LMul.MX) vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>; @@ -771,7 +771,7 @@ let Predicates = [HasStdExtV] in { foreach vti = AllIntegerVectors in { - def : Pat<(vti.Vector (SplatPat GPR:$rs1)), + def : Pat<(vti.Vector (SplatPat (XLenVT GPR:$rs1))), (!cast("PseudoVMV_V_X_" # vti.LMul.MX) GPR:$rs1, vti.AVL, vti.Log2SEW)>; def : Pat<(vti.Vector (SplatPat_simm5 simm5:$rs1)), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -247,8 +247,8 @@ //===----------------------------------------------------------------------===// /// Generic pattern classes -class PatFpr16Fpr16 - : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2)>; +class PatFpr16Fpr16 + : Pat<(vt (OpNode FPR16:$rs1, FPR16:$rs2)), (Inst $rs1, $rs2)>; class PatFpr16Fpr16DynFrm : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2, 0b111)>; @@ -256,7 +256,7 @@ let Predicates = [HasStdExtZfh] in { /// Float constants -def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>; +def : Pat<(f16 (fpimm0)), (FMV_H_X (XLenVT X0))>; /// Float conversion operations @@ -275,7 +275,7 @@ def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>; def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>; -def : PatFpr16Fpr16; +def : PatFpr16Fpr16; def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>; def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2), (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>; @@ -300,8 +300,8 @@ // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // LLVM's fminnum and fmaxnum // . -def : PatFpr16Fpr16; -def : PatFpr16Fpr16; +def : PatFpr16Fpr16; +def : PatFpr16Fpr16; /// Setcc @@ -312,7 +312,7 @@ def : PatFpr16Fpr16; def : PatFpr16Fpr16; -def Select_FPR16_Using_CC_GPR : SelectCC_rrirr; +def Select_FPR16_Using_CC_GPR : SelectCC_rrirr; /// Loads diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -117,13 +117,23 @@ def XLenVT : ValueTypeByHwMode<[RV32, RV64], [i32, i64]>; + +def XVEI8VT : ValueTypeByHwMode<[RV32, RV64], + [v4i8, v8i8]>; + +def XVEI16VT : ValueTypeByHwMode<[RV32, RV64], + [v2i16, v4i16]>; + +def XVEI32VT : ValueTypeByHwMode<[RV32, RV64], + [i32, v2i32]>; + def XLenRI : RegInfoByHwMode< [RV32, RV64], [RegInfo<32,32,32>, RegInfo<64,64,64>]>; // The order of registers represents the preferred allocation sequence. // Registers are listed in the order caller-save, callee-save, specials. -def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add +def GPR : RegisterClass<"RISCV", [XLenVT, XVEI8VT, XVEI16VT, XVEI32VT], 32, (add (sequence "X%u", 10, 17), (sequence "X%u", 5, 7), (sequence "X%u", 28, 31),