diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -467,6 +467,7 @@ case CK_Cooperlake: case CK_Cannonlake: case CK_IcelakeClient: + case CK_Rocketlake: case CK_IcelakeServer: case CK_Tigerlake: case CK_SapphireRapids: @@ -1314,6 +1315,7 @@ case CK_Tigerlake: case CK_SapphireRapids: case CK_IcelakeClient: + case CK_Rocketlake: case CK_IcelakeServer: case CK_Alderlake: case CK_KNL: diff --git a/clang/test/CodeGen/attr-target-mv.c b/clang/test/CodeGen/attr-target-mv.c --- a/clang/test/CodeGen/attr-target-mv.c +++ b/clang/test/CodeGen/attr-target-mv.c @@ -13,6 +13,7 @@ int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;} int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;} int __attribute__((target("arch=alderlake"))) foo(void) {return 11;} +int __attribute__((target("arch=rocketlake"))) foo(void) {return 12;} int __attribute__((target("default"))) foo(void) { return 2; } int bar() { @@ -97,6 +98,8 @@ // LINUX: ret i32 10 // LINUX: define{{.*}} i32 @foo.arch_alderlake() // LINUX: ret i32 11 +// LINUX: define{{.*}} i32 @foo.arch_rocketlake() +// LINUX: ret i32 12 // LINUX: define{{.*}} i32 @foo() // LINUX: ret i32 2 // LINUX: define{{.*}} i32 @bar() diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c --- a/clang/test/CodeGen/target-builtin-noerror.c +++ b/clang/test/CodeGen/target-builtin-noerror.c @@ -116,6 +116,7 @@ (void)__builtin_cpu_is("knl"); (void)__builtin_cpu_is("knm"); (void)__builtin_cpu_is("nehalem"); + (void)__builtin_cpu_is("rocketlake"); (void)__builtin_cpu_is("sandybridge"); (void)__builtin_cpu_is("shanghai"); (void)__builtin_cpu_is("silvermont"); diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c --- a/clang/test/Driver/x86-march.c +++ b/clang/test/Driver/x86-march.c @@ -72,6 +72,10 @@ // RUN: | FileCheck %s -check-prefix=icelake-client // icelake-client: "-target-cpu" "icelake-client" // +// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=rocketlake 2>&1 \ +// RUN: | FileCheck %s -check-prefix=rocketlake +// rocketlake: "-target-cpu" "rocketlake" +// // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-server 2>&1 \ // RUN: | FileCheck %s -check-prefix=icelake-server // icelake-server: "-target-cpu" "icelake-server" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -21,7 +21,7 @@ // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, +// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, @@ -33,7 +33,7 @@ // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, // X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, -// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, +// X86_64-SAME: icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, // X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, // X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, // X86_64-SAME: x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}} @@ -46,7 +46,7 @@ // TUNE_X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // TUNE_X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // TUNE_X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, +// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, // TUNE_X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // TUNE_X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // TUNE_X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, @@ -60,7 +60,7 @@ // TUNE_X86_64-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // TUNE_X86_64-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // TUNE_X86_64-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, +// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, // TUNE_X86_64-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // TUNE_X86_64-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // TUNE_X86_64-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1280,7 +1280,10 @@ // RUN: %clang -march=icelake-client -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ -// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M32 +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M32,CHECK_ICL_M32S +// RUN: %clang -march=rocketlake -m32 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M32,CHECK_RKL_M32S // CHECK_ICL_M32: #define __AES__ 1 // CHECK_ICL_M32: #define __AVX2__ 1 // CHECK_ICL_M32: #define __AVX512BITALG__ 1 @@ -1313,7 +1316,8 @@ // CHECK_ICL_M32: #define __RDPID__ 1 // CHECK_ICL_M32: #define __RDRND__ 1 // CHECK_ICL_M32: #define __RDSEED__ 1 -// CHECK_ICL_M32: #define __SGX__ 1 +// CHECK_ICL_M32S: #define __SGX__ 1 +// CHECK_RKL_M32S-NOT: #define __SGX__ 1 // CHECK_ICL_M32: #define __SHA__ 1 // CHECK_ICL_M32: #define __SSE2__ 1 // CHECK_ICL_M32: #define __SSE3__ 1 @@ -1337,7 +1341,10 @@ // RUN: %clang -march=icelake-client -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ -// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M64 +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M64,CHECK_ICL_M64S +// RUN: %clang -march=rocketlake -m64 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ICL_M64,CHECK_RKL_M64S // CHECK_ICL_M64: #define __AES__ 1 // CHECK_ICL_M64: #define __AVX2__ 1 // CHECK_ICL_M64: #define __AVX512BITALG__ 1 @@ -1370,7 +1377,8 @@ // CHECK_ICL_M64: #define __RDPID__ 1 // CHECK_ICL_M64: #define __RDRND__ 1 // CHECK_ICL_M64: #define __RDSEED__ 1 -// CHECK_ICL_M64: #define __SGX__ 1 +// CHECK_ICL_M64S: #define __SGX__ 1 +// CHECK_RKL_M64S-NOT: #define __SGX__ 1 // CHECK_ICL_M64: #define __SHA__ 1 // CHECK_ICL_M64: #define __SSE2__ 1 // CHECK_ICL_M64: #define __SSE3__ 1 diff --git a/compiler-rt/lib/builtins/cpu_model.c b/compiler-rt/lib/builtins/cpu_model.c --- a/compiler-rt/lib/builtins/cpu_model.c +++ b/compiler-rt/lib/builtins/cpu_model.c @@ -99,6 +99,7 @@ INTEL_COREI7_SAPPHIRERAPIDS, INTEL_COREI7_ALDERLAKE, AMDFAM19H_ZNVER3, + INTEL_COREI7_ROCKETLAKE, CPU_SUBTYPE_MAX }; @@ -384,6 +385,12 @@ *Subtype = INTEL_COREI7_SKYLAKE; break; + // Rocketlake: + case 0xa7: + CPU = "rocketlake"; + *Type = INTEL_COREI7; + *Subtype = INTEL_COREI7_ROCKETLAKE; + // Skylake Xeon: case 0x55: *Type = INTEL_COREI7; diff --git a/llvm/include/llvm/Support/X86TargetParser.h b/llvm/include/llvm/Support/X86TargetParser.h --- a/llvm/include/llvm/Support/X86TargetParser.h +++ b/llvm/include/llvm/Support/X86TargetParser.h @@ -98,6 +98,7 @@ CK_Cooperlake, CK_Cannonlake, CK_IcelakeClient, + CK_Rocketlake, CK_IcelakeServer, CK_Tigerlake, CK_SapphireRapids, diff --git a/llvm/include/llvm/Support/X86TargetParser.def b/llvm/include/llvm/Support/X86TargetParser.def --- a/llvm/include/llvm/Support/X86TargetParser.def +++ b/llvm/include/llvm/Support/X86TargetParser.def @@ -88,6 +88,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_SAPPHIRERAPIDS, "sapphirerapids") X86_CPU_SUBTYPE(INTEL_COREI7_ALDERLAKE, "alderlake") X86_CPU_SUBTYPE(AMDFAM19H_ZNVER3, "znver3") +X86_CPU_SUBTYPE(INTEL_COREI7_ROCKETLAKE, "rocketlake") #undef X86_CPU_SUBTYPE diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -708,6 +708,13 @@ *Subtype = X86::INTEL_COREI7_SKYLAKE; break; + // Rocketlake: + case 0xa7: + CPU = "rocketlake"; + *Type = X86::INTEL_COREI7; + *Subtype = X86::INTEL_COREI7_ROCKETLAKE; + break; + // Skylake Xeon: case 0x55: *Type = X86::INTEL_COREI7; diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -194,6 +194,7 @@ FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI | FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ; +constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX; constexpr FeatureBitset FeaturesICLServer = FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD; constexpr FeatureBitset FeaturesTigerlake = @@ -289,126 +290,143 @@ FeatureVAES | FeatureVPCLMULQDQ; constexpr ProcInfo Processors[] = { - // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. - { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, - // i386-generation processors. - { {"i386"}, CK_i386, ~0U, FeatureX87 }, - // i486-generation processors. - { {"i486"}, CK_i486, ~0U, FeatureX87 }, - { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, - { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, - { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, - // i586-generation processors, P5 microarchitecture based. - { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, - { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, - { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, - // i686-generation processors, P6 / Pentium M microarchitecture based. - { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, - { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, - { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, - { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, - { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, - { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, - { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, - { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, - // Netburst microarchitecture based processors. - { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, - { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, - { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, - { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, - // Core microarchitecture based processors. - { {"core2"}, CK_Core2, ~0U, FeaturesCore2 }, - { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, - // Atom processors - { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, - { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, - { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, - { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, - { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, - { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, - { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, - // Nehalem microarchitecture based processors. - { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, - { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, - // Westmere microarchitecture based processors. - { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, - // Sandy Bridge microarchitecture based processors. - { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, - { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, - // Ivy Bridge microarchitecture based processors. - { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, - { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, - // Haswell microarchitecture based processors. - { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, - { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, - // Broadwell microarchitecture based processors. - { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, - // Skylake client microarchitecture based processors. - { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, - // Skylake server microarchitecture based processors. - { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, - { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, - // Cascadelake Server microarchitecture based processors. - { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, - // Cooperlake Server microarchitecture based processors. - { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, - // Cannonlake client microarchitecture based processors. - { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, - // Icelake client microarchitecture based processors. - { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, - // Icelake server microarchitecture based processors. - { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, - // Tigerlake microarchitecture based processors. - { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, - // Sapphire Rapids microarchitecture based processors. - { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, - // Alderlake microarchitecture based processors. - { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake }, - // Knights Landing processor. - { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, - // Knights Mill processor. - { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, - // Lakemont microarchitecture based processors. - { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, - // K6 architecture processors. - { {"k6"}, CK_K6, ~0U, FeaturesK6 }, - { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, - { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, - // K7 architecture processors. - { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, - { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, - { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, - { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, - { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, - // K8 architecture processors. - { {"k8"}, CK_K8, ~0U, FeaturesK8 }, - { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, - { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, - { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, - { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, - { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, - { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, - { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, - { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, - // Bobcat architecture processors. - { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, - { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, - // Bulldozer architecture processors. - { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, - { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, - { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, - { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, - // Zen architecture processors. - { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, - { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, - { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 }, - // Generic 64-bit processor. - { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, - { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 }, - { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 }, - { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 }, - // Geode processors. - { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, + // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. + {{""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B}, + // i386-generation processors. + {{"i386"}, CK_i386, ~0U, FeatureX87}, + // i486-generation processors. + {{"i486"}, CK_i486, ~0U, FeatureX87}, + {{"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX}, + {{"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW}, + {{"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW}, + // i586-generation processors, P5 microarchitecture based. + {{"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B}, + {{"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B}, + {{"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX}, + // i686-generation processors, P6 / Pentium M microarchitecture based. + {{"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B}, + {{"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B}, + {{"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2}, + {{"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3}, + {{"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3}, + {{"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4}, + {{"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3}, + {{"yonah"}, CK_Yonah, ~0U, FeaturesPrescott}, + // Netburst microarchitecture based processors. + {{"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4}, + {{"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4}, + {{"prescott"}, CK_Prescott, ~0U, FeaturesPrescott}, + {{"nocona"}, CK_Nocona, ~0U, FeaturesNocona}, + // Core microarchitecture based processors. + {{"core2"}, CK_Core2, ~0U, FeaturesCore2}, + {{"penryn"}, CK_Penryn, ~0U, FeaturesPenryn}, + // Atom processors + {{"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell}, + {{"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell}, + {{"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont}, + {{"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont}, + {{"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont}, + {{"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus}, + {{"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont}, + // Nehalem microarchitecture based processors. + {{"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem}, + {{"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem}, + // Westmere microarchitecture based processors. + {{"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere}, + // Sandy Bridge microarchitecture based processors. + {{"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge}, + {{"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge}, + // Ivy Bridge microarchitecture based processors. + {{"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge}, + {{"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge}, + // Haswell microarchitecture based processors. + {{"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell}, + {{"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell}, + // Broadwell microarchitecture based processors. + {{"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell}, + // Skylake client microarchitecture based processors. + {{"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient}, + // Skylake server microarchitecture based processors. + {{"skylake-avx512"}, + CK_SkylakeServer, + FEATURE_AVX512F, + FeaturesSkylakeServer}, + {{"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer}, + // Cascadelake Server microarchitecture based processors. + {{"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake}, + // Cooperlake Server microarchitecture based processors. + {{"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake}, + // Cannonlake client microarchitecture based processors. + {{"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake}, + // Icelake client microarchitecture based processors. + {{"icelake-client"}, + CK_IcelakeClient, + FEATURE_AVX512VBMI2, + FeaturesICLClient}, + // Rocketlake microarchitecture based processors. + {{"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake}, + // Icelake server microarchitecture based processors. + {{"icelake-server"}, + CK_IcelakeServer, + FEATURE_AVX512VBMI2, + FeaturesICLServer}, + // Tigerlake microarchitecture based processors. + {{"tigerlake"}, + CK_Tigerlake, + FEATURE_AVX512VP2INTERSECT, + FeaturesTigerlake}, + // Sapphire Rapids microarchitecture based processors. + {{"sapphirerapids"}, + CK_SapphireRapids, + FEATURE_AVX512VP2INTERSECT, + FeaturesSapphireRapids}, + // Alderlake microarchitecture based processors. + {{"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake}, + // Knights Landing processor. + {{"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL}, + // Knights Mill processor. + {{"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM}, + // Lakemont microarchitecture based processors. + {{"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B}, + // K6 architecture processors. + {{"k6"}, CK_K6, ~0U, FeaturesK6}, + {{"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW}, + {{"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW}, + // K7 architecture processors. + {{"athlon"}, CK_Athlon, ~0U, FeaturesAthlon}, + {{"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon}, + {{"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP}, + {{"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP}, + {{"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP}, + // K8 architecture processors. + {{"k8"}, CK_K8, ~0U, FeaturesK8}, + {{"athlon64"}, CK_K8, ~0U, FeaturesK8}, + {{"athlon-fx"}, CK_K8, ~0U, FeaturesK8}, + {{"opteron"}, CK_K8, ~0U, FeaturesK8}, + {{"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3}, + {{"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3}, + {{"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3}, + {{"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10}, + {{"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10}, + // Bobcat architecture processors. + {{"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1}, + {{"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2}, + // Bulldozer architecture processors. + {{"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1}, + {{"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2}, + {{"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3}, + {{"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4}, + // Zen architecture processors. + {{"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1}, + {{"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2}, + {{"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3}, + // Generic 64-bit processor. + {{"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64}, + {{"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2}, + {{"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3}, + {{"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4}, + // Geode processors. + {{"geode"}, CK_Geode, ~0U, FeaturesGeode}, }; constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"}; diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -268,8 +268,6 @@ "Pad short functions">; def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", "Invalidate Process-Context Identifier">; -def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", - "Enable Software Guard Extensions">; def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", "Flush A Cache Line Optimized">; def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", @@ -653,8 +651,7 @@ list SKLAdditionalFeatures = [FeatureAES, FeatureXSAVEC, FeatureXSAVES, - FeatureCLFLUSHOPT, - FeatureSGX]; + FeatureCLFLUSHOPT]; list SKLTuning = [FeatureHasFastGather, FeatureMacroFusion, FeatureSlow3OpsLEA, @@ -754,7 +751,7 @@ list ICXFeatures = !listconcat(ICLFeatures, ICXAdditionalFeatures); - //Tigerlake + // Tigerlake list TGLAdditionalFeatures = [FeatureVP2INTERSECT, FeatureMOVDIRI, FeatureMOVDIR64B, @@ -763,7 +760,7 @@ list TGLFeatures = !listconcat(ICLFeatures, TGLAdditionalFeatures ); - //Sapphirerapids + // Sapphirerapids list SPRAdditionalFeatures = [FeatureAMXTILE, FeatureAMXINT8, FeatureAMXBF16, @@ -845,8 +842,7 @@ // Goldmont Plus list GLPAdditionalFeatures = [FeaturePTWRITE, - FeatureRDPID, - FeatureSGX]; + FeatureRDPID]; list GLPTuning = [FeatureUseGLMDivSqrtCosts, FeatureSlowTwoMemOps, FeatureSlowLEA, @@ -1307,6 +1303,8 @@ ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>; def : ProcModel<"icelake-client", SkylakeServerModel, ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; +def : ProcModel<"rocketlake", SkylakeServerModel, + ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; def : ProcModel<"icelake-server", SkylakeServerModel, ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>; def : ProcModel<"tigerlake", SkylakeServerModel, diff --git a/llvm/test/CodeGen/X86/cpus-intel.ll b/llvm/test/CodeGen/X86/cpus-intel.ll --- a/llvm/test/CodeGen/X86/cpus-intel.ll +++ b/llvm/test/CodeGen/X86/cpus-intel.ll @@ -38,6 +38,7 @@ ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty